CN107978606A - A kind of embedded flash memory technology integrating method - Google Patents
A kind of embedded flash memory technology integrating method Download PDFInfo
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- CN107978606A CN107978606A CN201711160947.9A CN201711160947A CN107978606A CN 107978606 A CN107978606 A CN 107978606A CN 201711160947 A CN201711160947 A CN 201711160947A CN 107978606 A CN107978606 A CN 107978606A
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- flash memory
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
Abstract
The invention discloses a kind of embedded flash memory technology integrating method, including：One substrate is provided, the substrate includes mutually isolated core device region, input/output device area and flash memory area, the first gate oxide and insulating layer are sequentially formed over the substrate, the insulating layer is performed etching, retain the insulating layer in the flash memory area, then the substrate is heat-treated, removes first gate oxide in the core device region afterwards, the second gate oxide is formed on the substrate in the core device region.The present invention is heat-treated after etching insulating layer, insulating layer is damaged when etching caused by the first gate oxide and is obtained certain reparation, the sidetracking of chemical substance when avoiding subsequently removing the first gate oxide, so as to reduce the leakage current of input/output device.
Description
Technical field
The present invention relates to IC manufacturing field, more particularly to a kind of embedded flash memory technology integrating method.
Background technology
In current semiconductor industry, IC products can be divided mainly into three major types type：Analog circuit, digital circuit
With D/A hybrid circuit, wherein memory device is an important kind in digital circuit.In recent years, it is embedding in memory device
The development for entering formula flash memory (embedded flash, Eflash) is particularly rapid.Embedded flash memory is mainly characterized by not powered
In the case of can keep the information of storage for a long time, and have the advantages that integrated level is high, access speed soon, be easy to wipe and rewrite,
Thus it is widely used in the multinomial field such as microcomputer, automated control.
Substantially flow is as follows as follows for existing embedded flash memory technology integrating method：
First, there is provided a substrate, the substrate include mutually isolated core device region, input/output device area and
Flash memory area, core devices (Core device), defeated are injected separately into core device region, input/output device area and flash memory area
Enter/output device (I/O device) and flash memory (Flash), between above-mentioned device region by fleet plough groove isolation structure carry out every
From；
Secondly, the first gate oxide is formed over the substrate, after removing the first gate oxide on the flash memory area,
ONO (Oxide/Nitride/Oxide, oxide/nitride/oxide) insulating layer is formed over the substrate；
Again, the ono dielectric layer on the flash memory area is retained, etching removes the ONO insulating layers beyond flash memory area；
Then, retain first gate oxide in the input/output device area and the ONO insulating layers of the flash memory area, lead to
Cross the first gate oxide that double grid (DG) wet etching removes core device region；
Finally, in two gate oxide of core device region growth regulation.
In above-mentioned integrated approach, ono dielectric layer etch step the first growth of gate oxide layer of input/output device area it
Afterwards, before double grid wet etching, since ono dielectric layer etching process can produce the Surface Physical Chemistry property of the first gate oxide
It is raw to influence, cause follow-up double grid photoresist and sticking for the first gate oxide not firm enough, cause during wet etching,
Chemical substance sidetracking enters first grid oxide layer, causes the first gate oxide edge thickness to be thinned, the leakage of input/output device
Electric current increases.
The content of the invention
The main object of the present invention is to provide a kind of embedded flash memory technology integrating method, repairs in insulating layer etching process
Caused by first grid oxide layer damage, the first gate oxide is thinned when avoiding subsequent etching, so as to reduce input/output
The leakage current of device.
To achieve the above object, the present invention provides a kind of embedded flash memory technology integrating method, comprises the following steps：
Step S01：A substrate is provided, the substrate includes mutually isolated core device region, input/output device area
And flash memory area；
Step S02：The first gate oxide and insulating layer are sequentially formed over the substrate；
Step S03：The insulating layer is performed etching, retains the insulating layer in the flash memory area；
Step S04：The substrate is heat-treated；
Step S05：Remove first gate oxide in the core device region；
Step S06：The second gate oxide is formed on substrate in the core device region.
Further, by shallow between core device region described in step S01, input/output device area and flash memory area
Groove isolation construction is isolated.
Further, in step S02, after first gate oxide is formed, formed before the insulating layer, institute
Embedded flash memory technology integrating method is stated to further include：Remove the first gate oxide in the flash memory area.
Further, in step S03, the insulating layer includes what is be made of oxide and nitride on the flash memory area
Sandwich construction.
Further, in step S04, the heat treatment includes steam oxidation technique in situ or annealing process.
Further, the step of steam oxidation technique in situ includes：
Environment in reaction chamber is set below to the environment of normal pressure；
The substrate is placed in the reaction chamber；
Mixed gas is passed through into the reaction chamber, raises the temperature of the reaction chamber, carries out oxidation reaction；
Stopping is passed through mixed gas, while inert gas is passed through into the reaction chamber, and anneals to the substrate
Processing.
Further, air pressure is less than 10Torr in the reaction chamber.
Further, the mixed gas includes O2And H2The mixed gas of composition.
Further, H in the mixed gas2Content be 1%-33%.
Further, the temperature in the reaction cavity is increased to 850 DEG C -1100 DEG C, and the time of the oxidation reaction is
15s-60s。
Further, the thickness of first gate oxide is more than the thickness of second gate oxide.
In embedded flash memory technology integrating method provided by the invention, sequentially form on substrate the first gate oxide with absolutely
Edge layer, performs etching the insulating layer, retains the insulating layer in the flash memory area, then carries out hot place to the substrate
Reason, removes first gate oxide in the core device region afterwards, and insulating layer causes the first gate oxide when etching
Damage, can be repaired through Overheating Treatment so that when avoiding subsequently removing the first gate oxide in the core device region,
Chemical substance sidetracking enters the first grid oxide layer in the input/output device area, prevents the input/output device area
The thickness of the first interior gate oxide is thinned, so as to reduce the leakage current of input/output device.
Brief description of the drawings
The flow chart for the embedded flash memory technology integrating method that Fig. 1 is provided by one embodiment of the invention；
Fig. 2 a~Fig. 2 g are each step structures for the embedded flash memory technology integrating method that one embodiment of the invention is provided
Schematic diagram；
Fig. 3 is the test curve figure of the I/O device creepages of existing process integrated approach production；
Fig. 4 is the test curve figure of I/O device creepages in the present embodiment.
Embodiment
To make present disclosure more clear understandable, below in conjunction with Figure of description, present disclosure is done into one
Walk explanation.Certainly the invention is not limited to the specific embodiment, and general replace well known to the skilled artisan in the art is also contained
Lid is within the scope of the present invention.
Secondly, the present invention has carried out detailed statement using schematic diagram, when present example is described in detail, for the ease of saying
Bright, schematic diagram is not partially enlarged in proportion to the general scale, should not be to this restriction as the present invention.
The core concept of the present invention is, the first gate oxide and insulating layer is sequentially formed on substrate, to the insulation
Layer performs etching, and retains the insulating layer in the flash memory area, then the substrate is heat-treated, afterwards described in removal
First gate oxide in core device region, the damage caused by the first gate oxide when insulating layer etches, at overheat
Comprehend to obtain certain reparation, so that when avoiding removing the first gate oxide in the core device region, chemical substance sidetracking
The first gate oxide into the input/output device area, prevents the first gate oxidation in the input/output device area
The thickness of layer is thinned, so as to reduce the leakage current of input/output device.
The flow chart for the embedded flash memory technology integrating method that Fig. 1 is provided by one embodiment of the invention, as shown in Figure 1,
The present invention proposes a kind of embedded flash memory technology integrating method, comprises the following steps：
Step S01：A substrate is provided, the substrate includes mutually isolated core device region, input/output device area
And flash memory area；
Step S02：The first gate oxide and insulating layer are sequentially formed over the substrate；
Step S03：The insulating layer is performed etching, retains the insulating layer in the flash memory area；
Step S04：The substrate is heat-treated；
Step S05：Remove first gate oxide in the core device region；
Step S06：The second gate oxide is formed on substrate in the core device region.
The flow chart for the embedded flash memory technology integrating method that Fig. 1 is provided by one embodiment of the invention, Fig. 2 a~Fig. 2 g
For each step structure diagram of embedded flash memory technology integrating method in one embodiment of the invention, please refer to Fig.1 shown in, and tie
Fig. 2 a~Fig. 2 g are closed, the embedded flash memory technology integrating method that the present invention will be described in detail proposes：
In step S01, there is provided a substrate 10, the substrate include mutually isolated core device region 20, input/output
Device region 30 and flash memory area 40, as shown in Figure 2 a.
The substrate 10 can be monocrystalline silicon, polysilicon, unformed silicon, silicon Germanium compound or silicon-on-insulator (SOI) etc.,
Can also be the compounds such as GaAs or gallium nitride, or other materials well known by persons skilled in the art.
Preferably, between the core device region 20, input/output device area 30 and flash memory area 40 by shallow trench every
Isolated from structure, such as pass through fleet plough groove isolation structure between the core device region 20 and input/output device area 30
50 are isolated, between the input/output device area 30 and the flash memory area 40 by fleet plough groove isolation structure 60 carry out every
From.Core devices are formed in the core device region 20 by modes such as ion implantings, in the input/output device area 30
Interior formation input/output device, forms flush memory device in the flash memory area 40.
In the present embodiment, an oxide layer 100 is formed on the substrate 10, the method for thermal oxide can be used to form institute
Oxide layer 100 is stated, chemical vapor deposition (Chemical Vapor Deposition, CVD), such as atmospheric pressure can also be used
Vapour deposition (APCVD) or low-pressure chemical vapor deposition (LPCVD) formation are learned, or those skilled in the art can also have been used
The other methods known are formed.
In step S02, the first gate oxide and insulating layer are sequentially formed over the substrate.
First, clean and remove the oxide layer 100, form the first gate oxide on the substrate 10 afterwards, for example,
The first gate oxide 201 is formed in the core device region 20, the first grid oxygen is formed in the input/output device area 30
Change layer 202, the first gate oxide 203 is formed in the flash memory area 40, as shown in Figure 2 b.
Then, photoresist layer is formed on the flash memory area 40, the photoresist layer is exposed and developed, is exposed
The flash memory area 40, forms patterned photoresist layer, then, using the patterned photoresist layer as mask, to described
One gate oxide 203 performs etching, and first gate oxide 203 in the flash memory area 40 is removed, finally by grey chemical industry
Skill removes photoresist layer, ultimately forms structure as shown in Figure 2 c.
Finally, insulating layer is formed on above-mentioned substrate 10, the insulating layer includes being made of oxide and nitride more
Rotating fields.Specifically, since the first gate oxide 203 in the flash memory area 40 has been etched, surface is substrate surface,
So the insulating layer formed has oxide-nitride-oxide three-decker, i.e. bottom oxide 301, intermediate layer nitridation
Thing 302 and top oxide 303, there has been the covering of the first gate oxide in other regions, so the insulating layer formed has nitridation
303 two layers of thing-oxide double-layer structure, i.e. intermediate layer nitride 302 and top oxide, such as Fig. 2 d institutes.
In step S03, the insulating layer is performed etching, retains the insulating layer in the flash memory area 40, is such as schemed
Shown in 2e.
The etching of nitride can have an impact the first gate oxide Surface Physical Chemistry property in the insulating layer, cause
Sticking not enough firmly for follow-up photoresist and the first gate oxide, causes during wet etching, chemical substance sidetracking into
Enter first grid oxide layer, cause the first gate oxide edge thickness to be thinned, the leakage current increase of input/output device.Therefore,
Continue step S04 in the present invention, to reduce the influence thereby resulted in.
In step S04, the substrate 10 is heat-treated.The heat treatment includes but not limited to vapor oxygen in situ
Chemical industry skill or annealing process.Illustrated below by taking steam oxidation in situ (ISSG) reaction as an example：
Air pressure in reaction cavity is first adjusted to the environment for being less than normal pressure, such as cavity air pressure is less than 10Torr (preferably
For 8Torr, 7Torr or 6Torr) etc., then the substrate is positioned on the disc holder in cavity, and be passed through at the same time by oxygen
Gas (O2) and hydrogen (H2) composition mixed gas.Wherein, it is described by O2And H2H in the mixed gas of composition2Content be 1%-
33%.The temperature in reaction cavity is raised to 850 DEG C -1100 DEG C (being preferably 900 DEG C, 1000 DEG C or 1100 DEG C etc.), to substrate
Surface is heated, described by O under high temperature atmosphere2And H2The mixed gas of composition chemically reacts, and generation largely has oxygen
Gas-phase activity free radical (including active oxygen atom (the O for the property changed2-), hydrone (H2O) and OH groups etc.), then the gas phase is lived
With substrate oxidation reaction occurs for free love base, and reaction 15s-60s (being preferably 15s, 30s or 55s etc.) stops being passed through afterwards described mixed
Gas is closed, while inert gas such as nitrogen (N is passed through in reaction chamber2) or argon gas (Ar) etc. (inert gas include but
It is not limited to N2Or Ar), by the temperature in reaction cavity be adjusted to 1000 DEG C -1100 DEG C (be preferably 1000 DEG C, 1030 DEG C or
1100 DEG C etc.), carry out the annealing of 15s-60s.
Steam oxidation (ISSG) technique in situ can the regrowth on the basis of original oxide (the first gate oxide)
Certain thickness oxide, therefore, it is necessary to by the first gate oxide described in S02 steps when using such a processing mode
Growth thickness is suitably thinned, to meet the top oxide of the requirement of gross thickness while flash memory area 40 by vapor oxygen in situ
Change (ISSG) certain thickness oxide of regrowth afterwards, therefore need the precalculated growth thickness in S02 steps.
If not selecting ISSG processing, a step annealing (Anneal) processing can be carried out, such a method is for original oxide layer
Thickness almost without influence.
In step S05, when removing first gate oxide 201 in the core device region 20, double grid need to be used
Light shield gets up the locality protection beyond the core device region, then by wet etching by the core device region 20
First gate oxide 201 removes, as shown in figure 2f.
Due to carrying out steam oxidation (ISSG) processing in situ to the substrate in step S04, generate substrate surface
Certain thickness oxide, avoids the sidetracking of chemical substance during wet etching, prevents in the input/output device area
The thickness of first gate oxide is thinned, so as to reduce the leakage current of input/output device (I/O device).
In step S06, the second gate oxide 400 is formed on the substrate 10 in the core device region 20, such as Fig. 2 g
It is shown, wherein the thickness of the second gate oxide layer is less than the thickness of first gate oxide.
Carry out grid (Poly), side wall (Spacer) isostructural formation, and source electrode and drain electrode successively after step S06
(Source/Drain) injection etc., forms final semiconductor devices.
The thickness of the first gate oxide formed to the present embodiment and existing process integrated approach contrasts, from sectional drawing
In it can be seen that, existing process integrated approach formed the first gate oxide thickness start apart from the place of edge about 104nm
Gradually thinning, most thin edge thickness is onlyNot as good as intermediate zone thicknessesHalf.And in the present embodiment
Silicon chip, the thickness of the first gate oxide of its most edge areIt is comparatively close to the thickness of intermediate region
It can also be seen that there is a situation where chemical substance sidetracking corrodes for the first gate oxide in the present embodiment from top view.
Fig. 3 is the test curve figure of input/output (I/O) device creepage of existing process integrated approach production.Fig. 4 is
The test curve figure of input/output (I/O) device creepage in the present embodiment.Used test sample is that operation voltage is 5V
NMOS (N-type metal-oxide semiconductor (MOS)) I/O devices.From figure 3, it can be seen that leaked with the sample of existing process integrated approach
Terminal voltage (Vd) starts obvious electric current occur after being more than 3.5V, and during more than 4.5V, current value Id (unit pA) is exponentially
Rise, as shown at 31 of figure 3.And the sample of the present embodiment, when drain terminal voltage Vd (unit V) is more than 3.5V, electric current does not go out
Now significantly increase, as shown in Figure 4.
In conclusion a kind of embedded flash memory technology integrating method provided by the invention, sequentially forms first on substrate
Gate oxide and insulating layer, perform etching the insulating layer, retain the insulating layer in the flash memory area, then to described
Substrate is heat-treated, and first gate oxide in the core device region is removed afterwards, to first when insulating layer etches
Damage, can be repaired through Overheating Treatment caused by gate oxide, so that when avoiding subsequently removing the first gate oxide, chemicals
Matter sidetracking enters the first grid oxide layer in the input/output device area, prevents the in the input/output device area
The thickness of one gate oxide is thinned, so as to reduce the leakage current of input/output device.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Scope.
Claims (11)
1. a kind of embedded flash memory technology integrating method, it is characterised in that comprise the following steps：
Step S01：A substrate is provided, the substrate includes mutually isolated core device region, input/output device area and sudden strain of a muscle
Deposit area；
Step S02：The first gate oxide and insulating layer are sequentially formed over the substrate；
Step S03：The insulating layer is performed etching, retains the insulating layer in the flash memory area；
Step S04：The substrate is heat-treated；
Step S05：Remove first gate oxide in the core device region；
Step S06：The second gate oxide is formed on substrate in the core device region.
2. embedded flash memory technology integrating method according to claim 1, it is characterised in that the core device region, defeated
Enter/isolated between output device area and flash memory area by fleet plough groove isolation structure.
3. embedded flash memory technology integrating method according to claim 1, it is characterised in that in step S02, formed
After first gate oxide, formed before the insulating layer, the embedded flash memory technology integrating method further includes：Remove
The first gate oxide in the flash memory area.
4. embedded flash memory technology integrating method according to claim 3, it is characterised in that the insulating layer is included by oxygen
Compound and the sandwich construction of nitride composition.
5. embedded flash memory technology integrating method according to claim 1, it is characterised in that in step S04, the heat
Processing includes steam oxidation technique in situ or annealing process.
6. embedded flash memory technology integrating method according to claim 5, it is characterised in that the original position steam oxidation
The step of technique, includes：
Environment in reaction chamber is set below to the environment of normal pressure；
The substrate is placed in the reaction chamber；
Mixed gas is passed through into the reaction chamber, raises the temperature of the reaction chamber, carries out oxidation reaction；
Stopping is passed through mixed gas, while inert gas is passed through into the reaction chamber, and the substrate is made annealing treatment.
7. embedded flash memory technology integrating method according to claim 6, it is characterised in that air pressure is small in the reaction chamber
In 10Torr.
8. embedded flash memory technology integrating method according to claim 6, it is characterised in that the mixed gas includes O2
And H2The mixed gas of composition.
9. embedded flash memory technology integrating method according to claim 8, it is characterised in that H in the mixed gas2's
Content is 1%-33%.
10. embedded flash memory technology integrating method according to claim 6, it is characterised in that the temperature in the reaction chamber
Degree is increased to 850 DEG C -1100 DEG C, and the time of the oxidation reaction is 15s-60s.
11. according to embedded flash memory technology integrating method according to any one of claims 1 to 10, it is characterised in that described
The thickness of first gate oxide is more than the thickness of the second gate oxide.
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