CN107978606B - Embedded flash memory process integration method - Google Patents
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- CN107978606B CN107978606B CN201711160947.9A CN201711160947A CN107978606B CN 107978606 B CN107978606 B CN 107978606B CN 201711160947 A CN201711160947 A CN 201711160947A CN 107978606 B CN107978606 B CN 107978606B
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- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
Abstract
The invention discloses an embedded flash memory process integration method, which comprises the following steps: providing a substrate, wherein the substrate comprises a core device area, an input/output device area and a flash memory area which are isolated from each other, sequentially forming a first gate oxide layer and an insulating layer on the substrate, etching the insulating layer, reserving the insulating layer in the flash memory area, then carrying out heat treatment on the substrate, then removing the first gate oxide layer in the core device area, and forming a second gate oxide layer on the substrate in the core device area. The invention carries out heat treatment after the insulating layer is etched, so that the damage to the first gate oxide layer during the etching of the insulating layer is repaired to a certain extent, and the sidetracking of chemical substances during the subsequent removal of the first gate oxide layer is avoided, thereby reducing the leakage current of an input/output device.
Description
Technical Field
The invention relates to the field of integrated circuit manufacturing, in particular to an embedded flash memory process integration method.
Background
In the current semiconductor industry, integrated circuit products can be divided into three major categories: analog circuits, digital circuits, and digital/analog hybrid circuits, where memory devices are an important type of digital circuit. In recent years, among memory devices, an embedded flash (Eflash) has been developed particularly rapidly. The embedded flash memory has the main characteristics of long-term storage information retention without power-on, and has the advantages of high integration level, high access speed, easy erasing and rewriting and the like, thereby being widely applied to various fields such as microcomputer, automatic control and the like.
The existing embedded flash memory process integration method comprises the following general flows:
firstly, providing a substrate, wherein the substrate comprises a Core device area, an input/output device area and a Flash memory area which are isolated from each other, respectively injecting a Core device (Core device), an input/output device (I/O device) and a Flash memory (Flash) into the Core device area, the input/output device area and the Flash memory area, and isolating the device areas through a shallow trench isolation structure;
secondly, forming a first gate Oxide layer on the substrate, and forming an Oxide-Nitride-Oxide (ONO) insulating layer on the substrate after removing the first gate Oxide layer on the flash memory area;
thirdly, reserving the ONO insulating layer on the flash memory area, and etching to remove the ONO insulating layer outside the flash memory area;
then, the first gate oxide layer of the input/output device area and the ONO insulating layer of the flash memory area are reserved, and the first gate oxide layer of the core device area is removed through double-gate (DG) wet etching;
and finally, growing a second gate oxide layer in the core device area.
In the integration method, after the first gate oxide layer in the input/output device area grows and before the dual-gate wet etching, the etching process of the ONO insulating layer can affect the surface physical and chemical properties of the first gate oxide layer, so that the subsequent dual-gate photoresist is not firmly adhered to the first gate oxide layer, chemical substances enter the first gate oxide layer through side drilling in the wet etching process, the thickness of the edge of the first gate oxide layer is reduced, and the leakage current of the input/output device is increased.
Disclosure of Invention
The invention mainly aims to provide an embedded flash memory process integration method, which repairs the damage to a first grid oxide layer in the etching process of an insulating layer, avoids the thinning of the first grid oxide layer in the subsequent etching process and reduces the leakage current of an input/output device.
In order to achieve the above object, the present invention provides an embedded flash memory process integration method, which comprises the following steps:
step S01: providing a substrate, wherein the substrate comprises a core device area, an input/output device area and a flash memory area which are isolated from each other;
step S02: sequentially forming a first gate oxide layer and an insulating layer on the substrate;
step S03: etching the insulating layer and reserving the insulating layer in the flash memory area;
step S04: performing heat treatment on the substrate;
step S05: removing the first gate oxide layer in the core device area;
step S06: and forming a second gate oxide layer on the substrate in the core device area.
Further, in step S01, the core device region, the input/output device region, and the flash memory region are isolated by a shallow trench isolation structure.
Further, in step S02, after the forming the first gate oxide layer and before the forming the insulating layer, the embedded flash memory process integration method further includes: and removing the first gate oxide layer in the flash memory area.
Further, in step S03, the insulating layer on the flash memory region includes a multi-layer structure composed of oxide and nitride.
Further, in step S04, the heat treatment includes an in-situ steam oxidation process or an annealing process.
Further, the steps of the in-situ steam oxidation process include:
setting the environment in the reaction cavity to be lower than the normal pressure;
placing the substrate in the reaction chamber;
introducing mixed gas into the reaction cavity, raising the temperature of the reaction cavity and carrying out oxidation reaction;
stopping introducing the mixed gas, introducing inert gas into the reaction chamber, and annealing the substrate.
Further, the pressure in the reaction chamber is less than 10 Torr.
Further, the mixed gas contains O2And H2The composition of the mixed gas.
Further, H in the mixed gas2The content of (A) is 1% -33%.
Further, the temperature in the reaction cavity is increased to 850-1100 ℃, and the time of the oxidation reaction is 15-60 s.
Further, the thickness of the first gate oxide layer is larger than that of the second gate oxide layer.
In the embedded flash memory process integration method provided by the invention, a first gate oxide layer and an insulating layer are sequentially formed on a substrate, the insulating layer is etched, the insulating layer in a flash memory area is reserved, then the substrate is subjected to heat treatment, then the first gate oxide layer in a core device area is removed, the damage to the first gate oxide layer during the etching of the insulating layer can be repaired through the heat treatment, so that when the first gate oxide layer in the core device area is subsequently removed, a chemical substance is prevented from laterally drilling into the first gate oxide layer in the input/output device area, the thickness of the first gate oxide layer in the input/output device area is prevented from being reduced, and the leakage current of an input/output device is reduced.
Drawings
Fig. 1 is a flowchart of an embedded flash memory process integration method according to an embodiment of the present invention;
fig. 2a to fig. 2g are schematic structural diagrams of steps of an embedded flash memory process integration method according to an embodiment of the invention;
FIG. 3 is a graph of a test plot of leakage current for an I/O device produced by a prior art integration method;
FIG. 4 is a test graph of the leakage current of the I/O device in this embodiment.
Detailed Description
In order to make the contents of the present invention more clearly understood, the contents of the present invention will be further described with reference to the accompanying drawings. The invention is of course not limited to this particular embodiment, and general alternatives known to those skilled in the art are also covered by the scope of the invention.
The present invention is described in detail with reference to the drawings, and for convenience of explanation, the drawings are not enlarged partially according to the general scale, and should not be construed as limiting the present invention.
The core idea of the invention is that a first gate oxide layer and an insulating layer are sequentially formed on a substrate, the insulating layer is etched, the insulating layer in a flash memory area is reserved, then the substrate is subjected to heat treatment, then the first gate oxide layer in a core device area is removed, and the damage to the first gate oxide layer caused by the etching of the insulating layer can be repaired to a certain extent through the heat treatment, so that when the first gate oxide layer in the core device area is removed, chemical substances are prevented from laterally drilling into the first gate oxide layer in the input/output device area, the thickness of the first gate oxide layer in the input/output device area is prevented from being reduced, and the leakage current of an input/output device is reduced.
Fig. 1 is a flowchart of an embedded flash memory process integration method according to an embodiment of the present invention, and as shown in fig. 1, the present invention provides an embedded flash memory process integration method, including the following steps:
step S01: providing a substrate, wherein the substrate comprises a core device area, an input/output device area and a flash memory area which are isolated from each other;
step S02: sequentially forming a first gate oxide layer and an insulating layer on the substrate;
step S03: etching the insulating layer and reserving the insulating layer in the flash memory area;
step S04: performing heat treatment on the substrate;
step S05: removing the first gate oxide layer in the core device area;
step S06: and forming a second gate oxide layer on the substrate in the core device area.
Fig. 1 is a flowchart of an embedded flash memory process integration method according to an embodiment of the present invention, and fig. 2a to 2g are schematic structural diagrams of steps of the embedded flash memory process integration method according to an embodiment of the present invention, and please refer to fig. 1 and refer to fig. 2a to 2g to describe in detail the embedded flash memory process integration method according to the present invention:
in step S01, a substrate 10 is provided, which includes a core device region 20, an input/output device region 30, and a flash memory region 40 isolated from each other, as shown in fig. 2 a.
The substrate 10 may be single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound, Silicon On Insulator (SOI), etc., gallium arsenide or gallium nitride, etc., or other materials known to those skilled in the art.
Preferably, the core device region 20, the input/output device region 30 and the flash memory region 40 are isolated by a shallow trench isolation structure, for example, the core device region 20 and the input/output device region 30 are isolated by a shallow trench isolation structure 50, and the input/output device region 30 and the flash memory region 40 are isolated by a shallow trench isolation structure 60. A core device is formed in the core device region 20, an input/output device is formed in the input/output device region 30, and a flash memory device is formed in the flash memory region 40 by ion implantation or the like.
In the present embodiment, an oxide layer 100 is formed on the substrate 10, the oxide layer 100 may be formed by a thermal oxidation method, or may be formed by Chemical Vapor Deposition (CVD), such as Atmospheric Pressure Chemical Vapor Deposition (APCVD) or Low Pressure Chemical Vapor Deposition (LPCVD), or may be formed by other methods known to those skilled in the art.
In step S02, a first gate oxide layer and an insulating layer are sequentially formed on the substrate.
First, the oxide layer 100 is cleaned and removed, and then a first gate oxide layer is formed on the substrate 10, for example, a first gate oxide layer 201 is formed in the core device region 20, a first gate oxide layer 202 is formed in the input/output device region 30, and a first gate oxide layer 203 is formed in the flash memory region 40, as shown in fig. 2 b.
Then, a photoresist layer is formed on the flash memory region 40, the photoresist layer is exposed and developed to expose the flash memory region 40, a patterned photoresist layer is formed, then, the first gate oxide layer 203 is etched by using the patterned photoresist layer as a mask, the first gate oxide layer 203 in the flash memory region 40 is removed, finally, the photoresist layer is removed through an ashing process, and finally, the structure shown in fig. 2c is formed.
Finally, an insulating layer including a multilayer structure composed of an oxide and a nitride is formed on the substrate 10. Specifically, since the first gate oxide layer 203 in the flash memory region 40 has been etched and has a surface that is a substrate, the formed insulating layer has a three-layer structure of oxide-nitride-oxide, i.e., a bottom layer oxide 301, a middle layer nitride 302 and a top layer oxide 303, and the other region is covered by the first gate oxide layer, so the formed insulating layer has a two-layer structure of nitride-oxide, i.e., two layers of the middle layer nitride 302 and the top layer oxide 303, as shown in fig. 2 d.
In step S03, the insulating layer is etched, and the insulating layer in the flash memory region 40 is remained, as shown in fig. 2 e.
The etching of the nitride in the insulating layer can affect the physical and chemical properties of the surface of the first gate oxide layer, so that the subsequent photoresist is not firmly adhered to the first gate oxide layer, chemical substances are laterally drilled into the first gate oxide layer in the wet etching process, the thickness of the edge of the first gate oxide layer is reduced, and the leakage current of an input/output device is increased. Therefore, step S04 is continued in the present invention to reduce the influence thereof.
In step S04, the substrate 10 is subjected to heat treatment. The thermal treatment includes, but is not limited to, an in-situ steam oxidation process or an annealing process. The in situ steam oxidation (ISSG) reaction is illustrated below as an example:
firstly, the pressure in the reaction cavity is adjusted to be lower than the normal pressure, for example, the pressure in the cavity is less than 10Torr (preferably 8Torr, 7Torr or 6Torr), and the like, then the substrate is placed on a disc support in the cavity, and oxygen (O) is introduced into the disc support2) And hydrogen (H)2) The composition of the mixed gas. Wherein, the compound is represented by2And H2Composition of H in mixed gas2The content of (A) is 1% -33%. Raising the temperature in the reaction chamber to 850-1100 deg.C (preferably 900 deg.C, 1000 deg.C or 1100 deg.C, etc.), heating the surface of the substrate, and making the substrate be in high-temperature atmosphere2And H2The mixed gas of the components is chemically reacted to generate a large amount of gas-phase active free radicals (including active oxygen atoms (O)2-) Water molecule (H)2O) and OH groups, etc.), then the gas-phase active free radicals and the substrate are subjected to oxidation reaction, the mixed gas is stopped to be introduced after the reaction is carried out for 15-60 s (preferably 15s, 30s, 55s, etc.), and meanwhile, inert gas such as nitrogen (N) is introduced into the reaction cavity2) Or argon (Ar) or the like (saidInert gases include, but are not limited to, N2Or Ar), adjusting the temperature in the reaction cavity to 1000-1100 ℃ (preferably 1000 ℃, 1030 ℃ or 1100 ℃, etc.), and carrying out annealing treatment for 15-60 s.
In-situ steam oxidation (ISSG) process can regrow oxide with a certain thickness on the basis of the original oxide (first gate oxide), so when using this processing method, the growth thickness of the first gate oxide in the step S02 needs to be reduced properly to meet the requirement of total thickness, and the top oxide of the flash memory region 40 regrows oxide with a certain thickness after in-situ steam oxidation (ISSG), so the growth thickness needs to be calculated in advance in the step S02.
If ISSG treatment is not selected, one-step annealing (Anneal) treatment can be performed, and the method has almost no influence on the thickness of the original oxide layer.
In step S05, when removing the first gate oxide 201 in the core device region 20, a double-gate mask is used to protect the region outside the core device region, and then the first gate oxide 201 in the core device region 20 is removed by wet etching, as shown in fig. 2 f.
In step S04, the substrate is subjected to in-situ steam oxidation (ISSG) to generate an oxide with a certain thickness on the surface of the substrate, thereby avoiding sidetracking of chemical substances during wet etching, and preventing the thickness of the first gate oxide layer in the I/O device region from being reduced, thereby reducing the leakage current of the I/O device (I/O device).
In step S06, a second gate oxide layer 400 is formed on the substrate 10 within the core device region 20, as shown in fig. 2g, wherein the thickness of the second gate oxide layer is smaller than the thickness of the first gate oxide layer.
After step S06, sequentially forming structures such as gate (Poly), Spacer (Spacer), and Source/Drain (Source/Drain), and the like, to form the final semiconductor device.
Comparing the thickness of the first gate oxide layer formed by the present embodiment and the prior art integration method, it can be seen from the cross-sectional view that the prior artThe thickness of the first gate oxide layer formed by the process integration method begins to become thinner at a position about 104nm away from the edge, and the thinnest edge thickness is only the thickness of the edge
Less than the thickness of the middle region
Half of that. In the silicon wafer of this embodiment, the thickness of the first gate oxide layer at the extreme edge is set to
Thickness relatively close to the intermediate region
It can also be seen from the top view that the first gate oxide layer in this embodiment has no chemical undercut.
FIG. 3 is a graph illustrating the leakage current of an input/output (I/O) device produced by a conventional process integration method. Fig. 4 is a test graph of leakage current of an input/output (I/O) device in the present embodiment. The test sample used was an NMOS (N-type metal oxide semiconductor) I/O device with an operating voltage of 5V. It can be seen from fig. 3 that the sample with the prior art integration method started to show significant current after the drain voltage (Vd) was greater than 3.5V, and that the current value Id (in pA) increased exponentially above 4.5V, as shown at 31 in fig. 3. However, in the sample of this embodiment, when the drain terminal voltage Vd (in V) is greater than 3.5V, the current does not increase significantly, as shown in fig. 4.
In summary, according to the embedded flash memory process integration method provided by the invention, the first gate oxide layer and the insulating layer are sequentially formed on the substrate, the insulating layer is etched, the insulating layer in the flash memory region is reserved, then the substrate is subjected to thermal treatment, then the first gate oxide layer in the core device region is removed, and the damage to the first gate oxide layer during the etching of the insulating layer can be repaired through the thermal treatment, so that the situation that chemical substances laterally penetrate into the first gate oxide layer in the input/output device region during the subsequent removal of the first gate oxide layer is avoided, the thickness of the first gate oxide layer in the input/output device region is prevented from being reduced, and the leakage current of the input/output device is reduced.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (11)
1. An embedded flash memory process integration method is characterized by comprising the following steps:
step S01: providing a substrate, wherein the substrate comprises a core device area, an input/output device area and a flash memory area which are isolated from each other;
step S02: sequentially forming a first gate oxide layer and an insulating layer on the substrate;
step S03: etching the insulating layer and reserving the insulating layer in the flash memory area;
step S04: performing heat treatment on the substrate;
step S05: removing the first gate oxide layer in the core device area, and reserving the first gate oxide layer in the input/output device area;
step S06: and forming a second gate oxide layer on the substrate in the core device area.
2. The method of claim 1, wherein the core device region, the input/output device region and the flash memory region are isolated from each other by shallow trench isolation structures.
3. The embedded flash memory process integration method of claim 1, wherein in step S02, after forming the first gate oxide layer and before forming the insulating layer, the embedded flash memory process integration method further comprises: and removing the first gate oxide layer in the flash memory area.
4. The method of claim 3, wherein the insulating layer comprises a multi-layer structure of oxide and nitride.
5. The method of claim 1, wherein the thermal treatment comprises an in-situ steam oxidation process or an annealing process in step S04.
6. The method of claim 5, wherein the step of the in-situ steam oxidation process comprises:
setting the environment in the reaction cavity to be lower than the normal pressure;
placing the substrate in the reaction chamber;
introducing mixed gas into the reaction cavity, raising the temperature of the reaction cavity and carrying out oxidation reaction;
stopping introducing the mixed gas, introducing inert gas into the reaction chamber, and annealing the substrate.
7. The embedded flash memory process integration method of claim 6, wherein a pressure in the reaction chamber is less than 10 Torr.
8. The embedded flash memory process integration method of claim 6, wherein the mixed gas comprises O2And H2The composition of the mixed gas.
9. The integrated process of claim 8, wherein H is in the mixed gas2The content of (A) is 1% -33%.
10. The embedded flash memory process integration method according to claim 6, wherein the temperature in the reaction chamber is raised to 850 ℃ -1100 ℃, and the time of the oxidation reaction is 15s-60 s.
11. The embedded flash memory process integration method as claimed in any one of claims 1 to 10, wherein the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer.
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| CN104681492B (en) * | 2013-11-26 | 2018-03-06 | 中芯国际集成电路制造(上海)有限公司 | Flash memory unit forming method |
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