KR20080002602A - Method for forming a gate of semiconductor device having dual gate - Google Patents

Method for forming a gate of semiconductor device having dual gate Download PDF

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KR20080002602A
KR20080002602A KR1020060061504A KR20060061504A KR20080002602A KR 20080002602 A KR20080002602 A KR 20080002602A KR 1020060061504 A KR1020060061504 A KR 1020060061504A KR 20060061504 A KR20060061504 A KR 20060061504A KR 20080002602 A KR20080002602 A KR 20080002602A
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film
gate
forming
polysilicon film
polysilicon
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KR1020060061504A
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Korean (ko)
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지연혁
서혜진
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes

Abstract

A method for forming a gate in a semiconductor device including a dual gate is provided to avoid generation of a pin hole by properly adjusting a process condition in an initial step for forming a metal electrode layer and by removing a native oxide layer formed on the surface of a polysilicon layer. A gate insulation layer(22) and a polysilicon layer(24) are formed on an NMOS region and a PMOS region in a semiconductor substrate(20). N-type or P-type impurity ions are implanted into the polysilicon layer in the NMOS and PMOS regions. A native oxide layer formed on the polysilicon layer is removed by using NF3 gas. The semiconductor substrate can be exposed to SiH4 gas wherein a silicon layer(26) having a thickness of 50-100 Å can be grown on the polysilicon layer. A metal electrode layer(28) is formed on the polysilicon layer. The metal electrode layer and the polysilicon layer are patterned.

Description

듀얼 게이트를 구비하는 반도체 소자의 게이트 형성방법{Method for forming a gate of semiconductor device having dual gate}Method for forming a gate of semiconductor device having dual gate

도 1은 종래의 반도체 소자의 듀얼 게이트 형성방법을 설명하기 위하여 도시한 단면도이다.1 is a cross-sectional view illustrating a conventional method of forming a dual gate of a semiconductor device.

도 2 및 도 3은 본 발명에 의한 반도체 소자의 듀얼 게이트 형성방법을 설명하기 위하여 도시한 단면도들이다.2 and 3 are cross-sectional views illustrating a method of forming a dual gate of a semiconductor device according to the present invention.

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 듀얼 게이트를 구비하는 반도체 소자의 게이트 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a gate of a semiconductor device having a dual gate.

최근 반도체 소자가 고집적화 및 고속화됨에 따라, 게이트절연막의 두께를 감소시키거나 폴리실리콘에 불순물을 도핑(doping)하거나 이온주입하여 게이트전극을 형성하던 종래의 방법으로는 소자의 특성요구에 부합할 수 없게 되었다. 이에 따라, NMOS 트랜지스터에는 기존의 N형 게이트전극을 형성하고 PMOS 트랜지스터에는 보론(Boron)과 같은 불순물이온을 주입하여 P형 게이트전극을 형성하는 듀얼 게이트(dual gate) 전극이 많이 사용되고 있다.Recently, as semiconductor devices have become more integrated and faster, conventional methods of reducing the thickness of the gate insulating layer, doping impurities into the polysilicon, or ion implantation to form the gate electrode cannot meet the characteristics requirements of the device. It became. Accordingly, conventional N-type gate electrodes are formed in NMOS transistors, and dual gate electrodes are commonly used in PMOS transistors to form P-type gate electrodes by implanting impurity ions such as boron.

도 1을 참조하여 종래의 방법에 의한 듀얼 게이트 형성방법을 간략히 설명하기로 한다.Referring to Figure 1 will be briefly described a dual gate forming method according to the conventional method.

먼저, 소자분리막(도시되지 않음)이 형성된 반도체기판(10) 위에 산화막을 성장시켜 게이트절연막(12)을 형성한 다음, 게이트전극 형성을 위한 폴리실리콘막(14)을 증착한다. P형 게이트전극이 형성될 영역을 한정하는 마스크패턴(도시되지 않음)을 상기 폴리실리콘막(14) 위에 형성한 다음 보론(B)을 이온주입한다. 상기 마스크패턴을 제거한 후에 N형 게이트전극이 형성될 영역을 한정하는 마스크패턴(도시되지 않음)을 형성하고 인(P)을 이온주입한다. 다음에, 상기 마스크패턴을 제거한 다음 주입된 상기 불순물이온들을 활성화시키기 위하여 소정 온도에서 반도체기판을 열처리한다. 이 열처리공정에서 상기 폴리실리콘막(14)의 결정화가 이루어진다.First, an oxide film is grown on a semiconductor substrate 10 on which an isolation layer (not shown) is formed to form a gate insulating film 12, and then a polysilicon film 14 for forming a gate electrode is deposited. A mask pattern (not shown) defining a region where a P-type gate electrode is to be formed is formed on the polysilicon film 14, and then boron B is ion implanted. After removing the mask pattern, a mask pattern (not shown) defining a region where the N-type gate electrode is to be formed is formed, and phosphorus (P) is ion implanted. Next, after removing the mask pattern, the semiconductor substrate is heat-treated at a predetermined temperature to activate the implanted impurity ions. In this heat treatment step, the polysilicon film 14 is crystallized.

다음에, 불산(HF) 또는 완충 산화막 식각액(BOE)을 이용하여 상기 폴리실리콘막(14)에 형성된 자연산화막을 제거하기 위한 세정공정을 실시한다. 다음, 상기 폴리실리콘막(14) 위에 텅스텐(W) 또는 텅스텐 실리사이드(WSi)막을 증착하여 금속 전극막(16)을 형성하고, 그 위에 질화막을 증착한 다음 패터닝하여 하드마스크층(18)를 형성한다. 상기 하드마스크층(18)을 마스크로 하여 상기 금속 전극막(16)과 폴리실리콘막(14)을 차례로 패터닝하여 게이트전극을 형성한다.Next, a cleaning process is performed to remove the native oxide film formed on the polysilicon film 14 using hydrofluoric acid (HF) or a buffer oxide film etching solution (BOE). Next, a tungsten (W) or tungsten silicide (WSi) film is deposited on the polysilicon film 14 to form a metal electrode film 16, a nitride film is deposited thereon, and then patterned to form a hard mask layer 18. do. The metal electrode layer 16 and the polysilicon layer 14 are sequentially patterned using the hard mask layer 18 as a mask to form a gate electrode.

이와 같이, 듀얼 게이트전극을 형성하기 위하여 폴리실리콘막에 불순물이온을 주입한 다음 이를 활성화시키기 위하여 열처리를 실시한다. P형 게이트를 형성하기 위한 보론(B)은 원자 직경이 작아서 이온주입공정 중 폴리실리콘막에 미치는 영향이 적다. 그러나, N형 게이트를 형성하기 위하여 주입하는 인(P)은 원자 직경이 실리콘(Si)과 유사한 수준으로, 이온주입공정 중 폴리실리콘막에 미치는 영향이 상대적으로 크다. 이로 인해 후속되는 열처리에 의한 폴리실리콘막의 결정화 단계에서 N형 이온이 주입된 폴리실리콘막의 표면은 매우 취약한 구조가 된다. 따라서, 게이트 전극막을 증착하기 전에 자연산화막을 제거하기 위한 목적으로 이루어지는 습식세정 공정에서 폴리실리콘의 그레인 경계면(grain boundary)을 통해 식각액이 침투하여 폴리실리콘막의 식각이 이루어져 핀-홀(pin-hole)이 발생된다. 이렇게 형성된 핀-홀은 후속되는 게이트 패터닝을 위한 건식식각 공정에서 게이트절연막(12)을 물리적으로 파괴하고 경우에 따라서 반도체기판(10)까지 손상시켜 소자의 특성을 열화시키는 문제점을 야기한다.As such, impurity ions are implanted into the polysilicon film to form a dual gate electrode, and then heat treatment is performed to activate the impurity ions. Boron (B) for forming a P-type gate has a small atomic diameter and therefore less influence on the polysilicon film during the ion implantation process. However, phosphorus (P) implanted to form an N-type gate has an atomic diameter similar to that of silicon (Si), and has a relatively large effect on the polysilicon film during the ion implantation process. As a result, the surface of the polysilicon film into which the N-type ion is implanted in the crystallization step of the polysilicon film by the subsequent heat treatment has a very fragile structure. Therefore, in the wet cleaning process for the purpose of removing the native oxide film before depositing the gate electrode film, the etching liquid penetrates through the grain boundary of the polysilicon to etch the polysilicon film, thereby forming a pin-hole. Is generated. The pin-holes thus formed physically destroy the gate insulating layer 12 in the subsequent dry etching process for gate patterning, and in some cases, damage the semiconductor substrate 10 to cause deterioration of device characteristics.

본 발명이 이루고자 하는 기술적 과제는, 듀얼 게이트 형성시 폴리실리콘막에 핀홀이 발생되는 것을 방지하여 소자의 특성이 열화되는 것을 방지할 수 있는 반도체 소자의 게이트 형성방법을 제공하는 것이다.An object of the present invention is to provide a method for forming a gate of a semiconductor device that can prevent the deterioration of the characteristics of the device by preventing the pinhole is generated in the polysilicon film when forming the dual gate.

본 발명에 의한 반도체 소자의 게이트 형성방법은, 반도체기판의 NMOS 영역 및 PMOS 영역에 게이트절연막과 폴리실리콘막을 형성하는 단계와, NMOS 영역 및 PMOS 영역의 폴리실리콘막에 N형 또는 P형 불순물이온을 주입하는 단계와, 삼불화질소(NF3) 가스를 이용하여 폴리실리콘막의 표면에 형성된 자연산화막을 제거하는 단계와, 폴리실리콘막 위에 금속 전극막을 형성하는 단계, 및 금속 전극막 및 폴리실리콘막을 패터닝하는 단계를 포함한다.The method for forming a gate of a semiconductor device according to the present invention includes forming a gate insulating film and a polysilicon film in an NMOS region and a PMOS region of a semiconductor substrate, and applying N-type or P-type impurity ions to a polysilicon film of an NMOS region and a PMOS region. Injecting, removing a natural oxide film formed on the surface of the polysilicon film using nitrogen trifluoride (NF 3 ) gas, forming a metal electrode film on the polysilicon film, and patterning the metal electrode film and the polysilicon film It includes a step.

본 발명에 있어서, 상기 폴리실리콘막 표면의 자연산화막을 제거하는 단계는, 상기 폴리실리콘막 위에 금속 전극막을 형성하는 단계와 동일한 챔버 내에서 인-시튜(in-situ)로 진행하는데, 500℃ ∼ 600℃의 온도, 0.5 ∼ 2.0Torr의 압력과 300 ∼ 500W의 알에프 전력(RF power)에서 진행하는 것이 바람직하다.In the present invention, the removing of the natural oxide film on the surface of the polysilicon film is performed in-situ in the same chamber as the step of forming the metal electrode film on the polysilicon film. It is preferable to proceed at a temperature of 600 ° C., a pressure of 0.5 to 2.0 Torr and an RF power of 300 to 500 W.

그리고, 상기 폴리실리콘막 표면의 자연산화막을 제거하는 단계 후에, 상기 반도체기판을 실란(SiH4) 가스에 노출시켜 상기 폴리실리콘막 위에 50Å ∼ 100Å 두께의 실리콘막을 성장시킬 수도 있다.After removing the native oxide film on the surface of the polysilicon film, the semiconductor substrate may be exposed to a silane (SiH 4 ) gas to grow a silicon film having a thickness of 50 kPa to 100 kPa on the polysilicon film.

그리고, 상기 반도체기판을 실란 가스에 노출시키는 단계에서, 디클로로실란(DCS) 가스를 이용하는 것이 바람직하다.In the exposing the semiconductor substrate to silane gas, it is preferable to use dichlorosilane (DCS) gas.

이하 첨부 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다. 그러나, 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 아래에서 상술하는 실시예들로 인해 한정되어지는 것으로 해석되어져서는 안된다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below.

도 2 및 도 3은 본 발명에 의한 듀얼 게이트를 구비하는 반도체 소자의 게이트 형성방법을 설명하기 위한 단면도들이다.2 and 3 are cross-sectional views illustrating a gate forming method of a semiconductor device having a dual gate according to the present invention.

도 2를 참조하면, 반도체기판(20)에 활성영역과 비활성영역을 한정하기 위한 소자분리막(도시되지 않음)을 통상적인 방법으로 형성한다. 이온주입 및 열처리 공 정을 통해 반도체기판에 웰(well)을 형성한다. 상기 반도체기판(20) 상에 산화막을 성장시켜 게이트절연막(22)을 형성한다. 이 게이트절연막(22)은 예를 들어 습식 혹은 건식 산화법을 이용하여 형성할 수 있다. 상기 게이트절연막(22) 위에, 예를 들어 저압 화학기상증착(Low Pressure Chemical Vapor Deposition; LPCVD) 방식을 사용하여 폴리실리콘막(24)을 형성한다.Referring to FIG. 2, an isolation layer (not shown) for defining active and inactive regions is formed on the semiconductor substrate 20 in a conventional manner. Wells are formed in the semiconductor substrate through ion implantation and heat treatment processes. An oxide film is grown on the semiconductor substrate 20 to form a gate insulating film 22. The gate insulating film 22 can be formed using, for example, a wet or dry oxidation method. On the gate insulating film 22, a polysilicon film 24 is formed using, for example, a Low Pressure Chemical Vapor Deposition (LPCVD) method.

다음에, P형 게이트전극이 형성될 영역을 한정하는 마스크패턴(도시되지 않음)을 상기 폴리실리콘막(24) 위에 형성한 다음 이 한정된 영역에 보론(B)을 이온주입한다. 상기 마스크패턴을 제거한 후, N형 게이트전극이 형성될 영역을 한정하는 마스크패턴(도시되지 않음)을 형성하고, 이 한정된 영역에 인(P)을 이온주입한다. 다음에, 상기 마스크패턴을 제거한 다음 주입된 불순물이온들을 활성화시키기 위하여 반도체기판을 열처리한다. 이 열처리 공정은 급속열처리(Rapid Thermal Anneal; RTA) 장비를 이용하여 950℃ 정도의 온도에서 20초간 진행한다. 언급한 바와 같이, N형 게이트를 형성하기 위하여 주입된 인(P) 이온은 실리콘과 유사한 원자직경을 갖는 원소로서, 이온주입 공정중 폴리실리콘막(24)에 물리적 충격을 주어 상기 열처리 공정을 통해 결정화가 이루어질 때 폴리실리콘막의 표면을 취약하게 만든다.Next, a mask pattern (not shown) defining a region in which the P-type gate electrode is to be formed is formed on the polysilicon film 24, and boron B is ion implanted into the limited region. After removing the mask pattern, a mask pattern (not shown) defining a region where the N-type gate electrode is to be formed is formed, and phosphorus (P) is ion-implanted into the limited region. Next, after removing the mask pattern, the semiconductor substrate is heat-treated to activate the implanted impurity ions. This heat treatment process is carried out for 20 seconds at a temperature of about 950 ℃ using a Rapid Thermal Anneal (RTA) equipment. As mentioned, phosphorus (P) ions implanted to form an N-type gate are elements having an atomic diameter similar to that of silicon, and give a physical impact to the polysilicon film 24 during the ion implantation process. It makes the surface of the polysilicon film brittle when crystallization takes place.

도 3을 참조하면, 상기 폴리실리콘막(24)과 후속 공정에서 형성될 금속 전극막의 접촉저항을 감소시키기 위하여 상기 폴리실리콘막(24)의 표면에 형성된 자연산화막을 제거하기 위한 세정을 실시한다. 이 세정공정은 종래의 불산(HF)과 같은 산화막 식각액을 사용하는 것이 아니라, 금속 전극막을 형성하기 위한 텅스텐(W) 또는 텅스텐 실리사이드(WSi) 증착 공정과 인-시튜(in-situ)로 이루어진다. 즉, 텅스텐(W) 또는 텅스텐 실리사이드(WSi)를 증착하기 위한 초기단계에서 증착 조건(recipe)을 적절히 조절하여 삼불화질소(NF3) 처리 공정을 실시한다. 보다 상세하게는, 금속 전극막 형성을 위한 텅스텐 실리사이드(WSi) 증착용 챔버(chamber)에 반도체기판을 로딩(loading)한 후에 500℃ ∼ 600℃의 온도, 0.5 ∼ 2.0Torr의 압력, 그리고 300 ∼ 500W의 알에프 전력(RF power)에서 삼불화질소(NF3) 가스를 주입한다. 그러면, 챔버내에 반응 에너지가 높은 라디칼(radical)이 형성되어 폴리실리콘막 표면의 산화막이 제거된다. 따라서, 산화막 식각액을 이용한 습식세정에서 그레인 경계면을 통해 식각액이 침투하여 핀홀이 발생되는 현상을 방지할 수 있다.Referring to FIG. 3, cleaning is performed to remove a native oxide film formed on the surface of the polysilicon film 24 in order to reduce the contact resistance between the polysilicon film 24 and the metal electrode film to be formed in a subsequent process. This cleaning process does not use an oxide etching solution such as conventional hydrofluoric acid (HF), but rather a tungsten (W) or tungsten silicide (WSi) deposition process for forming a metal electrode film and an in-situ. That is, in the initial stage for depositing tungsten (W) or tungsten silicide (WSi), a nitrogen trifluoride (NF 3 ) treatment process is performed by appropriately adjusting deposition conditions. More specifically, after loading a semiconductor substrate into a tungsten silicide (WSi) deposition chamber for forming a metal electrode film, the temperature of 500 ℃ to 600 ℃, pressure of 0.5 to 2.0 Torr, and 300 to Nitrogen trifluoride (NF 3 ) gas is injected at 500W RF power. Then, radicals with high reaction energy are formed in the chamber to remove the oxide film on the surface of the polysilicon film. Therefore, in the wet cleaning using the oxide etchant, the etching solution penetrates through the grain boundary to prevent pinholes from occurring.

다음에, 상기 챔버 내에 실란(SiH4) 또는 디클로로실란(DCS; SiH2Cl2)을 주입하여 반도체기판에 플로우(flow)시킴으로써, 자연산화막이 제거된 상기 폴리실리콘막(24)의 외벽에 50Å ∼ 100Å 정도 두께의 얇은 실리콘막이 성장되도록 한다. 상기 실리콘막(26)은 폴리실리콘막(24)의 취약한 표면구조를 강화하는 역할을 한다. Next, silane (SiH 4 ) or dichlorosilane (DCS; SiH 2 Cl 2 ) is injected into the chamber and flowed to a semiconductor substrate, whereby 50 Å is applied to the outer wall of the polysilicon film 24 from which the natural oxide film is removed. The thin silicon film having a thickness of about 100 kPa is grown. The silicon film 26 serves to reinforce the weak surface structure of the polysilicon film 24.

텅스텐 실리사이드(WSi)는 일반적으로 육불화텅스텐(WF6) 가스와 모노실란(SiH4) 또는 디클로로실란(SiH2Cl2) 가스를 사용하여 증착하는데, 본 발명에서와 같이 텅스텐 실리사이드를 증착하기 전에 반도체기판에 디클로로실란(SiH2Cl2)을 플로우시키면, 폴리실리콘막(24)의 표면을 강화하기 위한 실리콘막의 성장을 촉진시킬 수 있다.Tungsten silicide (WSi) is generally deposited using tungsten hexafluoride (WF 6 ) gas and monosilane (SiH 4 ) or dichlorosilane (SiH 2 Cl 2 ) gas, but before depositing tungsten silicide as in the present invention By flowing dichlorosilane (SiH 2 Cl 2 ) on the semiconductor substrate, it is possible to promote growth of a silicon film for strengthening the surface of the polysilicon film 24.

이어서, 상기 실리콘막(26) 위에 텅스텐 실리사이드(WSi)막을 증착하여 게이트 전극을 형성하기 위한 금속 전극막(28)을 형성하고, 그 위에 질화막을 증착한 다음 패터닝하여 하드마스크층(30)를 형성한다. 상기 하드마스크층(30)을 마스크로 하여 금속 전극막(28), 실리콘막(26) 및 폴리실리콘막(24)을 차례로 패터닝하면, 게이트절연막 또는 반도체기판의 손상없이 듀얼 게이트를 형성할 수 있다.Subsequently, a tungsten silicide (WSi) film is deposited on the silicon layer 26 to form a metal electrode film 28 for forming a gate electrode, and a nitride film is deposited thereon, followed by patterning to form a hard mask layer 30. do. By patterning the metal electrode film 28, the silicon film 26, and the polysilicon film 24 in sequence using the hard mask layer 30 as a mask, a dual gate can be formed without damaging the gate insulating film or the semiconductor substrate. .

상술한 본 발명에 의한 듀얼 게이트를 구비하는 반도체 소자의 게이트 형성방법에 의하면, 금속 전극막을 형성하기 위한 초기 단계에서 공정조건을 적절히 조절하여 폴리실리콘막의 표면에 형성된 자연산화막을 제거함으로써 산화막 식각액을 이용한 습식세정시 폴리실리콘막의 그레인 경계면을 통해 식각액이 침투하여 핀홀이 발생되는 현상을 방지할 수 있다. 따라서, 핀홀에 의한 게이트절연막의 파괴 또는 반도체기판 손상을 방지할 수 있으므로 소자의 특성이 열화되는 것을 방지할 수 있는 이점이 있다. 또한, 텅스텐 실리사이드 증착 전에, 텅스텐 실리사이드 증착 가스를 반도체기판에 플로우시킴으로써 폴리실리콘막의 표면을 강화시켜 소자의 전기적 특성을 향상시킬 수 있다.According to the gate forming method of a semiconductor device having a dual gate according to the present invention, by using the oxide etching solution by removing the natural oxide film formed on the surface of the polysilicon film by appropriately adjusting the process conditions in the initial stage for forming the metal electrode film During wet cleaning, the etching solution penetrates through the grain boundary of the polysilicon layer, thereby preventing the occurrence of pinholes. Therefore, it is possible to prevent breakage of the gate insulating film or damage to the semiconductor substrate by the pinholes, thereby preventing the deterioration of device characteristics. Further, before tungsten silicide deposition, the surface of the polysilicon film can be strengthened by flowing a tungsten silicide deposition gas to the semiconductor substrate to improve the electrical characteristics of the device.

이상 본 발명을 바람직한 실시예를 들어 상세하게 설명하였으나, 본 발명은 상기 실시예에 한정되지 않으며, 본 발명의 기술적 사상 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 여러 가지 변형이 가능함은 당연하다.Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.

Claims (7)

반도체기판의 NMOS 영역 및 PMOS 영역에 게이트절연막과 폴리실리콘막을 형성하는 단계;Forming a gate insulating film and a polysilicon film in the NMOS region and the PMOS region of the semiconductor substrate; NMOS 영역 및 PMOS 영역의 상기 폴리실리콘막에 N형 또는 P형 불순물이온을 주입하는 단계;Implanting N-type or P-type impurity ions into the polysilicon film in an NMOS region and a PMOS region; 삼불화질소(NF3) 가스를 이용하여 상기 폴리실리콘막의 표면에 형성된 자연산화막을 제거하는 단계;Removing the native oxide film formed on the surface of the polysilicon film by using nitrogen trifluoride (NF 3 ) gas; 상기 폴리실리콘막 위에 금속 전극막을 형성하는 단계; 및Forming a metal electrode film on the polysilicon film; And 상기 금속 전극막 및 폴리실리콘막을 패터닝하는 단계를 포함하는 것을 특징으로 하는 듀얼 게이트를 구비하는 반도체 소자의 게이트 형성방법.Patterning the metal electrode film and the polysilicon film; and forming a gate of a semiconductor device having a dual gate. 제1항에 있어서, The method of claim 1, 상기 폴리실리콘막 표면의 자연산화막을 제거하는 단계는,Removing the natural oxide film on the surface of the polysilicon film, 상기 폴리실리콘막 위에 금속 전극막을 형성하는 단계와 동일한 챔버 내에서 인-시튜(in-situ)로 진행되는 것을 특징으로 하는 듀얼 게이트를 구비하는 반도체 소자의 게이트 형성방법.And forming a metal electrode film on the polysilicon film in-situ in the same chamber as the step of forming a metal electrode film. 제2항에 있어서, The method of claim 2, 상기 폴리실리콘막 표면의 자연산화막을 제거하는 단계는,Removing the natural oxide film on the surface of the polysilicon film, 500℃ ∼ 600℃의 온도에서 진행하는 것을 특징으로 하는 듀얼 게이트를 구비하는 반도체 소자의 게이트 형성방법.A gate forming method of a semiconductor device having a dual gate, characterized in that it proceeds at a temperature of 500 ℃ to 600 ℃. 제3항에 있어서, 상기 폴리실리콘막 표면의 자연산화막을 제거하는 단계는,The method of claim 3, wherein the removing the natural oxide film on the surface of the polysilicon film comprises 0.5 ∼ 2.0Torr의 압력과 300 ∼ 500W의 알에프 전력(RF power)에서 진행하는 것을 특징으로 하는 듀얼 게이트를 구비하는 반도체 소자의 게이트 형성방법.A gate forming method of a semiconductor device having a dual gate, characterized in that it proceeds at a pressure of 0.5 to 2.0 Torr and RF power of 300 to 500W. 제1항에 있어서, The method of claim 1, 상기 폴리실리콘막 표면의 자연산화막을 제거하는 단계 후에, 상기 반도체기판을 실란(SiH4) 가스에 노출시키는 단계를 더 포함하는 것을 특징으로 하는 듀얼 게이트를 구비하는 반도체 소자의 게이트 형성방법.And after removing the native oxide film on the surface of the polysilicon film, exposing the semiconductor substrate to silane (SiH 4 ) gas. 제5항에 있어서,The method of claim 5, 상기 반도체기판을 실란(SiH4) 가스에 노출시키는 단계에서, 상기 폴리실리콘막 위에 50Å ∼ 100Å 두께의 실리콘막을 성장시키는 것을 특징으로 하는 듀얼 게이트를 구비하는 반도체 소자의 게이트 형성방법.Exposing the semiconductor substrate to a silane (SiH 4 ) gas, wherein a silicon film having a thickness of 50 kV to 100 kV is grown on the polysilicon film. 제5항에 있어서,The method of claim 5, 상기 반도체기판을 실란 가스에 노출시키는 단계에서, 디클로로실란(DCS) 가스를 이용하는 것을 특징으로 하는 듀얼 게이트를 구비하는 반도체 소자의 게이트 형성방법.Exposing the semiconductor substrate to silane gas, wherein a dichlorosilane (DCS) gas is used.
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Publication number Priority date Publication date Assignee Title
KR20170046085A (en) * 2015-10-20 2017-04-28 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Atomic layer deposition methods and structures thereof
CN107017157A (en) * 2015-10-20 2017-08-04 台湾积体电路制造股份有限公司 Atomic layer deposition method and its structure

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170046085A (en) * 2015-10-20 2017-04-28 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Atomic layer deposition methods and structures thereof
CN107017157A (en) * 2015-10-20 2017-08-04 台湾积体电路制造股份有限公司 Atomic layer deposition method and its structure
KR20190132615A (en) * 2015-10-20 2019-11-28 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Atomic layer deposition methods and structures thereof
CN107017157B (en) * 2015-10-20 2020-04-07 台湾积体电路制造股份有限公司 Atomic layer deposition method and structure thereof
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