CN103531498B - Wafer defect analytical system - Google Patents
Wafer defect analytical system Download PDFInfo
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- CN103531498B CN103531498B CN201310491945.3A CN201310491945A CN103531498B CN 103531498 B CN103531498 B CN 103531498B CN 201310491945 A CN201310491945 A CN 201310491945A CN 103531498 B CN103531498 B CN 103531498B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/24—Optical enhancement of defects or not directly visible states, e.g. selective electrolytic deposition, bubbles in liquids, light emission, colour change
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention provides a kind of wafer defect analytical system, comprise: wafer defect scan base, for storing the Defect Scanning figure of the wafer of the wafer-scanning board scanning in setting-up time, defective locations acquiring unit is used for sorting to described positional information, defective locations matching unit is used for mating the positional information of the positional information of a defect in the Defect Scanning figure of a wafer with a defect of the Defect Scanning figure of another wafer, and indicia matched group; The defect group analysis unit positional information obtaining defect group; Defect group association analytic unit, for carrying out correlation analysis to the positional information of the defect group between two wafers, flaw labeling unit is used for there is defect highlighted display in Defect Scanning figure of relevance.The present invention can be able to analyze wafer defect scintigram, marks highlighted for the defect that there is relevance, is convenient to investigate timely the situation of wafer ad-hoc location same defect, saves manpower and time.
Description
Technical field
The present invention relates to semiconductor technology manufacturing technology field, particularly wafer defect analytical system.
Background technology
At present, semiconductor manufacturing industry due to the process time of some technique board very short, once there is the situation causing process deviation because board is abnormal, be easy to cause considerable wafer to occur the defect of specific phase co-located, the wafer namely continuing through this technique board all can produce defect at same position.Chromatic aberration defect that the single-point defect out of focus of such as mask aligner, wafer support post deviation cause etc.The defective wafer that these process deviation boards often produce in the early stage is not easily found, and after continuing for some time, long lasting effect considerable wafer, can be found until defects count and coverage slowly become great talent.Prior art normally sends engineer once to check scanned whole wafers at set intervals, find out the situation of the specific phase co-located defect that wherein may exist, owing to being artificial judgment and manual operation, one is waste time and energy, and two is easily make mistakes.
Therefore, be necessary to provide a kind of wafer defect analytical system, wafer defect is analyzed.
Summary of the invention
The problem that the present invention solves is to provide a kind of wafer defect analytical system, can analyze, mark highlighted for the defect that there is relevance, be convenient to investigate timely the situation of wafer ad-hoc location same defect to wafer defect scintigram.
For solving the problem, a kind of wafer defect analytical system of the present invention, comprising:
Wafer defect scan base, for storing the Defect Scanning figure of the wafer of the wafer-scanning board scanning in setting-up time, described wafer at least comprises the wafer of two batches;
Defective locations acquiring unit, for obtaining the positional information of defect based on described Defect Scanning figure, and sort to described positional information, described positional information comprises abscissa and ordinate;
Defective locations matching unit, for mating the positional information of the positional information of a defect in the Defect Scanning figure of a wafer with a defect of the Defect Scanning figure of another wafer, and based on matching result indicia matched group; Described coupling comprises: the positional information of the abscissa of the positional information of a wafer defect and a defect of another wafer subtracted each other, and obtains abscissa difference; And the ordinate of a wafer and the ordinate of another wafer are subtracted each other, obtain ordinate difference, if the absolute value of described abscissa difference and ordinate difference is all within coordinate tolerance value, be then a defect group by a position flaw labeling of the Defect Scanning figure of a defect in the Defect Scanning figure of a described wafer and another wafer described;
Defect group analysis unit, defect group for obtaining based on described defective locations matching unit obtains the positional information of this defect group, the positional information of described defect group comprises: the abscissa of defect group and the ordinate of defect group, the abscissa of defect group is the mean value of the abscissa of two defects of described defect group, and the ordinate of described defect group is the mean value of the ordinate of two defects of described defect group;
Defect group association analytic unit, for carrying out correlation analysis to the positional information of the defect group between two wafers, described correlation analysis comprises: the difference of abscissa and the difference of ordinate that obtain the positional information of the defect group between two wafers, if the absolute value of described difference is less than allow relating value, then think that the defect group between two wafers exists relevance;
Flaw labeling unit, for based on the correlation analysis result between defect group association analytic unit, defect highlighted display in Defect Scanning figure of each wafer that the defect group defect group that there is relevance related to is corresponding.
Alternatively, described setting-up time is 0.5-5 hour.
Alternatively, the zero point of the coordinate system of described positional information is the center of circle of wafer.
Alternatively, described coordinate tolerance value is 2-8 micron.
Alternatively, allow described in that relating value is 2-8 micron.
Alternatively, described Defect Correlation group analysis unit also for can both be formed in a defect and multiple defects of another wafer of a wafer mate group time, from multiple defects of another wafer described, select a defect to be formed with a defect of a described wafer based on screening principle and mate group.
Compared with prior art, the present invention has the following advantages:
A kind of wafer defect analytical system is provided, can be able to analyzes wafer defect scintigram, mark highlighted for the defect that there is relevance, be convenient to investigate timely the situation of wafer ad-hoc location same defect, save manpower and time.
Accompanying drawing explanation
Fig. 1 is wafer defect analytical system structural representation of the present invention.
Embodiment
The problem that the present invention solves is to provide a kind of wafer defect analytical system, can analyze, mark highlighted for the defect that there is relevance, be convenient to investigate timely the situation of wafer ad-hoc location same defect to wafer defect scintigram.
For solving the problem, a kind of wafer defect analytical system of the present invention, comprising:
Wafer defect scan base, for storing the Defect Scanning figure of the wafer of the wafer-scanning board scanning in setting-up time, described wafer at least comprises the wafer of two batches;
Defective locations acquiring unit, for obtaining the positional information of defect based on described Defect Scanning figure, and sort to described positional information, described positional information comprises abscissa and ordinate;
Defective locations matching unit, for mating the positional information of the positional information of a defect in the Defect Scanning figure of a wafer with a defect of the Defect Scanning figure of another wafer, and based on matching result indicia matched group; Described coupling comprises: the positional information of the abscissa of the positional information of a wafer defect and a defect of another wafer subtracted each other, and obtains abscissa difference; And the ordinate of a wafer and the ordinate of another wafer are subtracted each other, obtain ordinate difference, if the absolute value of described abscissa difference and ordinate difference is all within coordinate tolerance value, be then a defect group by a position flaw labeling of the Defect Scanning figure of a defect in the Defect Scanning figure of a described wafer and another wafer described;
Defect group analysis unit, defect group for obtaining based on described defective locations matching unit obtains the positional information of this defect group, the positional information of described defect group comprises: the abscissa of defect group and the ordinate of defect group, the abscissa of defect group is the mean value of the abscissa of two defects of described defect group, and the ordinate of described defect group is the mean value of the ordinate of two defects of described defect group;
Defect group association analytic unit, for carrying out correlation analysis to the positional information of the defect group between two wafers, described correlation analysis comprises: the difference of abscissa and the difference of ordinate that obtain the positional information of the defect group between two wafers, if the absolute value of described difference is less than allow relating value, then think that the defect group between two wafers exists relevance;
Flaw labeling unit, for based on the correlation analysis result between defect group association analytic unit, defect highlighted display in Defect Scanning figure of each wafer that the defect group defect group that there is relevance related to is corresponding.
Below in conjunction with specific embodiment, technical scheme of the present invention is described in detail.In order to technical scheme of the present invention is described better, please refer to the wafer defect analytical system structural representation of the present invention shown in Fig. 1.
As an embodiment, store the Defect Scanning figure of the wafer of the wafer-scanning board scanning in setting-up time in wafer defect scan base 10, described wafer at least comprises the wafer of two batches.Described wafer-scanning board is existing wafer-scanning board, and it can carry out Defect Scanning to crystal column surface, and obtains Defect Scanning figure.As an embodiment, the setting-up time in described wafer defect scintigram is 0.5-5 hour, and such as described setting-up time can be 0.5 hour, 1 hour, 2 hours, 3 hours, 4 hours even 5 hours, in the present embodiment, and described setting-up time is 1 hour.As an embodiment, the wafer of described wafer-scanning board scanning comprises: No. 1 wafer of first batch, No. 1 wafer of second batch, No. 3 and No. 4 wafers of the 3rd batch, certainly, in other examples, the wafer of described wafer wafer-scanning board scanning can for having more wafer in more multiple batches of and each batch.
Defective locations acquiring unit 20 for obtaining the positional information of defect based on described Defect Scanning figure, and sorts to described positional information, and described positional information comprises abscissa and ordinate.In the present embodiment, the zero point of the coordinate system of described positional information is the center of circle of wafer.Certainly, in other examples, the zero point of the coordinate system of described positional information also can be any point on wafer.As an embodiment, the method of described positional information sequence is: first arrange defect from toward large order according to the abscissa of defect, then arrange from toward large order according to the ordinate of defect, certainly, the aligning method of described positional information also can carry out according to other sortord, does not do meaning explanation at this.
Defective locations matching unit 30 for mating the positional information of the positional information of a defect in the Defect Scanning figure of a wafer with a defect of the Defect Scanning figure of another wafer, and based on matching result indicia matched group.
Described Defect Correlation group analysis unit 40 also for can both be formed in a defect and multiple defects of another wafer of a wafer mate group time, from multiple defects of another wafer described, select a defect to be formed with a defect of a described wafer based on screening principle and mate group.
As an embodiment, the present invention compares for two defects of No. 1 wafer and 2 wafers and is described, described coupling comprises: by a defect (defect 1 of a wafer (No. 1 wafer of such as first batch), its abscissa and ordinate are respectively X1 and Y1) positional information (X1, a defect (defect 2 of abscissa X1 Y1) and another wafer (No. 1 wafer of such as second batch), its abscissa and ordinate are respectively X2 and Y2) positional information X2 subtract each other, obtain abscissa difference (i.e. X1-X2); And the ordinate Y2 of the ordinate Y1 of a wafer (i.e. No. 1 wafer of first batch) and another wafer (i.e. No. 1 wafer of second batch) is subtracted each other, obtain ordinate difference (i.e. Y1-Y2), if the absolute value of described abscissa difference and the absolute value of ordinate difference are all within coordinate tolerance value, be then a defect group by a position flaw labeling of the Defect Scanning figure of a defect in the Defect Scanning figure of a described wafer and another wafer described.The scope of described coordinate tolerance value is 2-8 micron, and such as described coordinate tolerance value can be 1 micron, 2 microns, 3 microns, 4 microns, 5 microns, 6 microns, 7 microns, even 8 micron.Usually, described coordinate tolerance value is less, and the matching degree for the position defect of two wafers requires higher, and in a preferred embodiment of the invention, the scope of described coordinate tolerance value is 2-5 micron, and such as described coordinate tolerance value can be 5 microns.When the absolute value of difference of the X value of a defect of a wafer and a defect of another wafer and the absolute value of the difference of Y value are all within coordinate tolerance value, be then coupling group by these two flaw labelings.Adopt and in this way the defect on all to the defect on each wafer and all the other wafers is mated one by one, the situation of the coupling group that mark is whole.
Match when a defect of a wafer of batch and a wafer of another batch exist multiple defect, there is the distance between multiple defect in a wafer of the defect and another batch that then calculate a wafer of described batch, select with the distance of a defect of a wafer of batch minimum from multiple defects of a wafer of another batch described, formed with a defect of a wafer of described batch and mate group.When having multiple minimum value in described distance, then select multiple defects of multiple wafers of a wafer of a wafer from another batch described and select the defect of ordinate maximum to be formed with a defect of a wafer of described batch to mate group.As an embodiment, if when its abscissa value of defect 1(of a wafer of batch (No. 1 wafer of such as first batch) is X1, ordinate value is Y1) there is multiple defect with the wafer (No. 2 wafers of such as second batch) of another batch and to match (the defect 1 on such as No. 2 wafers, defect 2 and defect 3, wherein the abscissa of defect 1 and ordinate are X2 and Y2, the abscissa of defect 2 and ordinate are X3 and Y3, the abscissa of defect 3 and ordinate are X4 and Y4, the defect that on No. 2 wafers getting second batch, No. 1 wafer middle distance of each defect and first batch is minimum, No. 1 wafer with first batch forms and mates group.In the present embodiment, calculating described distance is: the distance L2=√ ((X1-X2) of the defect 1 on second batch of No. 2 wafer and No. 1 wafer of first batch
2+ (Y1-Y2)
2), the distance L2=√ ((X1-X3) of the defect 2 on second batch of No. 2 wafer and No. 1 wafer of first batch
2+ (Y1-Y3)
2), the distance L3=√ ((X1-X4) of the defect 3 on second batch of No. 2 wafer and No. 1 wafer of first batch
2+ (Y1-Y4)
2), as an embodiment, if when in above-mentioned distance L1, L2 and L3, only have a minimum value L3, then the defect 3 marking the second lot number No. 2 wafers is formed with the defect 1 of No. 1 wafer of first batch mates group; If in above-mentioned distance L1, L2 and L3, there are two minimum value L2 and L3, then therefrom select defect ordinate value in No. 2 wafers of second batch larger, formed with the defect 1 of No. 1 wafer of first batch and mate group.
Defect group analysis unit 50 obtains the positional information of this defect group for the defect group obtained based on described defective locations matching unit, and the positional information of this defect group carries out correlation analysis for defect group association analysis unit 50.Particularly, the positional information of described defect group comprises: the abscissa of defect group and the ordinate of defect group, the abscissa of defect group is the mean value of the abscissa of two defects of described defect group, and the ordinate of described defect group is the mean value of the ordinate of two defects of described defect group.
Defect group association analytic unit 60 is for carrying out correlation analysis to the positional information of the defect group between two wafers, described correlation analysis comprises: the difference of abscissa and the difference of ordinate that obtain the positional information of the defect group between two wafers, if the absolute value of described difference is less than allow relating value, then think that the defect group between two wafers exists relevance.Describedly allow that relating value is 2-8 micron.As preferred embodiment, described in allow relating value for 2-5 micron.
Flaw labeling unit 70, for based on the correlation analysis result between defect group association analytic unit 60, defect highlighted display in Defect Scanning figure of each wafer that the defect group defect group that there is relevance related to is corresponding.
To sum up, the invention provides a kind of wafer defect analytical system, can be able to analyze wafer defect scintigram, mark highlighted for the defect that there is relevance, be convenient to investigate timely the situation of wafer ad-hoc location same defect, save manpower and time.
Therefore, above-mentioned preferred embodiment is only and technical conceive of the present invention and feature is described, its object is to person skilled in the art can be understood content of the present invention and implement according to this, can not limit the scope of the invention with this.All equivalences done according to Spirit Essence of the present invention change or modify, and all should be encompassed within protection scope of the present invention.
Claims (6)
1. a wafer defect analytical system, is characterized in that, comprising:
Wafer defect scan base, for storing the Defect Scanning figure of the wafer of the wafer-scanning board scanning in setting-up time, described wafer at least comprises the wafer of two batches;
Defective locations acquiring unit, for obtaining the positional information of defect based on described Defect Scanning figure, and sort to described positional information, described positional information comprises abscissa and ordinate;
Defective locations matching unit, for mating the positional information of the positional information of a defect in the Defect Scanning figure of a wafer with a defect of the Defect Scanning figure of another wafer, and based on matching result indicia matched group; Described coupling comprises: subtracted each other by the abscissa of the positional information of the abscissa of the positional information of a wafer defect and a defect of another wafer, obtains abscissa difference; And the ordinate of a wafer and the ordinate of another wafer are subtracted each other, obtain ordinate difference, if the absolute value of described abscissa difference and ordinate difference is all within coordinate tolerance value, be then a defect group by a position flaw labeling of the Defect Scanning figure of a defect in the Defect Scanning figure of a described wafer and another wafer described;
Defect group analysis unit, defect group for obtaining based on described defective locations matching unit obtains the positional information of this defect group, the positional information of described defect group comprises: the abscissa of defect group and the ordinate of defect group, the abscissa of defect group is the mean value of the abscissa of two defects of described defect group, and the ordinate of described defect group is the mean value of the ordinate of two defects of described defect group;
Defect group association analytic unit, for carrying out correlation analysis to the positional information of the defect group between two wafers, described correlation analysis comprises: the difference of abscissa and the difference of ordinate that obtain the positional information of the defect group between two wafers, if the absolute value of the difference of described abscissa and the difference of ordinate is less than allow relating value, then think that the defect group between two wafers exists relevance;
Flaw labeling unit, for based on the correlation analysis result between defect group association analytic unit, the defect of each wafer that the defect group defect group that there is relevance related to is corresponding marks Defect Scanning figure is highlighted.
2. wafer defect analytical system as claimed in claim 1, it is characterized in that, described setting-up time is 0.5-5 hour.
3. wafer defect analytical system as claimed in claim 1, it is characterized in that, the zero point of the coordinate system of described positional information is the center of circle of wafer.
4. wafer defect analytical system as claimed in claim 1, it is characterized in that, described coordinate tolerance value is 2-8 micron.
5. wafer defect analytical system as claimed in claim 1, is characterized in that, described in allow that relating value is 2-8 micron.
6. wafer defect analytical system as claimed in claim 1, it is characterized in that, described defect group association analytic unit also for can both be formed in a defect and multiple defects of another wafer of a wafer mate group time, from multiple defects of another wafer described, select a defect to be formed with a defect of a described wafer based on screening principle and mate group.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109065467A (en) * | 2018-08-31 | 2018-12-21 | 上海华力微电子有限公司 | Wafer defect detection system and detection method and computer storage medium |
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| CN104022050A (en) * | 2014-04-22 | 2014-09-03 | 上海华力微电子有限公司 | Detection method for repeated position defects in batch of wafers |
| CN103970938B (en) * | 2014-04-22 | 2017-07-28 | 上海华力微电子有限公司 | Wafer sort result figure marks amending method |
| CN110223929B (en) * | 2019-05-07 | 2022-01-04 | 徐州鑫晶半导体科技有限公司 | Method for determining defect source of wafer |
| KR20220010509A (en) * | 2019-05-07 | 2022-01-25 | 쉬저우 신징 세미컨덕터 테크놀러지 컴퍼니 리미티드 | Method and system for automatic detection and control of defects on wafer |
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| JP3566470B2 (en) * | 1996-09-17 | 2004-09-15 | 株式会社日立製作所 | Pattern inspection method and apparatus |
| CN100590832C (en) * | 2007-11-28 | 2010-02-17 | 上海华虹Nec电子有限公司 | Method for detecting silicon chip edge automatically |
| CN101872715B (en) * | 2009-04-21 | 2012-02-08 | 南茂科技股份有限公司 | Wafer defect marking system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109065467A (en) * | 2018-08-31 | 2018-12-21 | 上海华力微电子有限公司 | Wafer defect detection system and detection method and computer storage medium |
| CN109065467B (en) * | 2018-08-31 | 2020-11-13 | 上海华力微电子有限公司 | Wafer defect detection system and method and computer storage medium |
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