CN103531492B - 用于半导体晶圆的混合接合系统及方法 - Google Patents
用于半导体晶圆的混合接合系统及方法 Download PDFInfo
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- CN103531492B CN103531492B CN201210382930.9A CN201210382930A CN103531492B CN 103531492 B CN103531492 B CN 103531492B CN 201210382930 A CN201210382930 A CN 201210382930A CN 103531492 B CN103531492 B CN 103531492B
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Abstract
本发明公开了用于半导体晶圆的混合接合系统和方法。在一个实施例中,用于半导体晶圆的混合接合系统包括室和多个设置在该室内的副室。机械夹持器设置在该室内,适用于在多个副室之间移动室内的多个半导体晶圆。多个副室包括:适用于从多个半导体晶圆去除保护层的第一副室,以及适用于在将多个半导体晶圆混合接合在一起之前激活多个半导体晶圆的顶面的第二副室。多个副室还包括适用于对准多个半导体晶圆和将多个半导体晶圆混合接合在一起的第三副室。
Description
相关申请的交叉参考:
本申请涉及以下共同待决和普通转让的专利申请,该专利申请的全部公开内容通过引用结合到本文中:该申请序号为13/488,745,于2012年6月5日提交,标题为“ThreeDimensionalIntegratedCircuitStructuresandHybridBondingMethodsforSemiconductorWafers”。
技术领域
本发明涉及用于半导体晶圆的接合系统及方法。
背景技术
半导体器件被使用在各种电子应用中,诸如,个人计算机、手机、数码相机,以及其他电子设备中。通常通过在半导体衬底上方连续地沉积绝缘或介电层、导电层、以及半导体材料层,并且使用光刻图案化各种材料层从而形成电路部件及其上的元件来制造半导体器件。通常在单个半导体晶圆上制造有数十或数百个集成电路并且通过在两个集成电路之间沿着切割线进行切割来将晶圆上的各个管芯分离成单个的。通常是在例如,多芯片模式下或其他类型的封装方式下分别封装各个管芯。
半导体工业通过不断减小最小部件尺寸而持续改进了各种电子部件(例如,晶体管、二极管、电阻器、电容器等)的集成密度,其允许更多的部件集成到给定区域中。在一些应用中,这些更小的电子部件也需要更小的封装件,该封装件与过去的封装件相比利用更少的面积。
三维集成电路(3DIC)是半导体封装的最新发展,在该封装中多个半导体管芯彼此上下堆叠,诸如封装件上封装件(PoP)和封装件中系统(SiP)封装技术。例如,由于堆叠的管芯之间的互连长度得以减小,3DIC提供了改进的集成密度和其他优势,诸如更快的速度和更高的带宽。
混合接合是一种用于3DIC的接合工序,其中使用混合接合技术将两个半导体晶圆接合到一起。在2012年6月5日提交的、序列号为13/488,745,标题为“ThreeDimensionalIntegratedCircuitStructuresandHybridBondingMethodsforSemiconductorWafers”的专利申请中描述了一些形成3DIC的方法,该申请以其全部内容作为参考结合到本文中。
发明内容
为了解决现有技术中存在的问题,根据本发明的一个方面,提供了一种用于半导体晶圆的混合接合系统,所述系统包括:室;设置在所述室内的多个副室;以及设置在所述室内的机械夹持器,适用于在所述多个副室之间移动所述室内的多个半导体晶圆,其中所述多个副室包括:适用于从所述多个半导体晶圆去除保护层的第一副室;适用于在将所述多个半导体晶圆混合接合在一起之前激活所述多个半导体晶圆的顶面的第二副室;以及适用于对准所述多个半导体晶圆和将所述多个半导体晶圆混合接合在一起的第三副室。
在上述混合接合系统中,还包括适用于支撑多个第一半导体晶圆的第一加载端口,适用于支撑多个第二半导体晶圆的第二加载端口,以及适用于支撑多个已经被所述系统混合接合到一起的第一半导体晶圆和第二半导体晶圆的第三加载端口,其中,所述第一加载端口、所述第二加载端口,以及所述第三加载端口设置在所述机械夹持器的附近。
在上述混合接合系统中,其中,所述系统包括单个平台。
在上述混合接合系统中,其中,所述多个副室还包括第四副室,适用于在将所述多个半导体晶圆混合接合在一起之前清洁所述多个半导体晶圆。
在上述混合接合系统中,其中,所述多个副室还包括第四副室,适用于在将所述多个半导体晶圆混合接合在一起之前清洁所述多个半导体晶圆,其中,对于所述系统,在所述第四副室中清洁所述多个半导体晶圆和在所述第三副室中混合接合所述多个半导体晶圆之间的处理时间段包括大约30分钟或小于30分钟。
在上述混合接合系统中,其中,所述第一副室或所述第二副室包括用于所述多个半导体晶圆中的一个半导体晶圆的加热的支撑件、与所述第一副室或所述第二副室连接的泵、清洗管线、和桶;其中,所述第一副室或所述第二副室还包括与所述桶连接的起泡器。
根据本发明的另一方面,还提供了一种用于半导体晶圆的混合接合方法,所述方法包括:在第一半导体晶圆和第二半导体晶圆的顶面上方形成保护层;将所述第一半导体晶圆和所述第二半导体晶圆置入室内;从所述第一半导体晶圆和所述第二半导体晶圆的所述顶面的上方去除所述保护层;激活所述第一半导体晶圆和所述第二半导体晶圆的所述顶面;连接所述第二半导体晶圆的顶面与所述第一半导体晶圆的顶面;以及混合接合所述第一半导体晶圆和所述第二半导体晶圆;其中,在不将所述第一半导体晶圆和所述第二半导体晶圆从所述室移出的情况下,去除所述保护层,激活所述顶面,连接所述第二半导体晶圆的顶面和所述第一半导体晶圆的顶面,以及混合接合所述第一半导体晶圆和所述第二半导体晶圆。
在上述方法中,其中,去除所述保护层包括选自于基本上由暴露于酸、暴露于HCOOH、暴露于HCI、热分解、热解吸、暴露于等离子体去除处理、暴露于紫外(UV)光、以及这些的组合所组成的组的方法。
在上述方法中,还包括在激活所述顶面之后,清洁所述第一半导体晶圆和所述第二半导体晶圆的所述顶面。
在上述方法中,还包括在激活所述顶面之后,清洁所述第一半导体晶圆和所述第二半导体晶圆的所述顶面,其中,在所述室内的不同副室中分别去除所述保护层、激活所述顶面、以及清洁所述顶面。
在上述方法中,其中,在所述室内的单个副室中连接所述第二半导体晶圆的所述顶面和所述第一半导体晶圆的所述顶面,并且混合接合所述第一半导体晶圆和所述第二半导体晶圆。
在上述方法中,其中,形成所述保护层包括形成选自于基本上由C、Si、H、以及这些的组合所构成的组的材料。
在上述方法中,其中,形成所述保护层包括形成厚度为大约100埃或小于100埃的材料,或者形成所述保护层包括形成单层材料。
在上述方法中,其中,去除所述保护层或激活所述顶面还包括清洁所述第一半导体晶圆和所述第二半导体晶圆的所述顶面。
根据本发明的又一方面,还提供了一种用于半导体晶圆的混合接合方法,所述方法包括:提供第一半导体晶圆和第二半导体晶圆,所述第一半导体晶圆和所述第二半导体晶圆分别具有设置在晶圆顶面上的绝缘材料内的多个导电焊盘;在所述第一半导体晶圆和所述第二半导体晶圆的顶面上方形成保护层;将所述第一半导体晶圆和所述第二半导体晶圆置入室内;从所述第一半导体晶圆和所述第二半导体晶圆的所述顶面的上方去除所述保护层;激活所述第一半导体晶圆和所述第二半导体晶圆的所述顶面;清洁所述第一半导体晶圆和所述第二半导体晶圆的所述顶面;将所述第二半导体晶圆和所述第一半导体晶圆的所述顶面连接在一起;以及混合接合所述第一半导体晶圆和所述第二半导体晶圆,其中,混合接合所述第一半导体晶圆和所述第二半导体晶圆包括在所述第一半导体晶圆的绝缘材料和所述第二半导体晶圆的绝缘材料之间形成第一接合,以及在所述第一半导体晶圆的所述多个导电焊盘和所述第二半导体晶圆的所述多个导电焊盘之间形成第二接合;其中,在不将所述第一半导体晶圆和所述第二半导体晶圆从所述室移出的情况下,去除所述保护层,激活所述顶面,清洁所述顶面,将所述顶面连接在一起,以及混合接合所述第一半导体晶圆和所述第二半导体晶圆。
在上述方法中,其中,所述第一半导体晶圆和所述第二半导体晶圆的所述顶面包括形成在顶面上的氧化物材料,其中,去除所述保护层或激活所述顶面包括去除所述氧化物材料的一部分。
在上述方法中,其中,所述第一半导体晶圆和所述第二半导体晶圆的所述顶面包括形成在顶面上的氧化物材料,其中,去除所述保护层或激活所述顶面包括去除所述氧化物材料的一部分,其中,所述多个导电焊盘包括Cu或Cu合金,其中,去除所述氧化物材料的一部分包括去除CuOx。
在上述方法中,其中,清洁所述顶面包括选自于基本上由暴露于去离子(DI)H2O、暴露于NH4OH、暴露于稀释的氢氟酸(DHF)、暴露于酸、用刷子清洁、超声波工序、旋转工艺、暴露于红外(IR)灯、以及这些的组合所组成的组的方法。
在上述方法中,其中,在小于大约30MPa的压力下,或大约100至500摄氏度的温度下混合接合所述第一半导体晶圆和所述第二半导体晶圆。
在上述方法中,其中,包括形成保护层和将所述第一半导体晶圆和所述第二半导体晶圆混合接合在一起之间的时间段的储存(Q)时间大于大约1天。
附图说明
为了更全面地理解实施例及其优势,现将结合附图所进行的描述作为参考,其中:
图1是根据本发明的实施例的半导体晶圆的一部分的截面图;
图2至图5是截面图,示出根据处于各个阶段的实施例的晶圆与晶圆混合接合方法;
图6示出根据实施例的用于将半导体晶圆混合接合到一起的单个平台系统;
图7示出根据实施例的图6所示的系统的额外的部分;以及
图8是根据实施例使用混合接合工艺形成3DIC结构的方法的流程图。
除非另有说明,不同附图中的相应标号和符号通常指相应部件。将附图绘制成清楚地示出实施例的相关方面而不必须成比例绘制。
具体实施方式
下面,详细讨论本发明各实施例的制造和使用。然而,应该理解,本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式,而不用于限制本发明的范围。
本公开的实施例涉及的是半导体器件的3DIC封装。在此将描述用于半导体晶圆的新颖的混合接合系统和方法。
首先参考图1,示出了根据本公开的实施例的半导体晶圆100的一部分的截面图。使用根据本文的实施例的新颖的混合接合系统和工艺将两个或多个半导体晶圆(诸如,所示的晶圆100)垂直地连接在一起。
半导体晶圆100包括工件102。工件102包括半导体衬底,其包括硅或其他半导体材料并且可以被例如绝缘层所覆盖。工件102可以包括例如,位于单晶硅上方的氧化硅。可以使用化合物半导体,诸如,GaAs、InP、Si/Ge,或SiC来代替硅。工件102可以包括例如,绝缘体上硅(SOI)或绝缘体上锗(GOI)衬底。
工件102可以包括接近工件102的顶面形成的器件区域104。器件区域104包括有源部件或电路,诸如,导电部件、注入区域、电阻器、电容器,以及其他半导体部件,例如,晶体管、二极管等。在一些实施例中,例如,在前段(FEOL)工艺中,器件区域104形成在工件102上方。如图所示,工件102也可以包括具有导电材料的衬底通孔(TSV)105,其提供从工件102的底面到顶面的连接。
在工件102上方,例如,在工件102的器件区域104上方形成金属化结构106。例如,在一些实施例中,在后段(BEOL)工艺中在工件102上方形成金属化结构106。金属化结构106包括导电部件,诸如,导线108、通孔110、以及形成在绝缘材料114中的导电焊盘112。导电焊盘112包括例如,形成在半导体晶圆100的顶面上的接触焊盘或接合焊盘。一些通孔110将导电焊盘112与金属化结构106中的导线108相连接,而其他通孔110将接触焊盘112与工件102的器件区域104相连接。通孔110也可以将不同金属化层中的导线108连接在一起,未示出。导电部件可以包括通常使用在BEOL工艺中的导电材料,诸如,Cu、Al、W、Ti、TiN、Ta、TaN,或多层或这些的组合。根据实施例,例如,最接近金属化结构106的顶面设置的导电焊盘112包括Cu或铜合金。所示出的金属化结构106仅仅用于说明目的:金属化结构106可以包括其他配置并且可以包括例如,一个或多个导线和通孔层。如其他实例那样,一些半导体晶圆100可以具有三个导线和通孔层,或四个或四个以上导线和通孔层。
半导体晶圆100包括例如呈网格的多个半导体器件,这些器件包括工件102的部分和横跨其表面形成的金属化层106。例如,半导体器件包括管芯,每个管芯均可以在工件102的俯视图中呈方形或矩形图案的形状。
图2至图5是截面图,示出根据处于各个阶段的实施例使两个图1所示的半导体晶圆100混合接合的方法。图2示出了图1所示的半导体晶圆100的一部分的更详细的视图,该半导体晶圆包括设置在金属化结构106的顶面上的两个导电焊盘112。一些通孔110与导电焊盘112和导线108相连接。在一些实施例中,绝缘材料114包括SiO2,而导电焊盘112包括Cu。可选地,绝缘材料114和导电焊盘112可以包括其他材料。
在一些实施例中,使用镶嵌工艺来形成导电焊盘112,其中,绝缘材料114沉积在工件102上方,并且使用光刻图案化绝缘材料114。用导电材料填充图案化的绝缘材料114,并且使用化学机械抛光(CMP)工艺,蚀刻工艺,或这些的组合从绝缘材料114的顶面上去除导电材料的过量部分。在其他实施例中,可以沉积导电材料并使用光刻对其进行图案化,并可以在导电材料上方形成绝缘材料114,从而使用金属蚀刻工艺形成导电焊盘112。然后使用CMP工艺、蚀刻工艺,或这些的组合去除导电焊盘112上方的过量绝缘材料114。
根据本发明的一些实施例,在形成导电焊盘112之后,在半导体晶圆100的制造工艺几近结束时实施CMP工艺。
如图3所示,在形成和清洁导电焊盘112之后,在半导体晶圆100的顶面上方形成保护层116。保护层116包括绝缘材料,并且可以包括C、Si、H,和/或其组合。在一些实施例中,保护层116包括C、Si和H。可选地,保护层116可以包括其他材料。保护层116包括适用于防止氧化物材料形成在第一和第二半导体晶圆的顶面上(例如,在导电焊盘112的顶面上)或缓和第一和第二半导体晶圆的顶面上(例如,在导电焊盘112的顶面上)的氧化物材料的材料。在一些实施例中,在清洁工艺之后,在导电焊盘112的顶面上可能形成小部分的氧化物材料108,而保护层116缓和氧化物材料108,从而使进一步的氧化最小化并防止导电焊盘112受损。
在一些实施例中,使用与半导体晶圆100的顶面具有大于大约60度的接触角的蒸汽型沉积工艺或疏水性工艺形成保护层116。可选地,可以使用其他方法形成保护层116。保护层116包括大约100埃或更小的厚度。可选地,保护层116可以包括其他尺寸。在一些实施例中,保护层116包括单层材料。
在一些实施例中,然后将半导体晶圆100储存一段时间。例如,完成制造工艺之后,可以将半导体晶圆100放置在储存的制造设备中或放置在架子上一段时间。由于防止或缓和导电焊盘112的顶面上形成氧化物材料的保护层116的存在,可以有利地延长半导体晶圆100的储存时间。例如,在导电焊盘包括Cu或Cu合金的实施例中,保护层116防止在导电焊盘112的顶面上形成Cu氧化物。
当要使用3DIC工艺将半导体晶圆100与另一个半导体晶圆100封装在一起时,晶圆100被置入室142内(图3中未示出;见图6,本文将进一步进行描述)中。如图3和图4所示,使用去除工艺119将保护层116从晶圆100的顶面上去除。去除工艺119可以包括:例如,将晶圆100暴露给酸,暴露给HCOOH,暴露给HCI,热分解,热解吸附,暴露给等离子体去除处理,暴露给紫外(UV)光,或其组合。可选地,去除工艺119可以包括其他类型的去除工艺。
在形成保护层116之前,根据制造环境(例如,由于Cu容易氧化)可以在最终制造步骤之后立即开始在导电焊盘112的顶面上形成氧化物材料118。氧化物材料118可以包括例如,通过将Cu导电焊盘112暴露于空气中的氧而形成的氧化铜(CuOx)。例如,根据导电焊盘112的材料的类型,氧化物材料118可以包括其他材料。为了避免晶圆100之间的高电阻连接,将氧化物材料118从导电焊盘112的顶面去除对实现与另一个半导体晶圆100的高质量混合接合是至关重要的。有利地,在一些实施例中,在用于从晶圆100的顶面上去除保护层116的去除工艺119期间去除部分或所有的氧化物材料118。在一些实施例中,去除工艺119也可以清洁晶圆100的顶面。在不将晶圆100从室142移出的情况下执行保护层116的去除工艺119,从而避免在导电焊盘112的顶面上形成任何额外的氧化物材料118。
然后,如图4所示,使用激活工艺120来激活晶圆100的顶面。例如,在一些实施例中,激活工艺120包括利用等离子体,在小于大约1000瓦特的功率密度下激活晶圆100的顶面。可选地,可以使用其他方法和功率水平。晶圆100的顶面的表面粗糙度基本上不会被激活工艺120改变,并且在一个实施例中可以包括小于大约5埃的均方根(RMS)。在一些实施例中,激活工艺120还可以清洁晶圆100的顶面。在一些实施例中,例如,如果任何氧化物材料118在保护层116的去除工艺119之后仍残留在接触焊盘112的顶面上的话,可以在激活工艺120期间去除部分或所有的残留的氧化物材料118。为了避免在导电焊盘112的顶面上形成任何额外的氧化物材料118,在去除工艺119之后,在不将晶圆100从室142移出的情况下执行激活工艺120。
在一些实施例中,在激活工艺120之后,可以清洁晶圆100。该清洁工艺可以包括例如,暴露于去离子(DI)H2O,暴露于NH4OH,暴露于稀释的氢氟酸(DHF)(例如,在小于大约1%的HF酸浓度下),暴露于其他酸,带有刷子的清洁工艺,超声波工序(mega-sonicprocedure),旋转工序,暴露于红外线(IR)灯,或这些的组合,然而可选地,该清洁工艺可以包括其他类型的清洁工艺。在一些实施例中,该清洁工艺提高了晶圆100的顶面上(例如,导电焊盘112的顶面上)的羟基密度。例如,导电焊盘112上的羟基密度的提高有利地增强了接合强度和降低了混合接合工艺所需的退火温度。在不将晶圆100从室142移出的情况下再次执行清洁工艺,从而避免任何额外的氧化物材料118形成在导电焊盘112的顶面上。
例如,采用去除工艺119、激活工艺120以及清洁工艺来处理晶圆100的用于与另一个晶圆100混合接合的顶面,从而使得晶圆100尽可能干净以便在两个或多个晶圆100之间形成高质量的混合接合。去除工艺119、激活工艺120,以及清洁工艺有助于两个或多个晶圆100的混合接合,有利地允许在后续的混合接合工艺中使用低压和低温。去除工艺119、激活工艺120和/或清洁工艺可以被用于去除部分或所有的氧化物材料118。为了减少包括CuOx的氧化物材料118,选择化学反应作为去除工艺119、激活工艺120和/或清洁工艺的部分的想法可以包括以下反应,例如:
CuO+HCOOH→Cu(COOH)2+H2O;
Cu(HCOOH)2→Cu+CO2+H2;或
CuO+H2→Cu+H2O.
在清洁工艺之后,然后在不将晶圆100从室142移出的情况下,将图4所示的晶圆100与另一个晶圆100混合接合。图5示出了两个半导体晶圆100a和100b,使用混合接合工艺通过将一个半导体晶圆100b的顶面与另一个半导体晶圆100a的顶面相连接而混合来将这两个半导体晶圆混合接合在一起。这些晶圆包括第一半导体晶圆100a和第二半导体晶圆100b,使用本文所述的用于图1至图4所示的晶圆100的步骤来处理上述半导体晶圆。第二半导体晶圆100b的顶面与第一半导体晶圆100a的顶面相连接。第二半导体晶圆100b是颠倒的,即,例如,由图4所示的视图旋转90度所得。
如图5所示,通过将第二半导体100b上的导电焊盘112b与第一半导体晶圆100a上的导电焊盘112a相对准来实现第二半导体晶圆100b与第一半导体晶圆100a的接合。可以使用例如,光学探测来实现晶圆100a和100b的对准。第二半导体晶圆100b的绝缘材料114b的顶面也可以与第一半导体晶圆100a的绝缘材料114a的顶面相对准。
在晶圆100a和100b的对准工艺之后,如图5所示,通过施加压力124和热126来将晶圆100a和100b混合接合在一起。例如,施加的压力124可以包括小于约30Mpa的压力,施加的热量126可以包括在大约100至500摄氏度的温度下的退火工艺,然而可选地可以将其他数量的压力124和热量126用于混合接合工艺。例如,在一些实施例中,在退火工艺之后导电焊盘112的Cu的晶粒尺寸可以包括大约0.1至5μm,接合强度为大于约1.0J/m2。可以在N2氛、Ar氛、He氛、(大约4至10%H2)/(大约90至96%惰性气体或N2)氛、惰性混合气体氛,这些的组合,或其他类型的氛围下执行该混合接合工艺。例如,在一些实施例中,室142中的周围环境包括少量的或不包括O2,从而防止导电焊盘112a和112b在混合接合工艺之前或期间受到氧化。
混合接合工艺得到了接合132,该接合形成在第一和第二半导体晶圆100a和100b各自的绝缘材料114a和114b之间。接合134也形成在第一和第二半导体晶圆100a和100b各自的导电焊盘112a和112b之间。接合132包括非金属与非金属接合,而接合134包括金属与金属接合。例如,混合接合工艺的部分可以包括形成非金属与非金属接合132的熔融工艺,混合接合工艺的部分可以包括形成金属与金属接合134的铜与铜接合工艺。术语“混合”是指使用单次接合工艺形成两种不同类型的接合132和134,而不是像例如,其他类型的晶圆与晶圆接合工艺中所实践的那样仅形成一种类型的接合132或134。
所得到的、图5中所示的3DIC结构130包括堆叠的和接合的第一和第二半导体晶圆100a和100b。然后,沿着在俯视图中被布置成网格状的切割线128切割第一和第二半导体晶圆100a和100b,并且将晶圆100a和100b上的封装的3DIC半导体器件彼此分开(未示出)。
图6示出根据实施例的用于将半导体晶圆100、100a和100b混合接合到一起的单个平台系统140。系统140包括室142,在其中使用本文所述的工艺混合接合半导体晶圆100、100a和100b。机械夹持器144被设置在该室内用于将半导体晶圆100、100a和100b移动到理想位置,从而在室140的内部和外部进行加工。在室140内设置多个副室146、148、150和152。在机械夹持器144附近设置有多个处在室140外部的端口154、156和158。端口154、156和158为半导体晶圆100、100a和100b进出室140提供入口和出口。
端口154包括适用于支撑多个第一半导体晶圆100a的第一加载端口,而端口156包括用于支撑多个第二半导体晶圆100b的第二加载端口,该第二半导体晶圆将与第一半导体晶圆100a混合接合。端口154和156包括在混合接合工艺开始时放置和堆叠一个或多个上面具有保护层116的晶圆100a和100b的位置。机械夹持器144将一个半导体晶圆100a从端口154移动到室142中,并且通过室142进入到副室146中。副室146包括适用于将保护层116从半导体晶圆100a上去除的副室;例如,副室146包括端口和与其相连的线,其中,为了进行处理,可以使适合的化学药品和气体进入到副室146中。在实施例中,副室146包括烘烤室。使用本文所述的去除工艺119来将保护层116从晶圆100a去除,然后机械夹持器144将晶圆100a移动到下一个副室148中,该副室适用于激活晶圆100a的顶面。在一个实施例中,副室148包括等离子体室。在副室148中激活晶圆100a的顶面,并且机械夹持器144将晶圆100a移动到下一个副室150中,该副室适用于清洁晶圆100a。在一个实施例中,副室150包括清洁晶圆的清洁模块。在副室150中清洁晶圆100a,并且机械夹持器144将晶圆100a移动到下一个副室152中,该副室用于使第一半导体晶圆100a与第二半导体晶圆100b对准和混合接合。在一些实施例中,副室152包括晶圆与晶圆对准和接合模块。
然后,与第一半导体晶圆100a的处理同时地或相继地,在将第二半导体晶圆100b之一从端口156移入到室142中之后,通过机械夹持器144和各个副室146、148和150如上述处理第一半导体晶圆100a那样处理第二半导体晶圆100b。在副室150中对第二半导体晶圆100b进行清洁之后,晶圆100b也被移入到副室152中,并且将第一和第二晶圆100a和100b对准和混合接合在一起。在混合接合工艺之后,混合接合的晶圆130(见图5)被机械夹持器144移至端口158,该端口包括用于支撑多个已使用系统140接合在一起的第一和第二半导体晶圆100a和100b的负载接口。例如,在一个实施例中,负载接口158可以包括堆叠组(stackinglot)。
根据一些实施例,在独立的副室146中去除保护层116,在独立的副室148中激活晶圆100、100a和100b的顶面,并且在独立的副室150中清洁晶圆100、100a和100b的顶面。根据其他实施例,第二半导体晶圆100b的顶面与第一半导体晶圆100a连接和对准,并且在室140内的单个副室152内执行晶圆100a和100b的混合接合工艺。例如,在一些实施例中,使用光学系统执行晶圆100a和100b的对准,该光学系统包括可在大约300nm至大约750nm操作的可视光范围系统,可在大约800nm至1000nm工作的红外(IR)光范围系统,反射(IR)系统,或其组合。可选地也可以使用其他类型的光学对准系统对准晶圆100a和100b。光学对准系统可以设置在例如,副室152中或副室152附近。
混合接合系统140有利地包括单个平台,其中,多个晶圆100a和100b在未暴露于氧或最小限度地暴露于氧的情况下,在一个室142中进行混合接合,从而避免了随着晶圆100a和100b在各个副室146、148、150和152之间的运动在导电焊盘112上形成氧化物材料118,从而得到具有高质量混合接合的混合接合的晶圆130,例如之前本文关于图5所述的晶圆100a和100b的绝缘材料114a和11b之间的接合132,以及其导电焊盘112a和112b之间的接合134。在一些实施例中,系统140在副室150中清洁多个半导体晶圆与在副室152中混合接合多个半导体晶圆之间的处理时间段约为,例如,30分钟或更少,从而进一步降低了形成氧化物材料118的风险。
图7示出根据一个实施例的图6所示系统140的额外部分。示出了具有多个部件的实例,这些部件能够与副室146、148、150或152连接,从而使用副室146、148、150或152在晶圆100、100a和100b上执行所需的处理。示出了可以与用于去除保护层116的副室146相连接或与用于激活晶圆100的顶面的副室148相连接的部件的实例。副室146或148包括加热的支撑件170,该支撑件用于支撑和加热半导体晶圆100。清洗管线172与副室146或148相连接,而包括适用于存储处理晶圆100所需的酸162或其他化学药剂的容器或器皿的桶160通过管线168与副室146或148相连接。酸162通过管线164进入到桶160中。泵176通过管线174与副室146或148相连接。泵176被用于使用管线178在晶圆100的处理过程中去除残留物。管线172、164、168、174和178可以包括例如,管道或软管。在一些实施例中,根据所使用的化学药品和工艺,桶160可以具有与其相连接的起泡器166。
图8示出了根据一个实施例使用混合接合工艺形成3DIC结构130的方法的流程图180。在步骤182中,在第一半导体晶圆100a和第二半导体晶圆100b的顶面上方形成了保护层116。然后,在混合接合工艺之前将晶圆100a和100b储存一段时间。在步骤184中,将第一和第二半导体晶圆100a和100b放置到室142中。在步骤186中,在室142中的副室146中将保护层116从第一和第二半导体晶圆100a和100b的顶面上去除。在步骤188中,在室142中的副室148中,在不将第一和第二半导体晶圆100a和100b从室142移出的情况下激活第一和第二半导体晶圆100a和100b的顶面。也可以在室142中的副室150中清洁第一和第二半导体晶圆100a和100b(未示出)。在一些实施例中,可以不需要清洁步骤和清洁副室150;例如,可以使用用于保护层116的去除工艺119和激活工艺120来充分地清洁晶圆100a和100b。在步骤190中,在副室152中,在不将第一和第二半导体晶圆100a和100b从室142移出的情况下将第二半导体晶圆100b的顶面与第一半导体晶圆100a的顶面相连接。在步骤192中,在副室152中,在不将第一和第二半导体晶圆100a和100b从室142移出的情况下将第一和第二半导体100a和100b混合接合在一起。
使用本文所描述的方法可以将三个或三个以上半导体晶圆100、100a和100b垂直地堆叠和混合接合在一起。工件102的TSV105的暴露的端部(见图1)可以与例如,另一个半导体晶圆100、100a和100b上的导电焊盘112相连接。可选地,作为另一个实施例,可以在TSV105的暴露的端部上方形成额外的包括导电焊盘112的连接层,其可以被用于混合接合另一个晶圆100、100a和100b。
使用本文所述的混合接合工艺将第二半导体晶圆100b上的一个或多个半导体器件与第一半导体晶圆100a上的每个半导体器件混合接合。半导体晶圆100、100a和100b上的半导体器件可以包括以下器件类型,诸如,半导体管芯、电路、光电二极管、微机电系统(MEMS)器件、生物传感器件、互补金属氧化物(CMOS)器件、数字图像传感器、专用集成电路(ASIC)器件,或这些组合。如一个实例,一个半导体晶圆100a可以包括多个管芯,每个管芯均包括处理器,而其他的半导体晶圆100b则可以包括与处在其他半导体晶圆100a上的每个处理器相连接或封装在一起的一个或多个存储器件。在其他实施例中,一个半导体晶圆100b可以包括数字图像传感器,其包括多个形成在其上的光电二极管,作为另一个实例,其他的半导体晶圆100a可以包括其上具有支撑电路用于数字图像传感器的管芯。支撑电路可以包括例如,ASIC器件。在其他实施例中,可以使用一个晶圆100b来增强另一个晶圆100a中的光敏性。根据本文的实施例,取决于应用,使用本文所描述的新颖的混合接合方法将半导体晶圆100、100a和100b的其他类型组合以及半导体器件一起封装在3DIC结构中。
本发明的实施例包括混合接合半导体晶圆从而形成3DIC结构130的方法,还包括用于执行本文所描述的混合接合方法的系统140。在一些实施例中,第一半导体晶圆和第二半导体晶圆的多个导电焊盘包括Cu,而第一半导体晶圆和第二半导体晶圆的绝缘材料包括SiO2,其中,本文所描述的混合接合方法包括Cu/SiO2晶圆级混合接合工艺。
本发明的实施例的优势包括提供了新颖的混合接合方法和系统140,其为3DIC提供高质量混合接合。该新颖的方法和系统140能够去除保护层116并在单个平台中的混合接合工序中减少氧化物材料118在导电焊盘112上的形成。将混合接合工艺集成到单个平台中降低了经营成本(CoO)。保护层116使导电焊盘112表面绝缘并且还防止或缓和氧化物材料118的形成。保护层116能够延长储存时间(Q),该储存时间包括形成保护层116和将晶圆100混合接合在一起之间的时间段。通过本发明的实施例可有利地实现例如,大于大约1天(例如,几周或几个月或更长时间)的Q;因此在混合接合工序中消除了Q时间缩短的忧虑。新颖的混合接合方法和系统140通过减少或消除导电焊盘112a和112b之间的氧化物层118来降低导电焊盘112a和112b的接合的接触电阻。
在混合接合工艺中实现了高精度地对准晶圆100a和100b。由于氧化物材料118的量的减少以及晶圆100a和100b的被高度激活和清洁的顶面,可以使用更小的力、压力124和热量126来混合接合晶圆100a和100b,从而防止对晶圆100a和100b上的半导体器件施加机械和热应力并防止其变形。本文所描述的混合接合方法有利地与互补金属氧化物半导体(CMOS)工艺和材料兼容。可以轻易地在半导体制造和封装工艺流程和加工设备中实施该新颖的混合接合方法和系统140。
根据本发明的一个实施例,一种半导体晶圆的混合接合系统包括室和多个设置在该室内的副室。机械夹持器设置在室内,适用于在该室内,在多个副室之间移动多个半导体晶圆。多个副室包括:适用于从多个半导体晶圆去除保护层的第一副室,以及适用于将多个半导体晶圆混合接合在一起之前激活多个半导体晶圆的顶面的第二副室。多个副室还包括适用于对准多个半导体晶圆和将多个半导体晶圆混合接合在一起的第三副室。
根据另一个实施例,一种用于半导体晶圆的混合接合方法包括:在第一半导体晶圆和第二半导体晶圆的顶面上方形成保护层,以及将第一半导体晶圆和第二半导体晶圆置入室内。从第一半导体晶圆和第二半导体晶圆的顶面上方去除保护层,以及激活第一半导体晶圆和第二半导体晶圆的顶面。该方法包括将第二半导体晶圆的顶面与第一半导体晶圆的顶面相接合,以及混合接合第一半导体晶圆与第二半导体晶圆。在不将第一半导体晶圆和第二半导体晶圆从室移出的情况下,去除保护层,激活顶面,连接第二半导体晶圆的顶面和第一半导体晶圆的顶面,以及混合接合第一半导体晶圆和第二半导体晶圆。
根据又一个实施例,一种用于半导体晶圆的混合接合方法包括:提供第一半导体晶圆和第二半导体晶圆,第一半导体晶圆和第二半导体晶圆各自具有多个设置在其顶面上的绝缘材料内的导电焊盘。在第一半导体晶圆和第二半导体晶圆的顶面上方形成保护层,并且将第一半导体晶圆和第二半导体晶圆置入室内。从第一半导体晶圆和第二半导体晶圆的顶面上方去除保护层,以及激活第一半导体晶圆和第二半导体晶圆的顶面。清洁第一半导体晶圆和第二半导体晶圆的顶面,以及将第二半导体晶圆和第一半导体晶圆的顶面连接在一起。将第一半导体晶圆与第二半导体晶圆混合接合。混合接合第一半导体晶圆和第二半导体晶圆包括在第一半导体晶圆的绝缘材料和第二半导体晶圆的绝缘材料之间形成第一接合,以及在第一半导体晶圆的多个导电焊盘和第二半导体晶圆的多个导电焊盘之间形成第二接合。在不将第一半导体晶圆和第二半导体晶圆从室移出的情况下,去除保护层,激活顶面,清洁顶面,将顶面连接在一起,以及混合接合第一半导体晶圆和第二半导体晶圆。
尽管已经详细地描述了本发明及其优势,但应该理解,可以在不背离所附权利要求限定的本发明主旨和范围的情况下,做各种不同的改变,替换和更改。例如,本领域的技术人员将容易理解,处在本公开的范围内可以对在此所描述的多种部件、功能、工艺、以及材料进行改变。而且,本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解,通过本发明,现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造,材料组分、装置、方法或步骤根据本发明可以被使用。因此,所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。
Claims (20)
1.一种用于半导体晶圆的混合接合系统,所述系统包括:
室;
设置在所述室内的多个副室;以及
设置在所述室内的机械夹持器,适用于在所述多个副室之间移动所述室内的多个半导体晶圆,其中所述多个副室包括:适用于从所述多个半导体晶圆去除保护层并且去除部分或所有的氧化物材料的第一副室;适用于在从所述多个半导体晶圆去除所述保护层之后,在将所述多个半导体晶圆混合接合在一起之前,激活所述多个半导体晶圆的顶面并且去除部分或所有的氧化物材料的第二副室;以及适用于在激活工艺之后对准所述多个半导体晶圆和将所述多个半导体晶圆混合接合在一起的第三副室;
其中,半导体晶圆的顶面上的绝缘材料内设置有导电焊盘,并且所述氧化物材料形成在所述导电焊盘的顶面上。
2.根据权利要求1所述的混合接合系统,还包括适用于支撑多个第一半导体晶圆的第一加载端口,适用于支撑多个第二半导体晶圆的第二加载端口,以及适用于支撑多个已经被所述系统混合接合到一起的第一半导体晶圆和第二半导体晶圆的第三加载端口,其中,所述第一加载端口、所述第二加载端口,以及所述第三加载端口设置在所述机械夹持器的附近。
3.根据权利要求1所述的混合接合系统,其中,所述系统包括单个平台。
4.根据权利要求1所述的混合接合系统,其中,所述多个副室还包括第四副室,适用于在将所述多个半导体晶圆混合接合在一起之前清洁所述多个半导体晶圆。
5.根据权利要求4所述的混合接合系统,其中,对于所述系统,在所述第四副室中清洁所述多个半导体晶圆和在所述第三副室中混合接合所述多个半导体晶圆之间的处理时间段包括30分钟或小于30分钟。
6.根据权利要求1所述的混合接合系统,其中,所述第一副室或所述第二副室包括用于所述多个半导体晶圆中的一个半导体晶圆的加热的支撑件、与所述第一副室或所述第二副室连接的泵、清洗管线、和桶;其中,所述第一副室或所述第二副室还包括与所述桶连接的起泡器。
7.一种用于半导体晶圆的混合接合方法,所述方法包括:
在第一半导体晶圆和第二半导体晶圆的顶面上方形成保护层;
将所述第一半导体晶圆和所述第二半导体晶圆置入室内;
从所述第一半导体晶圆和所述第二半导体晶圆的所述顶面的上方去除所述保护层;
激活所述第一半导体晶圆和所述第二半导体晶圆的所述顶面;
连接所述第二半导体晶圆的顶面与所述第一半导体晶圆的顶面;以及
混合接合所述第一半导体晶圆和所述第二半导体晶圆;
其中,在不将所述第一半导体晶圆和所述第二半导体晶圆从所述室移出的情况下,去除所述保护层,激活所述顶面,连接所述第二半导体晶圆的顶面和所述第一半导体晶圆的顶面,以及混合接合所述第一半导体晶圆和所述第二半导体晶圆。
8.根据权利要求7所述的方法,其中,去除所述保护层包括选自于基本上由暴露于酸、暴露于HCOOH、暴露于HCI、热分解、热解吸、暴露于等离子体去除处理、暴露于紫外(UV)光、以及这些的组合所组成的组的方法。
9.根据权利要求7所述的方法,还包括在激活所述顶面之后,清洁所述第一半导体晶圆和所述第二半导体晶圆的所述顶面。
10.根据权利要求9所述的方法,其中,在所述室内的不同副室中分别去除所述保护层、激活所述顶面、以及清洁所述顶面。
11.根据权利要求7所述的方法,其中,在所述室内的单个副室中连接所述第二半导体晶圆的所述顶面和所述第一半导体晶圆的所述顶面,并且混合接合所述第一半导体晶圆和所述第二半导体晶圆。
12.根据权利要求7所述的方法,其中,形成所述保护层包括形成选自于基本上由C、Si、H、以及这些的组合所构成的组的材料。
13.根据权利要求7所述的方法,其中,形成所述保护层包括形成厚度为100埃或小于100埃的材料,或者形成所述保护层包括形成单层材料。
14.根据权利要求7所述的方法,其中,去除所述保护层或激活所述顶面还包括清洁所述第一半导体晶圆和所述第二半导体晶圆的所述顶面。
15.一种用于半导体晶圆的混合接合方法,所述方法包括:
提供第一半导体晶圆和第二半导体晶圆,所述第一半导体晶圆和所述第二半导体晶圆分别具有设置在晶圆顶面上的绝缘材料内的多个导电焊盘;
在所述第一半导体晶圆和所述第二半导体晶圆的顶面上方形成保护层;
将所述第一半导体晶圆和所述第二半导体晶圆置入室内;
从所述第一半导体晶圆和所述第二半导体晶圆的所述顶面的上方去除所述保护层;
激活所述第一半导体晶圆和所述第二半导体晶圆的所述顶面;
清洁所述第一半导体晶圆和所述第二半导体晶圆的所述顶面;
将所述第二半导体晶圆和所述第一半导体晶圆的所述顶面连接在一起;以及
混合接合所述第一半导体晶圆和所述第二半导体晶圆,其中,混合接合所述第一半导体晶圆和所述第二半导体晶圆包括在所述第一半导体晶圆的绝缘材料和所述第二半导体晶圆的绝缘材料之间形成第一接合,以及在所述第一半导体晶圆的所述多个导电焊盘和所述第二半导体晶圆的所述多个导电焊盘之间形成第二接合;其中,在不将所述第一半导体晶圆和所述第二半导体晶圆从所述室移出的情况下,去除所述保护层,激活所述顶面,清洁所述顶面,将所述顶面连接在一起,以及混合接合所述第一半导体晶圆和所述第二半导体晶圆。
16.根据权利要求15所述的方法,其中,所述第一半导体晶圆和所述第二半导体晶圆的所述顶面包括形成在顶面上的氧化物材料,其中,去除所述保护层或激活所述顶面包括去除所述氧化物材料的一部分。
17.根据权利要求16所述的方法,其中,所述多个导电焊盘包括Cu或Cu合金,其中,去除所述氧化物材料的一部分包括去除CuOx。
18.根据权利要求15所述的方法,其中,清洁所述顶面包括选自于基本上由暴露于去离子(DI)H2O、暴露于NH4OH、暴露于稀释的氢氟酸(DHF)、暴露于酸、用刷子清洁、超声波工序、旋转工艺、暴露于红外(IR)灯、以及这些的组合所组成的组的方法。
19.根据权利要求15所述的方法,其中,在小于30MPa的压力下,或100至500摄氏度的温度下混合接合所述第一半导体晶圆和所述第二半导体晶圆。
20.根据权利要求15所述的方法,其中,包括形成保护层和将所述第一半导体晶圆和所述第二半导体晶圆混合接合在一起之间的时间段的储存(Q)时间大于1天。
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