CN103500724A - 一种肖特基晶粒的预焊方法 - Google Patents

一种肖特基晶粒的预焊方法 Download PDF

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CN103500724A
CN103500724A CN201310393112.3A CN201310393112A CN103500724A CN 103500724 A CN103500724 A CN 103500724A CN 201310393112 A CN201310393112 A CN 201310393112A CN 103500724 A CN103500724 A CN 103500724A
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方丁玉
唐红梅
王栋梁
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Yangzhou Hy Technology Development Co Ltd
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Yangzhou Hy Technology Development Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/741Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L2224/742Apparatus for manufacturing bump connectors

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

本发明涉及肖特基晶粒的预焊方法,该方法包括以下步骤:步骤一,将丝网覆盖在肖特基晶圆的正表面;步骤一,将锡膏通过丝网印刷在肖特基晶圆的正表面上,丝网与肖特基晶圆分开;步骤三,将正表面印刷有锡膏的肖特基晶圆送入焊接炉中进行焊接,使锡膏均匀的覆盖在肖特基晶圆正表面;步骤四,焊接完成后,将肖特基晶圆从焊接炉中取出,进行切割,以得到正面覆盖有锡膏的肖特基晶粒。通过本发明所制得的晶粒可透过治具自动排列方向,提高生产效率,且在排列作业中因晶粒正面已被锡膏覆盖,可避免摩擦及晶粒相互碰撞造成正面划伤,提高生产良率及材料可靠性。

Description

一种肖特基晶粒的预焊方法
技术领域
本发明涉及半导体工艺领域,尤其涉及到一种肖特基晶粒的预焊方法。
背景技术
采用传统方法制作的肖特基晶粒因外型尺寸因素,无法使用治具自动排列方向,生产效率低,且在排列作业中晶粒正面会因摩擦治具及晶粒间相互碰撞造成划伤,影响生产良率及材料可靠性。
发明内容
本发明所要解决的技术问题是提供一种肖特基晶粒的预焊方法,使得晶圆切割后得到的一颗颗独立的晶粒可通过治具自动排列方向,以提高生产效率。
本发明解决上述技术问题的技术方案如下:一种肖特基晶粒的制作方法,包括以下步骤:
步骤一,将丝网覆盖在肖特基晶圆的正表面;
步骤一,将锡膏通过丝网印刷在肖特基晶圆的正表面上,丝网与肖特基晶圆分开;
步骤三,将正表面印刷有锡膏的肖特基晶圆送入焊接炉中进行焊接,使锡膏均匀的覆盖在肖特基晶圆正表面;
步骤四,焊接完成后,将肖特基晶圆从焊接炉中取出,进行切割,以得到正面覆盖有锡膏的肖特基晶粒。
进一步,所述肖特基晶粒正面形成有呈凸台状的锡膏。
进一步,所述凸台状的锡膏是球冠状的锡膏。
本发明的有益效果是:将锡膏通过丝网印刷在肖特基晶圆正面,进炉焊接后锡膏均匀覆盖在晶圆正面,待晶圆切割后,一颗颗独立晶粒可透过治具自动排列方向,提高生产效率,且在排列作业中因晶粒正面已被锡膏覆盖,可避免摩擦及晶粒相互碰撞造成正面划伤,提高生产良率及材料可靠性。
附图说明
图1为本发明肖特基晶粒的预焊方法的流程图;
图2为采用本发明肖特基晶粒的预焊方法中焊接完成后的肖特基晶圆俯视图;
图3为肖特基晶圆切割后形成的晶粒俯视图;
图4为肖特基晶圆切割后形成的晶粒侧视图。
附图中,各标号所代表的部件列表如下:
1、肖特基晶圆正表面,2、锡膏,3、晶粒。
具体实施方式
以下结合附图对本发明的原理和特征进行描述,所举实例只用于解释本发明,并非用于限定本发明的范围。
图1为本发明肖特基晶粒的预焊方法的流程图,如图1所示,肖特基晶粒的制作方法包括以下步骤:
步骤101,将丝网覆盖在肖特基晶圆的正表面。
步骤102,将锡膏通过丝网印刷在肖特基晶圆的正表面上,然后将丝网与肖特基晶圆分开。
步骤103,将正表面印刷有锡膏的肖特基晶圆送入焊接炉中进行焊接,使锡膏均匀的覆盖在肖特基晶圆正表面。
步骤104,焊接完成后,将肖特基晶圆从焊接炉中取出,进行切割,以得到正面覆盖有锡膏的肖特基晶粒。
图2为采用本发明肖特基晶粒的预焊方法中焊接完成后肖特基晶圆俯视图,如图2所示,肖特基晶圆通过丝网在其正表面印刷锡膏且通过焊接炉焊接后,锡膏2均匀的覆盖在肖特基晶圆正表面1上。锡膏2所在的位置与丝网中的网孔位置相对应,且丝网中网孔的直径大小根据晶粒大小的需要而设定。
图3为肖特基晶圆切割后形成的晶粒俯视图,且图4为肖特基晶圆切割后形成的晶粒侧视图,结合图3和图4所示,焊接完成后,将肖特基晶圆从焊接炉中取出,对肖特基晶圆进行切割,得到一颗颗独立的晶粒锡膏2在晶粒正面形成一个类似球冠状的凸台,而晶粒的背面没有凸台,晶粒筛盘利用晶粒这两个不同的面而将晶粒自动排列方向。晶粒通过治具自动排列方向,可以提高生产效率,且在排列作业中因晶粒正面已被锡膏覆盖,可避免摩擦及晶粒相互碰撞造成正面划伤,提高生产良率及材料可靠性。
以上所述仅为本发明的较佳实施例,并不用以限制本发明,凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。

Claims (3)

1.一种肖特基晶粒的预焊方法,其特征在于包括以下步骤:
步骤一,将丝网覆盖在肖特基晶圆的正表面;
步骤一,将锡膏通过丝网印刷在肖特基晶圆的正表面上,丝网与肖特基晶圆分开;
步骤三,将正表面印刷有锡膏的肖特基晶圆送入焊接炉中进行焊接,使锡膏均匀的覆盖在肖特基晶圆正表面;
步骤四,焊接完成后,将肖特基晶圆从焊接炉中取出,进行切割,以得到正面覆盖有锡膏的肖特基晶粒。
2.根据权利要求1所述的一种肖特基晶粒的预焊方法,其特征在于:所述肖特基晶粒正面形成有呈凸台状的锡膏。
3.根据权利要求2所述的一种肖特基晶粒的预焊方法,其特征在于:所述凸台状的锡膏为球冠状的锡膏。
CN201310393112.3A 2013-09-02 2013-09-02 一种肖特基晶粒的预焊方法 Pending CN103500724A (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106328548A (zh) * 2015-06-15 2017-01-11 苏州普福斯信息科技有限公司 晶圆印刷锡膏在二极管封装中的应用方法
CN113451158A (zh) * 2021-04-25 2021-09-28 福建天电光电有限公司 覆晶封装结构及其制作工艺

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0621109A (ja) * 1992-06-30 1994-01-28 Fuji Electric Co Ltd 半導体チップへの半田層の形成方法
CN1763937A (zh) * 2004-10-19 2006-04-26 宏齐科技股份有限公司 晶圆级光电半导体组装构造及其制造方法
US20080150128A1 (en) * 2006-12-25 2008-06-26 Siliconware Precision Industries Co., Ltd. Heat dissipating chip structure and fabrication method thereof and package having the same
KR100867521B1 (ko) * 2007-06-07 2008-11-07 삼성전기주식회사 마킹층을 구비한 웨이퍼 레벨 패키지의 패키징 방법
CN101689514A (zh) * 2007-01-19 2010-03-31 Lg伊诺特有限公司 用于封装半导体的方法
CN102064117A (zh) * 2010-11-19 2011-05-18 上海凯虹电子有限公司 小尺寸芯片的封装方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0621109A (ja) * 1992-06-30 1994-01-28 Fuji Electric Co Ltd 半導体チップへの半田層の形成方法
CN1763937A (zh) * 2004-10-19 2006-04-26 宏齐科技股份有限公司 晶圆级光电半导体组装构造及其制造方法
US20080150128A1 (en) * 2006-12-25 2008-06-26 Siliconware Precision Industries Co., Ltd. Heat dissipating chip structure and fabrication method thereof and package having the same
CN101689514A (zh) * 2007-01-19 2010-03-31 Lg伊诺特有限公司 用于封装半导体的方法
KR100867521B1 (ko) * 2007-06-07 2008-11-07 삼성전기주식회사 마킹층을 구비한 웨이퍼 레벨 패키지의 패키징 방법
CN102064117A (zh) * 2010-11-19 2011-05-18 上海凯虹电子有限公司 小尺寸芯片的封装方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106328548A (zh) * 2015-06-15 2017-01-11 苏州普福斯信息科技有限公司 晶圆印刷锡膏在二极管封装中的应用方法
CN113451158A (zh) * 2021-04-25 2021-09-28 福建天电光电有限公司 覆晶封装结构及其制作工艺

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Application publication date: 20140108