CN103489840A - 穿硅通孔及其制作方法 - Google Patents

穿硅通孔及其制作方法 Download PDF

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CN103489840A
CN103489840A CN201210323190.1A CN201210323190A CN103489840A CN 103489840 A CN103489840 A CN 103489840A CN 201210323190 A CN201210323190 A CN 201210323190A CN 103489840 A CN103489840 A CN 103489840A
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layer
metal
silicon via
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tungsten
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CN103489840B (zh
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黄琦雯
苏国辉
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Nanya Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

本发明公开了一种穿硅通孔结构，包含有一半导体基材；一第一金属层间介电层，设于该半导体基材上；一上盖层，覆盖该第一金属层间介电层；一导电层，贯穿该上盖层及该第一金属层间介电层，延伸至该半导体基材内；一钨金属膜，盖住该导电层的一上表面；一第二金属层间介电层，覆盖该上盖层以及该钨金属膜；以及一内连件，设于该第二金属层间介电层中。

Description

穿硅通孔及其制作方法
技术领域
本发明涉及半导体技术领域，特别是涉及一种用来连结堆栈芯片的穿硅通孔(through silicon via,TSV)技术，及其制作方法。
背景技术
为满足微小化封装及高稳定度、可靠度的需求，目前集成电路的封装已朝向立体封装技术发展。已知，立体堆栈式封装是由至少两个芯片或封装体彼此上下堆栈结合而成，利用此技术，例如在内存装置领域，可明显提升内存组件的整体效能。
立体堆栈式封装除了可以提升组件的整体效能，还可以提升组件的安装面积使用效率。举例来说，目前已有在立体堆栈式封装中采用穿硅通孔技术者，形成在芯片中的穿硅通孔将堆栈在一起的芯片彼此电性连结。顾名思义，穿硅通孔就是在芯片中形成贯穿通孔，然后填满导电材料，并可以连结他层接垫或线路，亦可直接与其它堆栈芯片电连接。
通常，形成穿硅通孔包括有以下步骤：首先，在晶圆阶段于各芯片的预定区域定义垂直孔洞，然后，于垂直孔洞内形成绝缘层，再于绝缘层上形成一晶种层，再以电镀方式将金属填满垂直孔洞。接着，进行晶背研磨或薄化，显露出穿硅通孔另一端。接着可以进行晶圆切割，形成单独的芯片，而芯片间即可直接够过穿硅通孔堆栈在一起构成立体封装。最后，将堆栈在一起的芯片模封，并在封装体的下表面植上锡球。
发明内容
本发明实施例提供一种穿硅通孔结构，包含有一半导体基材；一第一金属层间介电层，设于该半导体基材上；一上盖层，覆盖该第一金属层间介电层；一导电层，贯穿该上盖层及该第一金属层间介电层，延伸至该半导体基材内；一钨金属膜，盖住该导电层的一上表面；一第二金属层间介电层，覆盖该上盖层以及该钨金属膜；以及一内连件，设于该第二金属层间介电层中。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举较佳实施方式，并配合所附图式，作详细说明如下。然而如下的较佳实施方式与图式仅供参考与说明用，并非用来对本发明加以限制。
附图说明
图1至图4为依据本发明实施例所绘示的制作穿硅通孔的方法的剖面示意图。
其中，附图标记说明如下：
10半导体基材
10a前表面
10b后表面
12金属层间介电层
14钨插塞
16上盖层
18TSV沟槽
20导电层
22钨金属膜
30金属层间介电层
30a内连结构
30b内连结构
32铜金属内连件
34铜金属内连件
具体实施方式
在下文中，将参照附图说明本发明实施细节，该些附图中的内容构成说明书一部份，并以可实行该实施例的特例描述方式绘示。下文实施例已揭露足够的细节使该领域的一般技艺人士得以具以实施。当然，本发明中亦可实行其它的实施例，或是在不悖离文中所述实施例的前提下作出任何结构性、逻辑性、及电性上的改变。因此，下文的细节描述将不欲被视为是一种限定，其中所包含的实施例将由随附的申请专利范围来加以界定。
图1至图4为依据本发明实施例所绘示的制作穿硅通孔的方法的剖面示意图。如第1图所示，提供一半导体基材10，具有一前表面10a及一后表面10b。当然，半导体基材10也可以是任一底层，而不限于半导体材料。接着在半导体基材10的前表面10a上形成一金属层间介电(inter-metal dielectric,IMD)层12，且在IMD层12中可以形成有钨插塞14或钨区域连结(tungstenlocal interconnect)。接着可以在IMD层12上形成一上盖层16，例如，氮化硅层或氧化硅。接着，于上盖层16、IMD层12及半导体层10中蚀刻出一TSV沟槽1 8。在TSV沟槽1 8内可以形成一阻障层或晶种层(图未示)。接着以电镀等方法于TSV沟槽18内填满导电层20，例如，铜金属。接着，进行一化学机械研磨工艺，去除TSV沟槽1 8以外多余的导电层20。此时，导电层20的上表面约略与作为研磨停止层的上盖层16的上表面切齐。
如图2所示，进行选择性钨化学气相沈积(selective tungsten chemical vapordeposition,WCVD)工艺，选择性的在显露出来的导电层20的上表面沈积一钨金属膜22。举例来说，半导体基材10可以先进行除气处理(degassing condition:250°C)，接着，将除气后的半导体基材10导入预处理舱室中，加热至250°C。然后，将50 sccm氮气及100 sccm氢气同时通入舱室中，并利用射频(RF)等离子体处理半导体基材10的表面约30秒。之后，将半导体基材10移至反应室中，进行选择性钨化学气相沈积工艺，例如，将半导体基材10加热至250°C，通入10sccm六氟化钨(WF6)及5sccm硅烷(SiH4)，以于铜金属表面选择性的形成钨金属膜22。
如图3所示，接着进行一化学气相沈积工艺，沈积一IMD层30，例如，硅氧层或氧化硅。IMD层30覆盖住上盖层16以及钨金属膜22。接着，进行微影工艺及蚀刻工艺，于IMD层30中形成内连结构30a及30b。根据本发明实施例，内连结构30a及30b可以是镶嵌式沟槽，其中，内连结构30a贯穿IMD层30全部厚度，并且显露出部分的钨金属膜22，内连结构30b贯穿IMD层30及上盖层16全部厚度，并且显露出部分的钨插塞14。部分的IMD层12也可能被显露出来。接下来，对半导体基材10进行一预清洗工艺，将氧化钨从显露出来的钨金属表面去除。例如，可以利用氩(Ar)原子轰击显露出来的钨金属表面，以去除氧化钨。
如第4图所示，在完成上述内连结构30a及30b后，进行铜镶嵌工艺(copperdamascene process)，将内连结构30a及30b填满铜金属内连件(copperinterconnect features)32及34，其可以包括，但不限于，一阻障层以及一铜金属层。本发明的优点在于在形成铜金属内连件32及34前的预清洗阶段，仅有钨金属表面被显露出来，因此可以避免氩原子轰击造成对穿硅通孔的破坏，因而可以提升铜金属内连件32及34的电性效能。另外，根据本发明实施例，第4图中显示出来的结构特征包括：(1)钨金属膜22系选择性的形成在导电层或铜金属层20的上表面；以及(2)铜金属内连件32系与钨金属膜22直接接触。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。凡在本发明的精神和原则内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围内。

Claims (6)

1.一种穿硅通孔结构，其特征在于，包括：
一半导体基材；
一第一金属层间介电层，设于该半导体基材上；
一上盖层，覆盖该第一金属层间介电层；
一导电层，贯穿该上盖层及该第一金属层间介电层，延伸至该半导体基材内；
一钨金属膜，盖住该导电层的一上表面；
一第二金属层间介电层，覆盖该上盖层以及该钨金属膜；以及
一内连件，设于该第二金属层间介电层中。
2.根据权利要求1所述的穿硅通孔结构，其特征在于，该上盖层包含有氮化硅。
3.根据权利要求1所述的穿硅通孔结构，其特征在于，该内连件包含有铜镶嵌结构。
4.根据权利要求1所述的穿硅通孔结构，其特征在于，该内连件系与该钨金属膜直接接触。
5.根据权利要求1所述的穿硅通孔结构，其特征在于，该第一金属层间介电层包含有氧化硅。
6.根据权利要求1所述的穿硅通孔结构，其特征在于，该第二金属层间介电层包含有氧化硅。
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