CN103489795A - Frame-based AAQFN package with frame pre-plastic-package optimization technique adopted and manufacturing technique thereof - Google Patents
Frame-based AAQFN package with frame pre-plastic-package optimization technique adopted and manufacturing technique thereof Download PDFInfo
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- CN103489795A CN103489795A CN201310387744.9A CN201310387744A CN103489795A CN 103489795 A CN103489795 A CN 103489795A CN 201310387744 A CN201310387744 A CN 201310387744A CN 103489795 A CN103489795 A CN 103489795A
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000005457 optimization Methods 0.000 title abstract 3
- 238000004806 packaging method and process Methods 0.000 claims abstract description 36
- 238000005530 etching Methods 0.000 claims abstract description 35
- 238000003466 welding Methods 0.000 claims abstract description 9
- 238000007639 printing Methods 0.000 claims abstract description 6
- 238000000926 separation method Methods 0.000 claims abstract description 5
- 239000003292 glue Substances 0.000 claims description 12
- 238000012856 packing Methods 0.000 claims description 5
- 230000011664 signaling Effects 0.000 claims description 3
- 239000000853 adhesive Substances 0.000 abstract 3
- 230000001070 adhesive effect Effects 0.000 abstract 3
- 238000001514 detection method Methods 0.000 abstract 1
- 238000003754 machining Methods 0.000 abstract 1
- 238000011417 postcuring Methods 0.000 abstract 1
- 238000003860 storage Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 7
- 238000005538 encapsulation Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000006855 networking Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000013585 weight reducing agent Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention discloses a frame-based AAQFN package with the frame pre-plastic-package optimization technique adopted and a manufacturing technique thereof. The package is mainly composed of a lead frame, film adhesive, a chip, a bonding wire, etched protruding points and a plastic packaging body, wherein the lead frame is connected with the chip through the film adhesive, the etched protruding points are etched on the front side and the back side of the lead frame, the bonding wire is connected to the lead frame from the chip, the plastic packaging body surrounds the lead frame, the film adhesive, the chip, the bonding wire and the etched protruding points, and the chip, the bonding wire, the etched protruding points and the lead frame form a power supply of a circuit and a signal channel. The manufacturing technique comprises the steps of making pattern etched protruding points on the back side of the frame, carrying out pre-plastic-package on the back side of the frame after etching, making pattern etched protruding points on the front side of the frame, wafer thinning, scribing, chip adhering, pressure welding, plastic packaging, post curing, printing, product separation, detection, packaging and storage. According to the frame-based AAQFN package with the frame pre-plastic-package optimization technique adopted and the manufacturing technique thereof, application to a thin frame can be achieved, the thickness of a product is reduced greatly, designing and technique difficulty is reduced, the machining period of products is shortened, and production efficiency and product reliability are improved.
Description
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Technical field
The invention belongs to the integrated antenna package technical field, be specifically related to a kind of AAQFN packaging part and manufacture craft thereof that adopts pre-plastic packaging optimisation technique based on framework.
Background technology
Integrated circuit is the core of information industry and new and high technology, is the basis of economic development.Integrated antenna package is the chief component of IC industry, and its development is accompanied by the increase of its function and device count always and strides forward.From the nineties in 20th century, it has entered the development track of many number of pins, thin space, small-sized slimming.Carrier-free Background Grid array packages (being AAQFN) is for adapting to the fast-developing a kind of new packing forms be born of electronic product, is that complete electronic set is realized microminaturization, lightweight, the requisite product of networking.
Carrier-free Background Grid array packages element, bottom does not have soldered ball, during welding, pin directly is connected with pcb board, with the electric and mechanical connection of PCB be by Printing Paste on the PCB pad, the solder joint that coordinates the SMT reflow soldering process to form is realized.This technology encapsulation can realize many pins, high density, small-sized slimming encapsulation under the same size condition, has the characteristics such as thermal diffusivity, electrical property and coplanarity are good.
The AAQFN encapsulating products is applicable on a large scale, the encapsulation of very lagre scale integrated circuit (VLSIC).The device great majority of AAQFN encapsulation are for high-grade consumer goods markets such as mobile phone, network and communications equipment, digital camera, microcomputer, notebook computer and various types of flat panel displays.Grasp its core technology, possess mass production capabilities, will greatly dwindle the gap of domestic IC industry and international most advanced level, this product has wide market application foreground.
But, due to restrictions such as technical difficulty, the popularization of AAQFN product on market at present acquires a certain degree of difficulty, and especially, aspect reliability, directly affects use and the life-span of product, become the research of technique difficult point of AAQFN packaging part.
Summary of the invention
Large in order to solve AAQFN product design and technology difficulty, make long asking of construction cycle
Topic, the present invention adopts a kind of AAQFN packaging part and manufacture craft thereof that adopts pre-plastic packaging optimisation technique based on framework, carry out figure at the product back side by etching by the etching period before pre-plastic packaging and pre-plastic packaging, carry out again conventional packaging technology, chip is connected with pin with bonding line, thereby forms circuit integral body.
A kind of AAQFN packaging part and manufacture craft thereof that adopts pre-plastic packaging optimisation technique based on framework, described packaging part mainly is comprised of lead frame, bonding die glue, chip, bonding line, etching salient point and plastic-sealed body.Described lead frame is connected by bonding die glue with chip, and the front and back etching of lead frame has the etching salient point, and bonding line is connected to lead frame from chip.Plastic-sealed body has surrounded lead frame, bonding die glue, chip, bonding line and etching salient point, and chip, bonding line, etching salient point, lead frame have formed power supply and the signalling channel of circuit.
Described fabrication processing is as follows: the framework back side is done after Etching salient point → etching the back side and is carried out pre-plastic packaging → framework front and do Etching salient point → wafer attenuate → scribing → upper core (bonding die) → pressure welding → plastic packaging → rear solidify → printing → separation of products → check → packing → warehouse-in.
This invention can have the thickness that significantly reduces product, effectively reduces design and technology difficulty, and the production cycle of having improved product, weight reduction also improves the packaging part reliability.
The accompanying drawing explanation
Fig. 1 is the lead frame profile;
Fig. 2 is that profile after Etching is done at the lead frame back side;
Fig. 3 is the lead frame back side preformed profile of being honored as a queen;
Fig. 4 is that profile after Etching is done in the lead frame front;
Fig. 5 is product profile after upper core;
Fig. 6 is product profile after pressure welding;
Fig. 7 is the plastic packaged products profile;
Fig. 8 is product profile after rear solidifying;
Fig. 9 is the finished product profile.
In figure, 1 is lead frame, and 2 is bonding die glue, and 3 is chip, and 4 is bonding line, and 5 is the etching salient point, and 6 is plastic-sealed body.
Embodiment
Below in conjunction with accompanying drawing, this invention is described further.
As shown in Figure 9, a kind ofly based on framework, adopt the AAQFN packaging part of pre-plastic packaging optimisation technique mainly to be formed by lead frame 1, bonding die glue 2, chip 3, bonding line 4, etching salient point 5 and plastic-sealed body 6.Described lead frame 1 is connected by bonding die glue 2 with chip 3, and the front and back etching of lead frame 1 has etching salient point 5, and bonding line 4 is connected to lead frame 1 from chip 3.Plastic-sealed body 6 has surrounded lead frame 1, bonding die glue 2, chip 3, bonding line 4 and etching salient point 5, and chip 3, bonding line 4, etching salient point 5, lead frame 1 have formed power supply and the signalling channel of circuit.
As Fig. 1 to as shown in Fig. 9, a kind of manufacture craft that adopts the AAQFN packaging part of pre-plastic packaging optimisation technique based on framework, technical process is as follows: the framework back side is done after Etching salient point → etching the back side and is carried out pre-plastic packaging → framework front and do Etching salient point → wafer attenuate → scribing → upper core (bonding die) → pressure welding → plastic packaging → rear solidify → printing → separation of products → check → packing → warehouse-in.
As shown in the figure, a kind of manufacture craft that adopts the AAQFN packaging part of pre-plastic packaging optimisation technique based on framework, according to following concrete steps, carry out:
1, Etching salient point 5 is done at lead frame 1 back side, and after etching, pre-plastic packaging is carried out at the back side, and then Etching salient point 5 is done in lead frame 1 front.
This method can realize the application on slim framework, has significantly reduced the thickness of product, reduces design and technology difficulty, accelerates the product process-cycle, enhances productivity and product reliability.
Figure is carried out in lead frame 1 front after carrying out figure and etching and completing in lead frame 1 back side, carries out etching, can carry out the encapsulation flow process according to common process.
2, attenuate, scribing: wafer thickness thinning 50 μ m～200 μ m, the above wafer of 150 μ m is with common AAQFN scribing process, but thickness is used double-pole scribing machine and technique thereof at the following wafer of 150 μ m.
3, upper core (bonding die): adopt bonding die glue 2 that chip 3 is connected with lead frame 1, the connection of forming circuit.
4, pressure welding: pressure welding is identical with conventional AAQFN technique.
5, plastic packaging, solidify afterwards, printing, separation of products, check, packing etc. are all identical with conventional AAQFN technique.
Claims (2)
1. an AAQFN packaging part that adopts pre-plastic packaging optimisation technique based on framework, it is characterized in that: described packaging part mainly is comprised of lead frame (1), bonding die glue (2), chip (3), bonding line (4), etching salient point (5) and plastic-sealed body (6); Described lead frame (1) is connected by bonding die glue (2) with chip (3), and the front and back etching of lead frame (1) has etching salient point (5), and bonding line (4) is connected to lead frame (1) from chip (3); Plastic-sealed body (6) has surrounded lead frame (1), bonding die glue (2), chip (3), bonding line (4) and etching salient point (5), and chip (3), bonding line (4), etching salient point (5), lead frame (1) have formed power supply and the signalling channel of circuit.
2. a manufacture craft that adopts the AAQFN packaging part of pre-plastic packaging optimisation technique based on framework is characterized in that: according to following concrete steps, carry out:
(1), lead frame (1) back side does Etching salient point (5), after etching, pre-plastic packaging is carried out at the back side, then Etching salient point (5) is done in lead frame (1) front;
(2), attenuate, scribing: wafer thickness thinning 50 μ m～200 μ m, the above wafer of 150 μ m is with common AAQFN scribing process, but thickness is used double-pole scribing machine and technique thereof at the following wafer of 150 μ m;
(3), upper core (bonding die): adopt bonding die glue (2) that chip (3) is connected with lead frame (1), the connection of forming circuit;
(4), pressure welding: pressure welding is identical with conventional AAQFN technique;
(5), plastic packaging, solidify afterwards, printing, separation of products, check, packing etc. are all identical with conventional AAQFN technique.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310387744.9A CN103489795A (en) | 2013-08-31 | 2013-08-31 | Frame-based AAQFN package with frame pre-plastic-package optimization technique adopted and manufacturing technique thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310387744.9A CN103489795A (en) | 2013-08-31 | 2013-08-31 | Frame-based AAQFN package with frame pre-plastic-package optimization technique adopted and manufacturing technique thereof |
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| Publication Number | Publication Date |
|---|---|
| CN103489795A true CN103489795A (en) | 2014-01-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201310387744.9A Pending CN103489795A (en) | 2013-08-31 | 2013-08-31 | Frame-based AAQFN package with frame pre-plastic-package optimization technique adopted and manufacturing technique thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111755397A (en) * | 2020-07-17 | 2020-10-09 | 杰华特微电子（杭州）有限公司 | Packaging structure of multi-base-island lead frame and packaging method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6294100B1 (en) * | 1998-06-10 | 2001-09-25 | Asat Ltd | Exposed die leadless plastic chip carrier |
| CN102354689A (en) * | 2011-11-04 | 2012-02-15 | 北京工业大学 | Quad flat non-lead (QFN) package with leads arranged in plane array and manufacturing method |
| CN203481191U (en) * | 2013-08-31 | 2014-03-12 | 华天科技（西安）有限公司 | Frame-based AAQFN package adopting pre-plastic-package optimization technology |
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2013
- 2013-08-31 CN CN201310387744.9A patent/CN103489795A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6294100B1 (en) * | 1998-06-10 | 2001-09-25 | Asat Ltd | Exposed die leadless plastic chip carrier |
| CN102354689A (en) * | 2011-11-04 | 2012-02-15 | 北京工业大学 | Quad flat non-lead (QFN) package with leads arranged in plane array and manufacturing method |
| CN203481191U (en) * | 2013-08-31 | 2014-03-12 | 华天科技（西安）有限公司 | Frame-based AAQFN package adopting pre-plastic-package optimization technology |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111755397A (en) * | 2020-07-17 | 2020-10-09 | 杰华特微电子（杭州）有限公司 | Packaging structure of multi-base-island lead frame and packaging method thereof |
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Application publication date: 20140101 |