CN103489785A - 超级结半导体器件的元胞结构和工艺实现方法 - Google Patents
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Abstract
本发明公开了一种深槽型的超级结半导体器件的元胞结构和工艺实现方法，包括第一类型的重掺杂区，其上有第一类型外延漂移区；所述外延漂移区内的两侧有第二类型的外延柱区；第二类型的外延柱区之间有栅极沟槽；所述沟槽内部是栅极多晶硅和电介质隔离层；在所述栅极沟槽与半绝缘柱区之间形成第二类型掺杂的阱区；所述阱区上部形成第一类型掺杂的源区；所述第二类型掺杂的阱区内部有第二类型外延区；所述第二类型外延区下方有金属埋层。本发明能够有效降低超级结产品阱区的串联电阻，防止寄生晶体管的开启，从而提高器件抗雪崩击穿能力以及提高产品的相关的可靠性。
Description
技术领域
本发明涉及一种半导体集成电路中的超级结器件结构，具体涉及一种深槽型的超级结半导体器件的结构设计和工艺实现方法。
背景技术
超级结半导体器件是不断发展的功率-电子系统的内在驱动力。尤其是在节约能源、动态控制、噪音减少等方面。产品主要应用于对能源与负载之间的能量进行控制，并且应当拥有精度高、速度快和功耗低的特点。
但是，超结器件的应用受限于其雪崩耐量。如图3所示，当超级结器件在开启的状态下瞬时关断(产品的栅极电压下降为0或负电压)，由于存在负载电流，感性负载在器件完全关断前，起到类似电流源的负作用，负载电流从工作电流下降为0。此时由于器件沟道关闭，器件源漏两端电压差即为器件应用的阻断电压。阻断电压和负载电流的积分，即为器件在关断瞬间承受的雪崩耐量。当雪崩能量作用于器件，使器件发热超过器件本身所能承受的极限，器件损坏。而如图2所示，当器件发生雪崩击穿时，器件温度的持续升高，寄生晶体管的开启，导致器件所承受的雪崩耐量大幅度增加。
如何抑制与降低寄生晶体管的开启，是本发明研究的课题。
发明内容
本发明所要解决的技术问题是提供一种深槽型的超级结半导体器件的元胞结构以及相应的工艺解决方案，它可以提高超级结产品的雪崩击穿耐量。
为解决上述技术问题，本发明的技术解决方案为：通过在阱区底部有效的埋入埋层金属作为互联层，利用金属本身的低电阻和低温度阻性变化特性，有效降低超级结产品阱区的串联电阻，尤其在器件雪崩击穿发生时刻，最大化的抑制了寄生晶体管的开启，从而提高器件抗雪崩击穿能力以及提高产品的相关的可靠性。同时通过埋层金属上方浓度可调式第二类型外延层的设计，和埋层金属形成欧姆接触确保器件阱区电极的引出同时，对于雪崩击穿时过剩载流子的复合与引导，也是对器件性能优化的帮助。虽然对本发明的描述是参考其具体实施方案进行的，但对本领域的普通技术人员而言，许多其他的变化和修改是显而易见的，本发明不应该局限于本文的特定公开，而应仅由所附权利的要求来限定。
附图说明
下面结合附图和具体实施方式对本发明作进一步详细的说明：
图1本发明深槽型的超级结半导体器件的元胞结构示意图；
图2超级结器件发生雪崩击穿原理图；
图3超级结产品发生雪崩击穿瞬间电流电压变化曲线图；
图4本发明半导体基板剖视图；
图5本发明第二类型掺杂的阱区【7】离子注入，高温驱入后剖视图；
图6本发明第二类型的外延柱区【3】形成后剖视图；
图7本发明栅极沟槽【4】、栅极多晶硅【6】、电介质隔离层【5】形成后剖视图；
图8本发明金属埋层【9】形成后剖视图；
图9本发明第二类型外延区【10】形成后剖视图；
图10本发明第一类型掺杂的源区【8】形成后剖视图；
图11本发明接触孔【11】形成后剖视图；
具体实施方式
本发明公开了一种深槽型的超级结半导体器件的元胞结构和工艺实现方法，包括器件的衬底第一类型的重掺杂区【1】；位于衬底第一类型重掺杂区【1】之上的第一类型外延漂移区【2】；位于衬底重掺杂区【1】之上且位于外延漂移区【2】内的两侧的第二类型的外延柱区【3】；在所述第二类型的外延柱区【3】之间有栅极沟槽【4】；所述沟槽内部是栅极多晶硅【6】；所述栅极沟槽【4】与栅极多晶硅【6】之间有电介质隔离层【5】；在所述栅极沟槽【4】与半绝缘柱区【3】之间形成第二类型掺杂的阱区【7】；所述阱区上部形成第一类型掺杂的源区【8】；源区【8】和阱区【7】通过接触孔【11】连接电位；所述第二类型掺杂的阱区【7】内部有第二类型外延区【10】；所述第二类型外延区【10】下方有金属埋层【9】，金属埋层【9】和所述接触孔【11】相连。
具体工艺制造方法用来实现所述的深槽型的超级结半导体器件的元胞结构，其工艺步骤包括：
STEP1：在第一类型外延漂移区【2】上，利用光刻胶形成离子注入区域，采用离子注入，并用高温驱入的方法形成第二类型掺杂的阱区【7】。
STEP2：在第一类型外延漂移区【2】上形成沟槽Hard mask(硬掩膜)窗口，对所述Hard mask窗口进行等离子方式的沟槽刻蚀，形成硅体内的多个平行沟槽。对所述的沟槽内，通过外延方式成长第二类型的外延柱区【3】，将第二类型掺杂的阱区【7】隔离。
STEP3：在所述第二类型的外延柱区【3】之间，通过选择性掩模方式，形成沟槽Hard mask(硬掩膜)窗口，对所述Hard mask窗口进行等离子方式的沟槽刻蚀，形成硅体内的多个平行的栅极沟槽【4】。栅极沟槽【4】位于在第一类型外延漂移区【2】内，且深度超过第二类型掺杂的阱区【7】。
STEP4：对所述的栅极沟槽【4】内，通过热氧化或CVD化学气象成淀方式形成电介质隔离层【5】。对所述的栅极沟槽【4】内的电介质隔离层【5】的表面开始淀积导电多晶硅，形成器件的栅极多晶硅【6】。
STEP5：在第二类型掺杂的阱区【7】内，第二类型的外延柱区【3】和栅极沟槽【4】之间，通过选择性掩模方式和各项异性或等离子刻蚀的方式，形成沟槽，在沟槽表面淀积金属，形成金属埋层【9】；随后，在所述沟槽内通过外延方式填入第二类型的外延【10】。
STEP6：通过选择性掩模和离子注入方式，在第二类型掺杂的阱区【7】表面形成第一类型掺杂的源区【8】。
STEP7：在硅表面通过CVD技术，淀积一层层间膜。在层间膜上，通过接触孔掩膜，光刻和刻蚀，形成接触孔【11】。所述接触孔【11】穿透硅表面、第一类型掺杂的源区【8】和第二类型的外延【10】，与金属埋层【9】相连。
STEP8：通过任何可使用的所需预金属化清洗来清洗顶表面，在顶表面溅射金属，形成互连层。
STEP9：硅片的背面通过研磨方式进行减薄，同时通过溅射或蒸发的方式形成硅片背面的金属化。金属膜层的形成从硅表面至外，依次为铝、钛、镍、银。金属膜层形成后，在300～450度的惰性气体中合金。
Claims (19)
1.本发明公开了一种深槽型的超级结半导体器件的元胞结构和工艺实现方法，包括器件的衬底第一类型的重掺杂区【1】；位于衬底第一类型重掺杂区【1】之上的第一类型外延漂移区【2】；位于衬底重掺杂区【1】之上且位于外延漂移区【2】内的两侧的第二类型的外延柱区【3】；在所述第二类型的外延柱区【3】之间有栅极沟槽【4】；所述沟槽内部是栅极多晶硅【6】；所述栅极沟槽【4】与栅极多晶硅【6】之间有电介质隔离层【5】；在所述栅极沟槽【4】与半绝缘柱区【3】之间形成第二类型掺杂的阱区【7】；所述阱区上部形成第一类型掺杂的源区【8】；源区【8】和阱区【7】通过接触孔【11】连接电位；所述第二类型掺杂的阱区【7】内部有第二类型外延区【10】；所述第二类型外延区【10】下方有金属埋层【9】，金属埋层【9】和所述接触孔【11】相连。
2.根据权利要求1所述的结构，第一类型的重掺杂区【1】的掺杂浓度要高于第一类型外延漂移区【2】的浓度。
3.根据权利要求1所述的结构，其中，所述第二类型的外延柱区【3】延伸至所述第一类型外延漂移区【2】，且终止于所述第一类型外延漂移区【2】内。
4.根据权利要求1所述的电介质隔离层【5】，进一步包括：氧化物、氮化物、氮氧化物的单一膜层或组合膜层。
5.根据权利要求1所述的多晶硅【6】，其掺杂为N型。
6.根据权利要求1所述的第二类型外延区【10】深度不超过所述第二类型掺杂的阱区【7】，掺杂浓度要高于第二类型掺杂的阱区【7】，与所述金属埋层【9】形成欧姆接触。
7.根据权利要求6所述的第二类型外延区【10】，其体内可以是均一的掺杂，也可以为阶梯分布。
8.根据权利要求1所述的结构，深槽型的超级结半导体器件结构包括一个或多个权利要求1所述的元胞区，在元胞区之间由沟槽隔离，且每个沟槽均由权利要求所述的第二类型的外延柱区【3】构成。
9.根据权利要求1所述衬底第一类型的重掺杂区【1】厚度小于10微米，电阻率小于0.1欧姆*厘米。
10.根据权利要求1所述第一类型外延漂移区【2】，其电阻率1～10欧姆*厘米。
11.根据权利要求1所述的金属埋层【9】，为金属和硅合金化合物，金属材质为钛、或铝、或钴、或钨。
12.一种制造方法用来实现权利要求1所述的深槽型的超级结半导体器件的元胞结构，其工艺步骤包括：
STEP1：在第一类型外延漂移区【2】上，利用光刻胶形成离子注入区域，采用离子注入，并用高温驱入的方法形成第二类型掺杂的阱区【7】。
STEP2：在第一类型外延漂移区【2】上形成沟槽Hard mask(硬掩膜)窗口，对所述Hard mask窗口进行等离子方式的沟槽刻蚀，形成硅体内的多个平行沟槽。对所述的沟槽内，通过外延方式成长第二类型的外延柱区【3】，将第二类型掺杂的阱区【7】隔离。
STEP3：在所述第二类型的外延柱区【3】之间，通过选择性掩模方式，形成沟槽Hard mask(硬掩膜)窗口，对所述Hard mask窗口进行等离子方式的沟槽刻蚀，形成硅体内的多个平行的栅极沟槽【4】。栅极沟槽【4】位于在第一类型外延漂移区【2】内，且深度超过第二类型掺杂的阱区【7】。
STEP4：对所述的栅极沟槽【4】内，通过热氧化或CVD化学气象成淀方式形成电介质隔离层【5】。对所述的栅极沟槽【4】内的电介质隔离层【5】的表面开始淀积导电多晶硅，形成器件的栅极多晶硅【6】。
STEP5：在第二类型掺杂的阱区【7】内，第二类型的外延柱区【3】和栅极沟槽【4】之间，通过选择性掩模方式和各项异性或等离子刻蚀的方式，形成沟槽，在沟槽表面淀积金属，形成金属埋层【9】；随后，在所述沟槽内通过外延方式填入第二类型的外延【10】。
STEP6：通过选择性掩模和离子注入方式，在第二类型掺杂的阱区【7】表面形成第一类型掺杂的源区【8】。
STEP7：在硅表面通过CVD技术，淀积一层层间膜。在层间膜上，通过接触孔掩膜，光刻和刻蚀，形成接触孔【11】。所述接触孔【11】穿透硅表面、第一类型掺杂的源区【8】和第二类型的外延【10】，与金属埋层【9】相连。
STEP8：通过任何可使用的所需预金属化清洗来清洗顶表面，在顶表面溅射金属，形成互连层。
STEP9：硅片的背面通过研磨方式进行减薄，同时通过溅射或蒸发的方式形成硅片背面的金属化。金属膜层的形成从硅表面至外，依次为铝、钛、镍、银。金属膜层形成后，在300～450度的惰性气体中合金。
13.根据权利要求12STEP2所述沟槽内，通过外延方式成长第二类型的外延柱区【3】。在成长过程中同时在外延设备的腔体内，通入氯化氢气体，在600～1000摄氏度的高温下完成边成长边刻蚀的外延成长过程，形成沟槽2侧壁和底部均匀的外延层。
14.根据权利要求12STEP4所述的沟槽内电电介质隔离层【5】的表面，淀积一层厚度在5000～12000埃的多晶硅。在多晶硅淀积同时在设备的腔体内通入磷烷，在600～1000摄氏度的高温下完成分解，实现对多晶硅的N型掺杂。
15.根据权利要求14所述的多晶硅淀积完成后，通过多晶硅回刻工艺，去除硅表面的多晶硅且完成对沟槽内的多晶硅填充步骤。
16.根据权利要求12STEP5所述的金属埋层【9】形成后。
17.根据权利要求12STEP7所述的在硅表面通过CVD技术，淀积一层层间膜；层间膜，可以是BPSG(硼磷酸硅玻璃)，也可是BPSG和SiN的组合膜层；其中BPSG的厚度在5000～10000埃，SiN的厚度在1000～3000埃。通过650～950摄氏度BPSG回流，平坦化器件表面。
18.根据权利要求12STEP7所述的接触孔的刻蚀可以是湿法刻蚀，也可用湿法加干法的组合。
19.根据权利要求12STEP8所述的金属的互连层淀积后，需要进行惰性气体中的高温退火。退火温度控制在650～800度，时间小于2分钟。
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