CN103456707A - 半导体封装结构及其制造方法 - Google Patents

半导体封装结构及其制造方法 Download PDF

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CN103456707A
CN103456707A CN2013104003358A CN201310400335A CN103456707A CN 103456707 A CN103456707 A CN 103456707A CN 2013104003358 A CN2013104003358 A CN 2013104003358A CN 201310400335 A CN201310400335 A CN 201310400335A CN 103456707 A CN103456707 A CN 103456707A
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semiconductor element
filler
protective layer
spatial accommodation
layer
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CN103456707B (zh
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高金利
李长祺
赖逸少
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

本发明是关于一种半导体封装结构及其制造方法。该半导体封装结构具有一半导体元件，其包括一本体、数个导电通道及至少一填充物。该等导电通道贯穿该本体。该填充物是位于该本体内，其中该填充物的热膨胀系数与该本体和该等导电通道的热膨胀系数不同。藉此，可调整该半导体元件整体的热膨胀系数，减少翘曲。

Description

半导体封装结构及其制造方法
技术领域
本发明是关于一种半导体封装结构及半导体工艺。详言之，本发明是关于一种半导体元件及具有该半导体元件的半导体封装结构，以及半导体元件的制造方法。
背景技术
已知堆迭式封装结构通常包含一芯片、一半导体元件（例如：一中介板）及一基板。该芯片配置于该半导体元件且电性连接至该半导体元件。该半导体元件利用数个焊球连接至该基板。由于该半导体元件的材质与该基板的材质不同，因此其热膨胀系数(CTE)也有所差异。当该已知堆迭式封装结构受热时，由于该半导体元件的材质与该基板的热膨胀系数不同，其二者的翘曲程度不同，会导致所述焊球容易发生破坏。最主要的破坏是发生该等焊球和该半导体元件的界面，即该等焊球会从该半导体元件剥离(Peeling)；次要的破坏发生在该等焊球本身，即该等焊球会断裂(Fracture)。一旦上述破坏发生，该半导体元件及该基板间即形成断路，使得该已知堆迭式封装结构的寿命即告终止，导致该已知堆迭式封装结构的可靠度无法提高。此外，随着该半导体元件的尺寸越大，上述破坏情况会更明显，而封装结构的可靠度会更低。
发明内容
本揭露的一方面是关于一种半导体元件。在一实施例中，该半导体元件包括一本体、至少一容纳空间，贯穿该本体数个导电通道(Conductive Via)及至少一填充物。该等导电通道贯穿该本体。该填充物是位于该本体内，其中该填充物的热膨胀系数（CTE）与该本体和该等导电通道的热膨胀系数不同。
本揭露的另一方面是关于一种半导体封装结构。在一实施例中，该半导体封装结构包括一基板、一半导体元件、数个焊球及至少一芯片。该半导体元件是位于该基板上方，且包括一本体、数个导电通道及至少一填充物。该等导电通道贯穿该本体。该填充物是位于该本体内，其中该填充物的热膨胀系数与该本体和该等导电通道的热膨胀系数不同。该等焊球连接该基板及该半导体元件，且电性连接至该等导电通道。该芯片是附着至该半导体元件。
在该半导体封装结构中，该填充物添加至该半导体元件可以调整该半导体元件整体的热膨胀系数，使得该半导体元件接合至该基板后，不会因为彼此热膨胀系数不匹配（Mismatch）而产生严重翘曲。再者，该本体是被该填充物分割成数个独立的区块，因此，当该半导体元件受热时，该等区块是个别发生翘曲，而不会全部累加在一起，藉此，可大量减少该半导体元件整体的翘曲程度。此外，随着该半导体元件的尺寸越大（例如大于10mm*10mm），上述减少翘曲的效果会更明显，而可增加该半导体封装结构的可靠度，同时可增加堆迭于该半导体元件上的芯片的数目。
本揭露的另一方面是关于一种半导体元件的制造方法。在一实施例中，该制造方法包括以下步骤：(a)从一本体的一上表面形成数个孔及至少一容纳空间；(b)形成一导电通道于每一孔中；(c)形成至少一填充物于该至少一容纳空间，其中该填充物的热膨胀系数与该本体和该等导电通道的热膨胀系数不同；(d)形成一上重布层及一上保护层于该本体的上表面，其中该上重布层连接至该等导电通道，该上保护层覆盖该上重布层，该上保护层具有至少一上开口以显露部份该上重布层，并形成至少一上凸块，位于该上保护层的上开口内且接触该上重布层；(e)从该本体的一下表面薄化该本体，以显露该等导电通道；及(f)形成一下重布层及一下保护层于该本体的下表面，其中该下重布层连接至该等导电通道，该下保护层覆盖该下重布层，该下保护层具有至少一下开口以显露部份该下重布层，并形成至少一下凸块，位于该下保护层的下开口内且接触该下重布层。
附图说明
图1显示本发明半导体元件的一实施例的局部剖视示意图。
图2显示图1的半导体元件的俯视示意图，其中仅显示该填充物及该等焊球的相对位置。
图3至图9显示本发明半导体元件的制造方法一实施例的示意图。
图10显示本发明半导体元件的另一实施例的剖视示意图。
图11至图14显示本发明半导体元件的制造方法的另一实施例的示意图。
图15显示本发明半导体元件的另一实施例的剖视示意图。
图16显示本发明半导体元件的另一实施例的俯视示意图，其中仅显示该填充物及该等焊球的相对位置。
图17显示本发明半导体元件的另一实施例的俯视示意图，其中仅显示该填充物及该等焊球的相对位置。
图18显示本发明半导体元件的另一实施例的俯视示意图，其中仅显示该填充物及该等焊球的相对位置。
图19显示本发明半导体元件的另一实施例的俯视示意图，其中仅显示该填充物及该等焊球的相对位置。
图20显示本发明半导体元件的另一实施例的俯视示意图，其中仅显示该填充物及该等焊球的相对位置。
图21显示本发明半导体封装结构的一实施例的剖视示意图。
具体实施方式
参考图1，显示本发明半导体元件的一实施例的局部剖视示意图。该半导体元件1包括一本体10、数个导电通道(Conductive Via)12、至少一填充物14、一上重布层16、一下重布层18、一第一上保护层20、一第二上保护层22、一第一下保护层24、一第二下保护层26、至少一上凸块28、至少一下凸块30及数个焊球32。
该本体10的材质可以是例如硅、锗、砷化镓等半导体材料。该本体10具有一上表面101、一下表面102、数个孔103及至少一容纳空间104。在本实施例中，该等孔103为圆柱状，其直径为5μm至200μm；该容纳空间104为一线型沟槽（Trench），其宽度为5μm至200μm，且于该本体10的上表面101具有至少一第一开口1041。该容纳空间104是位于至少二个孔103之间，且该第一开口1041于该本体10上表面101的线段的长度大于二个孔103的间距。在本实施例中，该等孔103及该容纳空间104皆贯穿该本体10，然而，在其他实施例中，仅有该等孔103贯穿该本体10，而该容纳空间104可不贯穿该本体10。此外，
该等导电通道12具有一衬层（Liner）121及一导电金属122。该衬层121为绝缘材料，其是位于该孔103的侧壁，且定义出一中心孔。该导电金属122的材质为铜，其是填满该中心孔，且显露于该本体10的上表面101及下表面102，做为电性连接之用。
该填充物14为聚合物(Polymer)或金属，填充于该本体10的该容纳空间104内。亦即，该填充物14是位于至少二个导电通道12之间。在本实施例中，该填充物14为聚合物(Polymer)，其热膨胀系数（CTE）是大于10ppm/℃；该本体10的材质为硅，其热膨胀系数（CTE）约为3ppm/℃；该导电通道12的材质为铜，其热膨胀系数（CTE）约为17ppm/℃。因此，该填充物14的热膨胀系数与该本体10和该等导电通道12的热膨胀系数不同，且该填充物14的热膨胀系数是大于该本体10的热膨胀系数。要说明的是，该填充物14可不做为电性连接的用，其可不连接任何线路，即使该填充物14是金属材质也是如此。
该上重布层16邻接于该本体10的上表面101，且连接至该等导电通道12。在本实施例中，该上重布层16是位于该第一上保护层20上及其开口201内，以接触该等导电通道12。
该下重布层18邻接于该本体10的下表面102，且连接至该等导电通道12。在本实施例中，该下重布层18是位于该第一下保护层24上及其开口241内，以接触该等导电通道12。
该第一上保护层20是覆盖该本体10的上表面101，且具有数个开口201以显露该等导电通道12。要注意的是，该第一上保护层20是覆盖该填充物14。该第一上保护层20的材质为苯环丁烯(Benzocyclobutene,BCB)或聚酰亚胺(Polyimide,PI)。
该第二上保护层22位于该第一上保护层20上，且覆盖该上重布层16。该第二上保护层22具有至少一上开口221以显露部份该上重布层16。该第二上保护层22的材质为苯环丁烯(Benzocyclobutene,BCB)或聚酰亚胺(Polyimide,PI)，且该第一上保护层20及该第二上保护层22的材质可相同或不同。该第一下保护层24是覆盖该本体10的下表面102，且具有数个开口241以显露该等导电通道12。要注意的是，该第一下保护层24是覆盖该填充物14。该第一下保护层24的材质为苯环丁烯(Benzocyclobutene,BCB)或聚酰亚胺(Polyimide,PI)。
该第二下保护层26位于该第一下保护层24上，且覆盖该下重布层18。该第二下保护层26具有至少一下开口261以显露部份该下重布层18。该第二下保护层26的材质为苯环丁烯(Benzocyclobutene,BCB)或聚酰亚胺(Polyimide,PI)，且该第一下保护层24及该第二下保护层26的材质可相同或不同。
该上凸块28位于该第二上保护层22的上开口221内且接触该上重布层16。该下凸块30位于该第二下保护层26的下开口261内且接触该下重布层18。该等焊球32是连接至该下凸块30。可以理解的是，该半导体元件1可以不包括该等焊球32。
参考图2，显示图1的半导体元件的俯视示意图，其中仅显示该填充物14及该等焊球32的相对位置。
该容纳空间104于该本体10上表面101的该第一开口1041的长度是大于二个焊球32的间距。如图所示，该第一开口1041在该本体10的上表面101上形成数个线段，且该等线段排列成特定图案，例如：矩形、L形、十字形或网格状。在本实施例中，该等线段排列成网格状，每一焊球32是位于每一网格的相对位置内。此外，所有该第一开口1041的面积总和与该本体10的上表面101的全部表面积的比值为5%至50%，较佳为5%至20%。配合参考图1及图2，可看出该本体10是被该填充物14分割成数个独立（互不连接）的区块。
在该半导体元件1中，该填充物14的添加可以调整该半导体元件1整体的热膨胀系数，使得该半导体元件1接合至其他元件（例如：印刷电路板）后，不会因为彼此热膨胀系数不匹配（Mismatch）而产生严重翘曲。再者，该本体10是被该填充物14分割成数个独立的区块，因此，当该半导体元件1受热时，该等区块是个别发生翘曲，而不会全部累加在一起，藉此，可大量减少该半导体元件1整体的翘曲程度。此外，随着该半导体元件1的尺寸越大（例如大于10mm*10mm），上述减少翘曲的效果会更明显，而可增加接合结构的可靠度。
参考图3至图9，显示本发明半导体元件的制造方法一实施例的示意图。
参考图3，提供该本体10。该本体10的材质可以是例如硅、锗、砷化镓等半导体材料，其具有一上表面101及一下表面102。接着，从该本体10的上表面101形成数个孔103及至少一容纳空间104。在本实施例中，该等孔103为圆柱状，其直径为5μm至200μm；该容纳空间104为一线型沟槽（Trench），其宽度为5μm至200μm。在本步骤，该等孔103及该容纳空间104皆未贯穿该本体10。此外，该容纳空间104是位于至少二个孔103之间。
该第一开口1041在该本体10的上表面101上形成数个线段（如图2所示），且该等线段排列成特定图案，例如：矩形、L形、十字形或网格状。在本实施例中，该等线段排列成网格状。此外，所有该第一开口1041的面积总和与该本体10的上表面101的全部表面积的比值为5%至50%，较佳为5%至20%。
参考图4，形成该衬层121于该孔103的侧壁，且定义出一中心孔123。在本实施例中，该衬层121为绝缘材料，其仅位于该孔103的侧壁，而不位于该容纳空间104的侧壁。
参考图5，将该导电金属122填满该中心孔123，以于每一孔103中形成一导电通道12。在本实施例中，该导电金属122的材质为铜。
参考图6，形成该填充物14至该容纳空间104。该填充物14为聚合物(Polymer)或金属，其填满该容纳空间104。在本实施例中，该填充物14为聚合物(Polymer)，其热膨胀系数（CTE）是大于10ppm/℃；该本体10的材质为硅，其热膨胀系数（CTE）约为3ppm/℃；该导电通道12的材质为铜，其热膨胀系数（CTE）约为17ppm/℃。因此，该填充物14的热膨胀系数与该本体10和该等导电通道12的热膨胀系数不同，且该填充物14的热膨胀系数是大于该本体10的热膨胀系数。要说明的是，该填充物14并不做为电性连接之用，其并不连接任何线路，即使该填充物14是金属材质也是如此。
参考图7，形成该第一上保护层20、该上重布层16、该第二上保护层22及该上凸块28于该本体10的上表面101。该第一上保护层20覆盖该本体10的上表面101，且具有数个开口201以显露该等导电通道12。要注意的是，该第一上保护层20覆盖该填充物14。该上重布层16邻接于该本体10的上表面101，且连接至该等导电通道12。在本实施例中，该上重布层16是位于该第一上保护层20上及其开口201内，以接触该等导电通道12。该第二上保护层22位于该第一上保护层20上，且覆盖该上重布层16。该第二上保护层22具有至少一上开口221以显露部份该上重布层16。该第一上保护层20及该第二上保护层22的材质为苯环丁烯(Benzocyclobutene,BCB)或聚酰亚胺(Polyimide,PI)，且该第一上保护层20及该第二上保护层22的材质可相同或不同。该上凸块28位于该第二上保护层22的上开口221内且接触该上重布层16。
参考图8，从该本体10的下表面102薄化该本体10，以显露该等导电通道12及该填充物14。此时，该等导电通道12及该填充物14皆贯穿该本体10。
参考图9，形成该第一下保护层24、该下重布层18、该第二下保护层26及该下凸块30于该本体10的下表面102。该第一下保护层24覆盖该本体10的下表面102，且具有数个开口241以显露该等导电通道12。要注意的是，该第一下保护层24覆盖该填充物14。该下重布层18邻接于该本体10的下表面102，且连接至该等导电通道12。在本实施例中，该下重布层18是位于该第一下保护层24上及其开口241内，以接触该等导电通道12。该第二下保护层26位于该第一下保护层24上，且覆盖该下重布层18。该第二下保护层26具有至少一下开口261以显露部份该下重布层18。该第一下保护层24及该第二下保护层26的材质为苯环丁烯(Benzocyclobutene,BCB)或聚酰亚胺(Polyimide,PI)，且该第一下保护层24及该第二下保护层26的材质可相同或不同。该下凸块30位于该第二下保护层26的下开口261内且接触该下重布层18。接着，形成该等焊球32于该下凸块30上，以形成该半导体元件1，如图1所示。
参考图10，显示本发明半导体元件的另一实施例的剖视示意图。本实施例的半导体元件1a与图1所示的半导体元件1的大致相同，其不同处如下所述。在本实施例中，该半导体元件1a更包括数个电性元件（例如电晶体105），其位于该本体10的上表面101，且被该第一上保护层20所覆盖。
参考图11至图14，显示本发明半导体元件的制造方法的另一实施例的示意图。在本实施例中，「前半段」工艺与图3至图6的制造方法中相同。本实施例的制造方法接续图6的步骤。
参考图11，在形成该等导电通道12及该填充物14后，更于该本体10的上表面101形成该等电性元件（例如电晶体105）。
参考图12，形成该第一上保护层20、该上重布层16、该第二上保护层22及该上凸块28于该本体10的上表面101。要注意的是，该第一上保护层20覆盖该等电性元件。
参考图13，从该本体10的下表面102薄化该本体10，以显露该等导电通道12及该填充物14。此时，该等导电通道12及该填充物14皆贯穿该本体10。
参考图14，形成该第一下保护层24、该下重布层18、该第二下保护层26及该下凸块30于该本体10的下表面102。接着，形成该等焊球32于该下凸块30上，以形成该半导体元件1a，如图10所示。
参考图15，显示本发明半导体元件的另一实施例的剖视示意图。本实施例的半导体元件1b与图1所示的半导体元件1的大致相同，其不同处如下所述。在本实施例中，该半导体元件1b更包括至少一绝缘层15，其位于该填充物14与该容纳空间104的侧壁之间。该绝缘层15的材质与该衬层121的材质相同或不同。在本实施例中，该绝缘层15的材质与该衬层121的材质相同，且是在图4的步骤同时形成。此外，由于增加该绝缘层15，因此，该填充物14可以是金属，其不仅可以调整该半导体元件1b整体的热膨胀系数，而且可做为散热路径。要说明的是，该填充物14可不做为电性连接之用，其可不连接任何线路。
参考图16，显示本发明半导体元件的另一实施例的俯视示意图，其中仅显示该填充物14及该等焊球32的相对位置。本实施例的半导体元件1c与图2所示的半导体元件1的大致相同，其不同处如下所述。在本实施例中，该半导体元件1c的该第一开口1041在该本体10的上表面101排列成网格状，且单一网格比图2所示的半导体元件1的网格大，其中位于中间的单一网格涵盖四个焊球32。
参考图17，显示本发明半导体元件的另一实施例的俯视示意图，其中仅显示该填充物14及该等焊32球的相对位置。本实施例的半导体元件1d与图2所示的半导体元件1的大致相同，其不同处如下所述。在本实施例中，该半导体元件1d的该第一开口1041在该本体10的上表面101排列成网格状，且单一网格比图2所示的半导体元件1的网格大，其中位于中间的单一网格涵盖八个焊球32。
参考图18，显示本发明半导体元件的另一实施例的俯视示意图，其中仅显示该填充物14及该等焊球32的相对位置。本实施例的半导体元件1e与图2所示的半导体元件1的大致相同，其不同处如下所述。在本实施例中，该半导体元件1e的该第一开口1041在该本体10的上表面101排列成一个矩形及一个十字形，其中该十字形可视为二个L形的组合。
参考图19，显示本发明半导体元件的另一实施例的俯视示意图，其中仅显示该填充物14及该等焊球32的相对位置。本实施例的半导体元件1f与图2所示的半导体元件1的大致相同，其不同处如下所述。在本实施例中，该半导体元件1f的该第一开口1041在该本体10的上表面101排列成一个十字形或二个L形。
参考图20，显示本发明半导体元件的另一实施例的俯视示意图，其中仅显示该填充物14及该等焊球32的相对位置。本实施例的半导体元件1g与图2所示的半导体元件1的大致相同，其不同处如下所述。在本实施例中，该半导体元件1g的该第一开口1041在该本体10的上表面101排列成一个矩形。
参考图21，显示本发明半导体封装结构的一实施例的剖视示意图。该半导体封装结构4包括一基板41、一半导体元件1、数个焊球32、至少一芯片(例如芯片42)、一底胶46及一封胶材料47。在本实施例中，该基板41为一印刷电路板(PCB)基板。该半导体元件1是位于该基板41上方。该半导体元件1是与图1及图2所示的半导体元件1相同，然而，该半导体元件1也可以替换成图10的半导体元件1a、图15的半导体元件1b、图16的半导体元件1c、图17的半导体元件1d、图18的半导体元件1e、图19的半导体元件1f或图20的半导体元件1g。该等焊球32连接该基板41及该半导体元件1的该下凸块30，且电性连接至该等导电通道12。
该至少一芯片(例如芯片42)配置于该半导体元件1，且电性连接至该半导体元件1。在本实施例中，该至少一芯片包含一第一芯片42（例如：蓝芽(BT)芯片）、第二芯片43（例如：射频(RF)芯片）、第三芯片44（例如：电源管理(PMIC)芯片）及第四芯片45（例如：侦测器(Detector)）。该第一芯片42具有数个第一凸块421，连接至该等上凸块28。该第二芯片43具有数个第二凸块431，连接至该等上凸块28。该第三芯片44具有数个第三凸块441，连接至该等上凸块28。该第四芯片45具有数个第四凸块451，连接至该等上凸块28。
该底胶46是位于该等芯片42,43,44,45及该半导体元件1之间，以保护该等第一凸块421、该等第二凸块431、该等第三凸块441、该等第四凸块451及该等上凸块28。该封胶材料47是位于该基板41上，以覆盖该等芯片42,43,44,45的一上表面。在其他实施例中，可不需要该封胶材料47，仅以该底胶46包覆该等凸块421,431,441,451及该等上凸块28。或者，可不需要该底胶46，仅以该封胶材料47保护该等芯片42,43,44,45、该等凸块421,431,441,451及该等上凸块28。另外，该底胶46与该封胶材料47的材质相同或不同。
在该半导体封装结构4中，该填充物14添加至该半导体元件1可以调整该半导体元件1整体的热膨胀系数，使得该半导体元件1接合至该基板41后，不会因为彼此热膨胀系数不匹配（Mismatch）而产生严重翘曲。再者，该本体10被该填充物14分割成数个独立的区块，因此，当该半导体元件1受热时，该等区块个别发生翘曲，而不会全部累加在一起，藉此，可大量减少该半导体元件1整体的翘曲程度。此外，随着该半导体元件1的尺寸越大（例如大于10mm*10mm），上述减少翘曲的效果会更明显，而可增加该半导体封装结构4的可靠度，同时可增加堆迭芯片（例如该等芯片42,43,44,45）的数目。
参考表1，显示本发明不同型式半导体元件利用焊球32接合至一基板的接合结构中，保护层所受正向应力(Normal Stress)的模拟结果比较表，其中比较例为已知技术，其未添加该填充物14；实例1为图2的半导体元件1，其所有该第一开口1041的面积总和与该本体10的上表面101的全部表面积的比值为40%；实例2为图16的半导体元件1c，其所有该第一开口1041的面积总和与该本体10的上表面101的全部表面积的比值为20%；实例3为图17的半导体元件1d，其所有该第一开口1041的面积总和与该本体10的上表面101的全部表面积的比值为10%；实例4为图18的半导体元件1e，其所有该第一开口1041的面积总和与该本体10的上表面101的全部表面积的比值为5%；实例5为图19的半导体元件1f，其所有该第一开口1041的面积总和与该本体10的上表面101的全部表面积的比值为2.5%；实例6为图20的半导体元件1g，其所有该第一开口1041的面积总和与该本体10的上表面101的全部表面积的比值为2.5%。该半导体元件的材质为硅，该填充物14为聚合物(Polymer)，该保护层是指该第一下保护层24。
表1：不同型式半导体元件的保护层所受正向应力的模拟结果
Figure BDA0000377789340000101
Figure BDA0000377789340000111
由表1可知，实例1至实例3的安全系数皆有明显提升，实例4至实例6则与比较例差不多，由表1模拟结果可知，第一开口1041的面积总和与该本体10的上表面101的全部表面积的比值大于5%以上时，可具有较佳的安全系数，例如大于1.00。
参考表2，显示本发明不同型式半导体元件利用焊球32接合至一基板的接合结构中，焊球破坏寿命（Solder Fatigue Life）的模拟结果比较表，其中比较例及实例1至实例6的参数与上述表1相同。
表2：不同型式半导体元件的焊球破坏寿命的模拟结果
Figure BDA0000377789340000112
Figure BDA0000377789340000121
由表2可知，实例1至实例3的效能皆有明显提升，，而实例4至实例6的效能仅略高于比较例，由表2模拟结果可知，第一开口1041的面积总和与该本体10的上表面101的全部表面积的比值大于5%以上时，可具有较显著的效能，例如大于1000%。
惟上述实施例仅为说明本发明的原理及其功效，而非用以限制本发明。因此，习于此技术的人士对上述实施例进行修改及变化仍不脱本发明的精神。本发明的权利范围应如权利要求书所列。

Claims (20)

1.一种半导体元件，包括：
一本体；
数个导电通道，贯穿该本体；
至少一容纳空间，贯穿该本体；及
至少一填充物，位于该容纳空间内，其中该填充物的热膨胀系数与该本体和所述导电通道的热膨胀系数不同。
2.如权利要求1的半导体元件，其特征在于，该本体具有数个孔，贯穿该本体，每一所述导电通道具有一衬层及一导电金属，该衬层是位于该孔的侧壁，且定义出一中心孔，该导电金属是填满该中心孔。
3.如权利要求1的半导体元件，其特征在于，该填充物是位于至少二个导电通道之间。
4.如权利要求1的半导体元件，其特征在于，该至少一容纳空间于该本体的一表面具有至少一第一开口。
5.如权利要求1的半导体元件，其特征在于，该本体为半导体材料，该填充物为聚合物或金属。
6.如权利要求4的半导体元件，其特征在于，该第一开口的长度大于二个导电通道的间距。
7.如权利要求4的半导体元件，其特征在于，所有该至少一第一开口的面积总和与该本体的该表面的全部表面积的比值为5%至50%。
8.如权利要求1的半导体元件，其特征在于，更包括至少一绝缘层，位于该填充物与该容纳空间的侧壁之间。
9.如权利要求4的半导体元件，其特征在于，该至少一第一开口在该本体的该表面上形成至少一线段，该至少一线段排列成矩形、L形、十字形或网状。
10.如权利要求1的半导体元件，其特征在于，该本体更包括数个电性元件。
11.一种半导体封装结构，包括：
一基板；
一半导体元件，位于该基板上方，该半导体元件包括：
一本体；
数个导电通道，贯穿该本体；
至少一容纳空间，贯穿该本体；及
至少一填充物，位于该容纳空间内，其中该填充物的热膨胀系数与该本体和所述导电通道的热膨胀系数不同；
数个焊球，连接该基板及该半导体元件，且电性连接至所述导电通道；及
至少一芯片具有至少一凸块，配置于该半导体元件上方。
12.如权利要求11的半导体封装结构，其特征在于，该至少一容纳空间于该本体的一表面具有至少一第一开口。
13.如权利要求12的半导体封装结构，其特征在于，所有该至少一第一开口的面积总和与该本体的该表面的全部表面积的比值为5%至50%。
14.如权利要求11的半导体封装结构，其特征在于，更包括一底胶包覆该至少一凸块。
15.如权利要求11的半导体封装结构，其特征在于，更包括一封胶材料覆盖该至少一芯片的一上表面。
16.如权利要求11的半导体封装结构，其特征在于，该本体更包括数个电性元件。
17.一种半导体元件的制造方法，包括以下步骤：
(a)从一本体的一上表面形成数个孔及至少一容纳空间；
(b)形成一导电通道于每一孔中；
(c)形成至少一填充物于该至少一容纳空间，其中该填充物的热膨胀系数与该本体和该导电通道的热膨胀系数不同；
(d)形成一上重布层及一上保护层于该本体的上表面，其中该上重布层连接至所述导电通道，该上保护层覆盖该上重布层，该上保护层具有至少一上开口以显露部份该上重布层，并形成至少一上凸块于该上保护层的上开口内且接触该上重布层；
(e)从该本体的一下表面薄化该本体，以显露所述导电通道；及
(f)形成一下重布层及一下保护层于该本体的下表面，其中该下重布层连接至所述导电通道，该下保护层覆盖该下重布层，该下保护层具有至少一下开口以显露部份该下重布层，并形成至少一下凸块于该下保护层的下开口内且接触该下重布层。
18.如权利要求17的制造方法，其特征在于，步骤(a)中，该至少一容纳空间为线型沟槽，且于该本体的上表面具有至少一第一开口，所有该至少一第一开口的面积总和与该本体的上表面的全部表面积的比值为5%至50%。
19.如权利要求17的制造方法，其特征在于，该步骤(c)之后更包括一形成数个电性元件于该本体的步骤。
20.如权利要求17的制造方法，其特征在于，更包括步骤(g)形成一焊球连接至该下凸块。
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US10056325B2 (en) 2018-08-21
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