CN103440195A - Switch chip verification method and device based on logic chip - Google Patents
Switch chip verification method and device based on logic chip Download PDFInfo
- Publication number
- CN103440195A CN103440195A CN2013102900965A CN201310290096A CN103440195A CN 103440195 A CN103440195 A CN 103440195A CN 2013102900965 A CN2013102900965 A CN 2013102900965A CN 201310290096 A CN201310290096 A CN 201310290096A CN 103440195 A CN103440195 A CN 103440195A
- Authority
- CN
- China
- Prior art keywords
- chip
- configuration
- logic
- emulation
- platform
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Tests Of Electronic Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention discloses a switch chip verification method based on a logic chip. The switch chip verification method based on the logic chip comprises the steps that a test case is designed according to network protocol standards and the configuration interface information of the logic chip, wherein the configuration information of the test case is stored in the logic chip; a chip configuration conversion module reads the configuration information of the test case from the logic chip and converts the configuration information into configuration information required for verifying the chip; and chip verification is performed based on an independent simulation platform. The invention additionally provides a switch chip verification device based on the logic chip. The switch chip verification device based on the logic chip comprises a case design unit, a chip configuration conversion unit, a logic chip unit and the simulation platform which is connected with the chip configuration conversion unit through a driver layer. The switch chip verification method based on the logic chip and the switch chip verification device based on the logic chip have the advantages that the goal of synchronously performing the design process of the test case and the design process of the chip is realized, the overall research and development period of the chip is shortened, the cost of chip verification and the input of human resources are saved and the chip verification efficiency is improved.
Description
Technical field
The present invention relates to exchanger chip verification method field, especially relate to a kind of exchanger chip verification method and device of logic-based chip.
Background technology
Develop rapidly along with the communication technology, switch of today is no longer a simple message forwarding equipment, a but integrated numerous procotol Standard IN network node, in order to adapt to the development of network, exchanger chip is constantly improving exchange capacity on the one hand, supporting more and more abundanter network standard on the other hand, these have brought huge workload to undoubtedly the checking of exchanger chip in R&D process.
The research and development of a exchanger chip have high input, the cycle is long, once and a switch ASIC chip go into operation after the defect of its existence can not make up by increment, so, in the design process of chip, the checking of chip is extremely important.In R&D process, the checking of chip must be carried out simultaneously on three platforms, these three platforms are respectively higher level lanquage emulation checking, the emulation of RTL checking, checking based on the FPGA hardware simulation platform, checking based on these three independent platforms all needs to safeguard a large amount of test cases, in R&D process, the discovery of chip defect, solve, the trace adjustment of chip design all must be thrown in a large amount of resources and time and be carried out the synchronous of test case, these drop into R&D costs and the R&D cycle that has affected greatly chip, become the bottleneck of monster chip research and development.
At present, general exchanger chip design verification flow process as shown in Figure 1, after the chip design standard has been developed, for higher level lanquage emulation checking, the emulation of RTL checking, based on these three of FPGA hardware simulation platforms emulation platform independently, start with and design separately corresponding test case from the chip design standard by different testers respectively, then the test case based on these three kinds of platforms is issued respectively to each self-corresponding model-driven layer: higher level lanquage model-driven layer, RTL model-driven layer, the FPGA hardware platform drives layer, thereby drive the higher level lanquage realistic model, the RTL realistic model, the FPGA hardware simulation model completes the checking of chip configuration.
There is following problem in the verification method of this chip: (1) test case is directly designed for the design specifications of chip, like this, in R&D process, chip design is adjusted for the change of defect or the part of design, a large amount of test cases need to be carried out corresponding synchronous, and at different chip chambers, because the design architecture of chip changes, very easily cause all test cases to need redesign, can't do incremental development; (2) Test Sample Design must can't carry out with the exploitation of chip design standard when chip design has been developed simultaneously, and the R&D cycle of chip is long; (3) in the face of the test case of three kinds of platforms, although all come from the chip design standard, still need to safeguard separately test case library separately, work that it is a large amount of overlapping to exist, cause the waste of human resources.
Summary of the invention
The object of the invention is to overcome the defect of prior art, a kind of exchanger chip verification method and device of logic-based chip are provided, for the logic chip design test case, test case can be reused, and realizes that Test Sample Design carries out with synchronizeing of exchanger chip design.
For achieving the above object, the present invention proposes following technical scheme: a kind of exchanger chip verification method of logic-based chip comprises the following steps:
Step 1, according to the configuration interface information of procotol standard and logic chip, design test case, the configuration information of test case is stored in logic chip;
The configuration information of step 2, chip configuration modular converter read test use-case from logic chip, and this configuration information is converted to the required configuration information of proofing chip;
Step 3, based on emulation platform independently, carry out chip checking.
Preferably, described logic chip comprises configuration interface and scanning fetch interface, and described configuration interface provides the design of configuration interface information for test case, and described scanning fetch interface extracts the configuration information of test case for the chip configuration modular converter.
The configuration information of described test case be stored in logic chip transmit with control register in.
Described test case configuration information comprises: according to the chip functions information of procotol standard configuration and the list item information corresponding with transmitting of logic chip of configuration, the list item information that the logic chip transfer is delivered is corresponding with the list item information of test case configuration.
Described chip configuration modular converter is sent by test case " configuration submits to " after command driven, start the configuration information of the test case in the scanning logic chip.
Described independently emulation platform is respectively: the emulation of higher level lanquage emulation verification platform, RTL verification platform, based on FPGA simulation hardware verification platform.
Described chip configuration modular converter is by driving adapter that the authorization information of emulation platform is transported to respectively to the corresponding driving layer of each platform.
Described driving layer comprises that higher level lanquage model-driven layer, RTL model-driven layer, FPGA hardware platform drive layer, and each drives layer to drive respectively corresponding emulation platform, realizes, with different language, the exchanger chip function is carried out to emulation.
Another object of the present invention also is to provide a kind of exchanger chip demo plant of logic-based chip, comprise use-case design cell, chip configuration converting unit, be arranged on logic chip unit between use-case design cell and chip configuration converting unit and by an emulation platform that drives layer to be connected with the chip configuration converting unit, described logic chip unit is for providing respectively the configuration information of configuration interface information and test case to use-case design cell and chip configuration converting unit; Described use-case design cell is according to the configuration interface information design test case of procotol standard and logic chip unit; Described chip configuration converting unit reads the configuration information of described test case from the logic chip unit, and this configuration information is converted to the required configuration information of checking actual chips; Described emulation platform is for being verified actual chips.
Preferably, described chip configuration converting unit comprises that three independently first drive adaptation unit, second drives adaptation unit and the 3rd to drive adaptation unit, described driving layer comprises higher level lanquage model-driven layer, RTL model-driven layer, the FPGA hardware platform drives layer, described emulation platform comprises: higher level lanquage emulation verification platform, the emulation of RTL verification platform, based on FPGA simulation hardware verification platform, described chip configuration converting unit drives higher level lanquage emulation verification platform to carry out emulation by the first driving adaptation unit and higher level lanquage model-driven layer, described chip configuration converting unit drives emulation the verification platform of RTL to carry out emulation by the second driving adaptation unit and RTL model-driven layer, described chip configuration converting unit drives adaptation unit and FPGA hardware platform to drive layer driving to carry out emulation based on FPGA simulation hardware verification platform by the 3rd.
Compared with prior art, the invention has the beneficial effects as follows: (1) test case is directly designed for logic chip, realizes that the design process of test case carries out with synchronizeing of chip design process, thereby has shortened the whole R&D cycle of chip; (2) the test case of disperseing, focus on the chip configuration modular converter, be convenient to the maintenance of test case; (3) different emulation platforms is used same test case, greatly reduces the workload that test case is safeguarded, saves the input of human resources; (4) test case can be reused, and has saved the cost of chip checking and has improved the efficiency of chip checking.
The accompanying drawing explanation
Fig. 1 is the FB(flow block) schematic diagram of general exchanger chip design verification;
Fig. 2 is the FB(flow block) schematic diagram that the present invention is based on the exchanger chip verification method of logic chip;
Fig. 3 is the structured flowchart schematic diagram that the present invention is based on the exchanger chip demo plant of logic chip;
Embodiment
Below in conjunction with accompanying drawing of the present invention, the technical scheme of the embodiment of the present invention is carried out to clear, complete description.
The present invention has disclosed a kind of exchanger chip verification method of logic-based chip, in the exchanger chip R&D process, chip functions being verified.As shown in Figure 2, test case, according to the configuration interface information of procotol standard and logic chip, completes the configuration of proofing chip function information needed, and the testing procedure of setting chip checking.In the present invention, the design of test case is directly designed for logic chip and procotol standard, while therefore not needing chip design by the time to complete, chip is not carried out to functional verification, can carry out the design of test case in chip design, shorten the whole development cycle of chip.
Logic chip is according to the procotol standard, and the configuration interface by self provides configuration interface information to test case on the one hand, for the design of test case; The configuration information that provides test case by the scanning fetch interface on the other hand is to the chip configuration modular converter, for the conversion of chip configuration information.The configuration information of test case is stored in transmitting of logic chip and control register, and what the test case configuration information comprised configuration transmits corresponding list item information with logic chip.
The test case configuration information disperseed, by the scanning fetch interface of logic chip, is concentrated and is submitted to the chip configuration modular converter, and the chip configuration modular converter comprises the driving aptamer module driven based on three emulation platforms.The chip configuration modular converter is after receiving " configuration is submitted to " instruction that test case sends, scan and extract the configuration information of test case in logic chip, this configuration information is converted to the required configuration information of proofing chip, and, by driving the correspondence that the aptamer module is handed down to three independent emulation platforms to drive layer, drive corresponding emulation platform to be verified designed chip functions.
Drive layer to comprise that higher level lanquage model-driven layer, RTL model-driven layer and FPGA hardware platform drive layer, each drives layer to drive respectively corresponding emulation platform, the emulation of higher level lanquage emulation checking, RTL checking and based on the FPGA simulation hardware and verify that these three emulation platforms are used same test case, greatly reduced the workload that test case is safeguarded, its emulation testing process is similar with general testing process, realizes the checking to chip functions with different language respectively.
The present invention has also disclosed a kind of exchanger chip demo plant of logic-based chip, in the exchanger chip R&D process, chip functions being verified.As shown in Figure 3, comprise use-case design cell, chip configuration converting unit, logic chip unit and emulation platform, described use-case design cell and chip logic unit are according to the procotol standard design, and described chip configuration converting unit is configured the information conversion according to the actual chips design standards.
Upstream, described logic chip unit connects the use-case design cell, and downstream connects chip configuration transitions unit, and the configuration information of configuration interface information and test case is provided to use-case design cell and chip configuration converting unit respectively.Described use-case design cell is according to the configuration interface information design test case of procotol standard and logic chip unit, and test case setting testing procedure and configuration complete the logic chip function information corresponding with actual chips of procotol standard code; Described chip configuration converting unit reads the configuration information of described test case from the logic chip unit, and this configuration information is converted to the required configuration information of checking actual chips.
The chip configuration converting unit comprises that three independently first drive adaptation unit, second drives adaptation unit and the 3rd to drive adaptation unit, described chip configuration converting unit is by driving layer to drive corresponding emulation platform, described driving layer comprises respectively and the first driving adaptation unit, second drives adaptation unit and the 3rd higher level lanquage model-driven layer that drives adaptation unit to be connected, RTL model-driven layer, the FPGA hardware platform drives layer, described emulation platform comprises and the higher level lanquage emulation the verification platform that drive the corresponding connection of layer, the emulation of RTL verification platform, based on FPGA simulation hardware verification platform, on emulation platform, the actual chips function is verified.
The present invention does not limit and uses above-mentioned three emulation platforms to be verified chip functions information, and the adapter of the corresponding emulation platform of exploitation in the chip configuration converting unit, just can use with the corresponding emulation platform of adapter and realize the checking to chip.
Technology contents of the present invention and technical characterictic have disclosed as above; yet those of ordinary skill in the art still may be based on teaching of the present invention and announcements and are done all replacement and modifications that does not deviate from spirit of the present invention; therefore; protection domain of the present invention should be not limited to the content that embodiment discloses; and should comprise various do not deviate from replacement of the present invention and modifications, and contained by the present patent application claim.
Claims (10)
1. the exchanger chip verification method of a logic-based chip is characterized in that comprising the following steps:
Step 1, according to the configuration interface information of procotol standard and logic chip, design test case, the configuration information of test case is stored in logic chip;
The configuration information of step 2, chip configuration modular converter read test use-case from logic chip, and this configuration information is converted to the required configuration information of checking actual chips;
Step 3, based on emulation platform independently, carry out chip checking.
2. the exchanger chip verification method of logic-based chip according to claim 1, it is characterized in that, described logic chip comprises configuration interface and scanning fetch interface, described configuration interface provides the design of configuration interface information for test case, and described scanning fetch interface extracts the configuration information of test case for the chip configuration modular converter.
3. the exchanger chip verification method of logic-based chip according to claim 1, is characterized in that, the configuration information of described test case be stored in logic chip transmit with control register in.
4. the exchanger chip verification method of logic-based chip according to claim 3, it is characterized in that, described test case configuration information comprises: according to the chip functions information of procotol standard configuration and the list item information corresponding with transmitting of logic chip of configuration.
5. the exchanger chip verification method of logic-based chip according to claim 1, it is characterized in that, described chip configuration modular converter is sent by test case " configuration submits to " after command driven, start the configuration information of the test case in the scanning logic chip.
6. the exchanger chip verification method of logic-based chip according to claim 1, it is characterized in that, described independently emulation platform comprises: the emulation of higher level lanquage emulation verification platform, RTL verification platform, based on FPGA simulation hardware verification platform.
7. the exchanger chip verification method of logic-based chip according to claim 6, is characterized in that, described chip configuration modular converter is by driving adaptation module that the authorization information of emulation platform is transported to respectively to the corresponding driving layer of each platform.
8. the exchanger chip verification method of logic-based chip according to claim 7, it is characterized in that, described driving layer comprises that higher level lanquage model-driven layer, RTL model-driven layer, FPGA hardware platform drive layer, and each drives layer to drive respectively corresponding emulation platform.
9. the exchanger chip demo plant of logic-based chip, it is characterized in that comprising use-case design cell, chip configuration converting unit, be arranged on logic chip unit between use-case design cell and chip configuration converting unit and by an emulation platform that drives layer to be connected with the chip configuration converting unit, described logic chip unit provides respectively the configuration information of configuration interface information and test case to use-case design cell and chip configuration converting unit; Described use-case design cell is according to the configuration interface information design test case of procotol standard and logic chip unit; Described chip configuration converting unit reads the configuration information of described test case from the logic chip unit, and this configuration information is converted to the required configuration information of checking actual chips; Described emulation platform is for being verified actual chips.
10. the exchanger chip demo plant of logic-based chip according to claim 9, it is characterized in that, described chip configuration converting unit comprises that three independently first drive adaptation unit, second drives adaptation unit and the 3rd to drive adaptation unit, described driving layer comprises higher level lanquage model-driven layer, RTL model-driven layer, the FPGA hardware platform drives layer, described emulation platform comprises: higher level lanquage emulation verification platform, the emulation of RTL verification platform, based on FPGA simulation hardware verification platform, described chip configuration converting unit drives higher level lanquage emulation verification platform to carry out emulation by the first driving adaptation unit and higher level lanquage model-driven layer, described chip configuration converting unit drives emulation the verification platform of RTL to carry out emulation by the second driving adaptation unit and RTL model-driven layer, described chip configuration converting unit drives adaptation unit and FPGA hardware platform to drive layer driving to carry out emulation based on FPGA simulation hardware verification platform by the 3rd.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013102900965A CN103440195A (en) | 2013-07-11 | 2013-07-11 | Switch chip verification method and device based on logic chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013102900965A CN103440195A (en) | 2013-07-11 | 2013-07-11 | Switch chip verification method and device based on logic chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103440195A true CN103440195A (en) | 2013-12-11 |
Family
ID=49693886
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013102900965A Pending CN103440195A (en) | 2013-07-11 | 2013-07-11 | Switch chip verification method and device based on logic chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103440195A (en) |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104253723A (en) * | 2014-09-29 | 2014-12-31 | 电子科技大学 | Software and hardware collaborative implementation-based switch verification test method and device |
| CN105306265A (en) * | 2015-10-12 | 2016-02-03 | 烽火通信科技股份有限公司 | Data packet tracing method for simulation verification of switch system |
| CN105447251A (en) * | 2015-12-01 | 2016-03-30 | 浪潮(北京)电子信息产业有限公司 | Transaction type excitation based verification method |
| CN106599343A (en) * | 2016-11-01 | 2017-04-26 | 深圳国微技术有限公司 | SOC system verification method and apparatus for improving simulation efficiency |
| CN106940428A (en) * | 2016-01-04 | 2017-07-11 | 中兴通讯股份有限公司 | Chip verification method, apparatus and system |
| CN109446677A (en) * | 2018-11-02 | 2019-03-08 | 南京贝伦思网络科技股份有限公司 | General-purpose platform and its building method based on network chip |
| CN109522212A (en) * | 2018-09-30 | 2019-03-26 | 广西电网有限责任公司电力科学研究院 | A kind of acquisition terminal software reliability safety half detection system in kind |
| CN110120877A (en) * | 2018-02-05 | 2019-08-13 | 大唐移动通信设备有限公司 | A kind of configuration method of the parameter of the configuration circuit and exchange chip of exchange chip |
| CN110413464A (en) * | 2019-07-12 | 2019-11-05 | 杭州迪普科技股份有限公司 | A kind of configuration list item test method, system |
| CN110990112A (en) * | 2019-10-31 | 2020-04-10 | 苏州浪潮智能科技有限公司 | Method and device for realizing interface simulation platform |
| CN111985179A (en) * | 2020-08-26 | 2020-11-24 | 上海磐启微电子有限公司 | Design verification system and method for wireless communication chip |
| CN112597718A (en) * | 2020-12-21 | 2021-04-02 | 海光信息技术股份有限公司 | Verification method, verification device and storage medium for integrated circuit design |
| CN115480914A (en) * | 2022-09-02 | 2022-12-16 | 江苏安超云软件有限公司 | Method and system for realizing multi-tenant service |
| CN117291132A (en) * | 2023-11-27 | 2023-12-26 | 上海小厘科技有限公司 | Chip verification system, method and storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201522707U (en) * | 2009-03-16 | 2010-07-07 | 盛科网络（苏州）有限公司 | Software and hardware cooperated simulation verification system based on FPGA |
| CN102402628A (en) * | 2010-09-07 | 2012-04-04 | 无锡中星微电子有限公司 | Method and system for generating systems-on-a-chip (SoC) verification platform |
| CN102957553A (en) * | 2011-08-25 | 2013-03-06 | 中兴通讯股份有限公司 | Method and device for automatic generation of excitation codes |
-
2013
- 2013-07-11 CN CN2013102900965A patent/CN103440195A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201522707U (en) * | 2009-03-16 | 2010-07-07 | 盛科网络（苏州）有限公司 | Software and hardware cooperated simulation verification system based on FPGA |
| CN102402628A (en) * | 2010-09-07 | 2012-04-04 | 无锡中星微电子有限公司 | Method and system for generating systems-on-a-chip (SoC) verification platform |
| CN102957553A (en) * | 2011-08-25 | 2013-03-06 | 中兴通讯股份有限公司 | Method and device for automatic generation of excitation codes |
Cited By (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104253723A (en) * | 2014-09-29 | 2014-12-31 | 电子科技大学 | Software and hardware collaborative implementation-based switch verification test method and device |
| CN104253723B (en) * | 2014-09-29 | 2017-11-14 | 电子科技大学 | The method and device for the interchanger validation test realized based on software-hardware synergism |
| CN105306265A (en) * | 2015-10-12 | 2016-02-03 | 烽火通信科技股份有限公司 | Data packet tracing method for simulation verification of switch system |
| CN105306265B (en) * | 2015-10-12 | 2019-01-04 | 烽火通信科技股份有限公司 | A kind of data packet method for tracing for switch system simulating, verifying |
| CN105447251A (en) * | 2015-12-01 | 2016-03-30 | 浪潮(北京)电子信息产业有限公司 | Transaction type excitation based verification method |
| CN105447251B (en) * | 2015-12-01 | 2018-12-07 | 浪潮(北京)电子信息产业有限公司 | A kind of verification method based on transaction types excitation |
| CN106940428A (en) * | 2016-01-04 | 2017-07-11 | 中兴通讯股份有限公司 | Chip verification method, apparatus and system |
| CN106940428B (en) * | 2016-01-04 | 2020-11-03 | 中兴通讯股份有限公司 | Chip verification method, device and system |
| CN106599343A (en) * | 2016-11-01 | 2017-04-26 | 深圳国微技术有限公司 | SOC system verification method and apparatus for improving simulation efficiency |
| CN110120877A (en) * | 2018-02-05 | 2019-08-13 | 大唐移动通信设备有限公司 | A kind of configuration method of the parameter of the configuration circuit and exchange chip of exchange chip |
| CN110120877B (en) * | 2018-02-05 | 2020-11-20 | 大唐移动通信设备有限公司 | Configuration circuit of exchange chip and configuration method of parameters of exchange chip |
| CN109522212A (en) * | 2018-09-30 | 2019-03-26 | 广西电网有限责任公司电力科学研究院 | A kind of acquisition terminal software reliability safety half detection system in kind |
| CN109446677A (en) * | 2018-11-02 | 2019-03-08 | 南京贝伦思网络科技股份有限公司 | General-purpose platform and its building method based on network chip |
| CN110413464A (en) * | 2019-07-12 | 2019-11-05 | 杭州迪普科技股份有限公司 | A kind of configuration list item test method, system |
| CN110413464B (en) * | 2019-07-12 | 2023-10-27 | 杭州迪普科技股份有限公司 | Configuration table item testing method and system |
| CN110990112B (en) * | 2019-10-31 | 2022-12-16 | 苏州浪潮智能科技有限公司 | Method and device for realizing interface simulation platform |
| CN110990112A (en) * | 2019-10-31 | 2020-04-10 | 苏州浪潮智能科技有限公司 | Method and device for realizing interface simulation platform |
| CN111985179A (en) * | 2020-08-26 | 2020-11-24 | 上海磐启微电子有限公司 | Design verification system and method for wireless communication chip |
| CN112597718A (en) * | 2020-12-21 | 2021-04-02 | 海光信息技术股份有限公司 | Verification method, verification device and storage medium for integrated circuit design |
| CN112597718B (en) * | 2020-12-21 | 2023-10-03 | 海光信息技术股份有限公司 | Verification method, verification device and storage medium for integrated circuit design |
| CN115480914A (en) * | 2022-09-02 | 2022-12-16 | 江苏安超云软件有限公司 | Method and system for realizing multi-tenant service |
| CN117291132A (en) * | 2023-11-27 | 2023-12-26 | 上海小厘科技有限公司 | Chip verification system, method and storage medium |
| CN117291132B (en) * | 2023-11-27 | 2024-02-20 | 上海小厘科技有限公司 | Chip verification system, method and storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103440195A (en) | Switch chip verification method and device based on logic chip | |
| CN101499937A (en) | Software and hardware collaborative simulation verification system and method based on FPGA | |
| CN104702474B (en) | A kind of EtherCAT master station devices based on FPGA | |
| CN109298648A (en) | A kind of train control center emulation Auto-Test System | |
| CN105808843A (en) | Construction method of mixed signal verification platform | |
| CN114036013B (en) | Multi-module synchronous verification platform and verification method for transponder chip based on UVM | |
| RU2009140981A (en) | METHOD AND DEVICE FOR MAINTENANCE IN AIRCRAFT | |
| CN103376340B (en) | A kind of keyset, multi-platform serial test system and method | |
| CN205301911U (en) | Embedded fault injection control system | |
| CN202383515U (en) | Automatic test platform for train network equipment | |
| CN201522707U (en) | Software and hardware cooperated simulation verification system based on FPGA | |
| CN105450475A (en) | FC switch test device | |
| CN110611312B (en) | On-line simulation system and method for panoramic data of substation bay level | |
| CN204733178U (en) | A kind of EtherCAT master station device based on FPGA | |
| CN104699524A (en) | SOC (system on chip) chip verifying system and method for dynamic simulation of static compilation | |
| CN102495626A (en) | Train network equipment automatic test stand | |
| CN108111265B (en) | Automatic testing method for consistency of communication protocol | |
| CN114089719B (en) | Vehicle signal interface simulation verification method and device for TACS system | |
| CN106849349B (en) | A kind of sun square formation simulator developing Of Remote Control Power frame system | |
| CN102497290A (en) | Data detecting equipment and method for MVB (multifunctional vehicle bus) network | |
| CN101551769B (en) | Agglomeration method and device of configurable firmware | |
| CN117061544A (en) | Verification system, method, device and medium for transformer substation replacement gateway machine | |
| CN102436186B (en) | Performer simulator and satellite closed loop simulation system with performer simulator | |
| CN114785681B (en) | Automatic checking and accepting system and method for monitoring information of transformer substation on-line equipment | |
| CN202195949U (en) | Direct-current converter external characteristic hardware-in-the-loop simulation testing bench |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20131211 |