CN204733178U - A kind of EtherCAT master station device based on FPGA - Google Patents
A kind of EtherCAT master station device based on FPGA Download PDFInfo
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- CN204733178U CN204733178U CN201520139633.0U CN201520139633U CN204733178U CN 204733178 U CN204733178 U CN 204733178U CN 201520139633 U CN201520139633 U CN 201520139633U CN 204733178 U CN204733178 U CN 204733178U
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Abstract
The utility model discloses a kind of EtherCAT master station device based on FPGA, comprise EtherCAT bus interface RJ45, network isolation transformer, PHY chip, FPGA module and PCI/ARM expansion interface.FPGA module receives by expansion connection module the data that CPU sends FPGA module to, and the director data of CPU carries out encapsulating and dispatching by the EtherCAT protocol-driven module of FPGA module inside, and composition dataframe is to PHY chip; PHY chip is converted into differential signal, is sent among EtherCAT network; Each slave station returns main website after processing accordingly after receiving EtherCAT Frame, and after network transformer and PHY chip, data frame receipt module receives the Frame in network; In EtherCAT protocol-driven module, parsing extracted valid data is carried out for CPU to carry out reading state and feedback data to Frame.Device of the present utility model can realize communicating with the CPU with pci interface or ARM interface, has the advantages such as platform compatibility is good, stability is high, efficiency is high, real-time, has important application prospect to industrial automatic control.
Description
Technical field
The utility model belongs to Industrial Ethernet field bus communication field, is specifically related to a kind of EtherCAT master station device based on FPGA.
Background technology
Along with the progress of electronics and the communication technology, industrial automatic control changes the field bus communication control model of Network Basedization into gradually by traditional point-to-point focus control mode.The equipment such as the control of industry spot, monitoring are integrated in a communication network by the mode of serial signal by field bus control system, have the advantages such as digital, two-way and serial multinode.Field bus communication system based on Industrial Ethernet can realize the high speed of 100 m ethernet, the control of low jitter, in the middle of the kinetic control system being widely used in various high-speed, high precision.
EtherCAT is a kind of fieldbus communication protocol based on Industrial Ethernet, because of its advantage such as applicability, refresh cycle short and net synchronization capability is good widely, has been widely recognized in all kinds of control system and applies.
Patent documentation CN201310344639.7 discloses the master/slave station control system of a kind of EtherCAT based on Linux and method, its EtherCAT main website adopts the Intel X86 hardware platform with network interface card, for relevant control instruction is sent to EtherCAT master station module, after being then encoded to EtherCAT message, send by Ethernet interface the control algorithm task realizing digital control system.
Patent documentation 201310542835.5 discloses a kind of supervisory control system based on EtherCAT network, it adopts PC as main website, a network is composed in series, for realizing in remote situation the monitoring of looked environment and the remote control operation of actuator with multiple slave station.
Patent documentation 201310385168.4 discloses a kind of information intelligent terminal system of EtherCAT fieldbus, comprises EtherCAT main website and the information intelligent terminal with EtherCAT bus interface, directly can gather, transmits and monitor Workshop Production information.
The implementation major part of existing EtherCAT main website adopts Bei Fu company under Windows operating system based on the solution of PC, certainly also has the embedded solution based on (SuSE) Linux OS and Android operation system.Its hardware plan overwhelming majority adopts processor CPU to extend out the general system framework of the chip of network interface card, and CPU is used for processing respectively data link layer and the application layer of EtherCAT agreement.But existing this EtherCAT main website implementation utilizes CPU and network interface card to coordinate to come the transmitting-receiving operation of process frames of data, reduce the stability of Frame transmitting-receiving, the operator scheme of network interface card list buffer memory also reduces the efficiency of data transmit-receive simultaneously, causes the stability problem and efficiency that are applied to industrial environment; Secondly, the EtherCAT main website of this main website scheme can not compatible various operating system widely, and it is comparatively large to transplant difficulty, causes the compatibility issue of platform resource; Finally, for the control system that requirement of real-time is strict, utilize software interrupt to guarantee can not meet industrial requirements in real time, cause the loss of real-time, be unfavorable for high-precision real-time control system.
Utility model content
For above defect or the Improvement requirement of prior art, the utility model object is to propose a kind of EtherCAT main website implement device based on FPGA, it is by utilizing FPGA parallel processing and hardware implementing characteristic, based on hardware implementing EtherCAT agreement, achieve the EtherCAT protocol processes of high efficiency and high stability, the communicator simultaneously realized based on FPGA is also integrated with pci interface and ARM interface respectively, can compatible different operating system platform easily.
For achieving the above object, the concrete technical scheme of the utility model employing is as follows:
A kind of EtherCAT master station implementation method based on FPGA and device, its data link layer by the ardware feature and parallel behavior process EtherCAT agreement that utilize FPGA and application layer, thus realize the communication function of integrated EtherCAT on FPGA, and access the integrated function with EtherCAT Industrial Ethernet field bus communication interface in different types of CPU operating system neatly, it is characterized in that
This device comprises PCI/ARM expansion interface, FPGA module, PHY chip, network isolation transformer and EtherCAT bus interface RJ45, wherein,
Described FPGA module is connected with described expansion connection module and PHY chip respectively, it receives by described expansion connection module the data that CPU sends FPGA module to, and by the EtherCAT protocol-driven module of its inside, the director data of CPU is carried out encapsulating and dispatching according to EtherCAT agreement, composition EtherCAT Frame sends to PHY chip by dataframe module in FPGA module; Described PHY chip is connected with network isolation transformer, network isolation transformer is connected with corresponding slave station by EtherCAT bus interface RJ45, described PHY chip is used for the EtherCAT Frame received to be converted to differential signal, and by sending it among EtherCAT network after network isolation transformer, and described EtherCAT bus interface RJ45 is utilized to input each slave station; Each slave station returns main website after processing accordingly after receiving EtherCAT Frame, after network isolation transformer and PHY chip, enter into FPGA module, in this FPGA module, Frame is resolved, and carries out reading state and feedback data for CPU.
As improvement of the present utility model, described FPGA module comprises cpu i/f and selects operational module, CPU application program operation-interface, EtherCAT protocol-driven module, Frame transmitting-receiving operation-interface, Frame transmitting-receiving and checking computations module and PHY chip transceiving data interface; Wherein, described cpu i/f selects operational module to be connected with CPU, provides exchange channels for CPU operates CPU application program operation-interface; Described CPU application program operation-interface can carry out read and write access for CPU and EtherCAT protocol-driven module simultaneously, as the operation-interface of CPU and described FPGA module interactive information; Described EtherCAT protocol-driven module is EtherCAT application program process core, for responding instruction and the valid data of CPU application program operation-interface, complete corresponding director data is dispatched according to EtherCAT standard agreement, framing conciliates the process of frame, realizes the data interaction function of Frame and CPU application program operation-interface; Described Frame transmitting-receiving operation-interface, for receiving the Framed Data frame from EtherCAT protocol-driven module, also can receive the Frame received from network from Frame transmitting-receiving and checking computations module simultaneously; The transmission buffering area valid data that Frame is received and dispatched in operation-interface by described Frame transmitting-receiving and checking computations module send successively according to network communication protocol, and calculate the CRC32 checking computations value of these frame data simultaneously, receiving data frames calculates CRC32 checking computations value while writing Frame transmitting-receiving operation-interface at the same time, and compares the validity of decision data frame with postamble CRC32; Described PHY chip transceiving data interface and PHY chip carry out data interaction, and what complete between data flow is mutual.
As improvement of the present utility model, described application program operation-interface comprises control command data buffer area, state feedback data buffer area and process data buffer area, wherein, described control command data buffer area is the instruction configuration data that CPU writes toward application programming interfaces, comprises control data and interruption arranges instruction; Described state feedback data buffer area is the data buffer area that CPU reads application programming interfaces state, what status data buffer area reflected is that EtherCAT network writes the coomand mode response condition of instruction to CPU, comprise the feedback of state machine information, diagnosis of program information and mailbox communication order, described state feedback data buffer area also comprises the feedback of the bus states such as number of dropped packets feedback, instruction errors feedback and diagnostic message feedback simultaneously; Described process data buffer area comprises real-time command data and the real-time feedback data of each slave station, and the interrupt cycle that the update cycle of its buffer area is set by CPU is determined.
As improvement of the present utility model, described control data is for completing the operation-interface of acyclic state machine switches order and mailbox communication service command, and described interruption arranges instruction and can complete CPU and carry out setting and enable control to the interruption in described FPGA module 2.
As improvement of the present utility model, described Frame transmitting-receiving operation-interface comprises the data frame buffer memory district that configuration data frame sends buffer area, data frame receipt feeds back buffer area and transmitting-receiving, wherein, configuration data frame sends buffer area and comprises and send buffering area enable control register, first and send buffering area and send length and arrange register, second and send buffering area 2 and send that length arranges register, the timed sending cycle arranges register, first page buffering area sending times arranges register and hardware interrupts control register; Described data frame receipt feedback buffer area comprises and receives valid data frame and upgrade the Frame number register, CRC32 effective marker bit register, low 16 bit registers, low 16 bit status registers calculated in the CRC32 of gained in CRC32 in Frame that receive in register, one-period; The data frame buffer memory district of described transmitting-receiving comprises the first transmission buffer area, the second transmission buffer area, first receives buffer area and second and receives buffer area, and corresponding periodicity sends buffer area respectively, aperiodicity transmission buffer area, periodic receipt buffer area and aperiodicity receive buffer area for it.
As improvement of the present utility model, described EtherCAT protocol-driven module comprises feedback data frame processing module, periodically command process module, application command respond module, application command processing module, generate Frame command module and control transceiving data frame register log-on data frame sending module, wherein, described feedback data frame processing module receives CPU and configures interrupt cycle that FPGA produces after signal, first the process of a upper cycle return period feedback data is carried out, then aperiodicity Frame has been judged whether according to the frame number received of receiving register, if had, process corresponding aperiodicity feedback data, when described feedback data frame processing module process feedback data pass to application program operation-interface time, utilize the characteristic of FPGA parallel processing to trigger described periodicity command process module and described application command respond module simultaneously, described periodicity command process module takes out valid data and according to EtherCAT frame standard production cycle process data frame from the described process data buffer area described application program operation-interface, simultaneously described application command respond module from the data cached middle inspection application program operation-interface with or without command operating, if had, carry out the triggering process of respond module, and then form the aperiodicity Frame in this cycle, as do not sent periodic data frame in nothing then this cycle, after described creation data frame ordering module receives the Frame of band transmission, trigger described control transceiving data frame interface register log-on data frame and send, director data frame is sent.
As improvement of the present utility model, described Frame transceiver checking computations module comprises terminal pulse and produces sequence, delivery time pulses generation sequence, send data flow control module, dataframe and hardware CRC32 computing module, receiving data stream control module and data frame receipt and hardware CRC32 check module, wherein, described interruption pulse produces sequence and arranges the cycle according to interruption and interrupt that enable control produces interrupt signal when waiting, described delivery time pulses generation sequence produces dataframe time-ofday signals according to interrupt signal during the grade produced, described transmission data flow control module is according to dataframe time-ofday signals and send configuration register, inside transmission buffer area, read corresponding data send to described dataframe and hardware CRC32 computing module, Frame is converted to data flow and also calculates CRC32 transmission to PHY chip simultaneously by described dataframe and hardware CRC32 computing module, described data frame receipt and hardware CRC32 check the data flow of module reception from PHY chip, calculate CRC32 simultaneously, and compare with postamble CRC32 value the validity verified and receive Frame, after described receiving data stream control module receives Frame, Frame is inserted and receive in buffer area, write the register of corresponding state simultaneously.
In the utility model, CPU makes hardware timing produce interruption by PCI/ARM interface to the setting that FPGA module carries out messaging parameter at initial phase, when interrupting producing to CPU, CPU writes corresponding control command and data according to the scheduling of self control task to the application programming interfaces in FPGA module.The instruction of EtherCAT protocol-driven module continuous scan round application program controlling, when writing the instruction and data of CPU in application program operation-interface, EtherCAT protocol-driven module starts to carry out different operations according to corresponding instruction, and its effect can complete the process of the state machine maintenance of EtherCAT agreement, parameter configuration, mailbox data process aperiodic and periodic process data.For periodic process data, the process data in application program operation-interface can be carried out framing in each interrupt cycle by EtherCAT protocol-driven module, and the timed periodic completing Frame sends; For state machine maintenance, parameter configuration and aperiodicity data, EtherCAT protocol-driven module detected in each interrupt cycle these type of data of s.m.p, if CPU is written with corresponding instruction, then carry out operating corresponding instruction, according to EtherCAT consensus standard composition standard Frame aperiodic, within an interrupt cycle, after periodic data frame, carry out transmission Frame aperiodic, if without these type of data, then do not carry out the transmission of data aperiodic.
In EtherCAT protocol-driven module to periodic data with after having the aperiodicity data of needs transmission to carry out framing, Frame is write Frame transmitting-receiving operation-interface and the configuration parameter of the Frame of write transmission simultaneously.When Frame transmitting-receiving and checking computations module receive the Frame of Frame transmitting-receiving operation-interface and send configuration, start and send, data frame data is received definition according to PHY chip and sends to PHY chip transceiving data interface successively in order, and utilize the characteristic of FPGA parallel work-flow to calculate the CRC32 verification of current data frame simultaneously simultaneously, PHY chip is converted to differential signal after receiving the signal of FPGA module transmission, the signal in EtherCAT network is become after network isolation transformer, by EtherCAT bus interface in access EtherCAT network, realize the communication interaction function with each slave station.
Within an interrupt cycle, timed sending one frame period property Frame, then can send another frame aperiodicity Frame if needed, according to the protocol operation that EtherCAT slave station " flies to read to fly to write ", can judge according to the scheduling strategy of main website periodicity and aperiodicity data simultaneously, the first frame that EtherCAT main website returns is periodic data frame, if there is the second frame, is aperiodicity Frame.EtherCAT bus interface receives data in network after network isolation transformer and PHY chip, be converted to data flow to PHY chip transceiving data interface, Frame transmitting-receiving and checking computations module utilize FPGA parallel work-flow characteristic, the Frame received is received and dispatched operation-interface stored in Frame successively, the CRC32 simultaneously calculating these frame data verifies and provides the result of calculation indicator register of response, if identical with the data postamble CRC32 received, then illustrate effectively; Otherwise then there is the situation of packet loss in this frame.
When the next interrupt cycle of hardware interrupts arrives, first EtherCAT protocol-driven module can detect the Frame that the last cycle returns, check its CRC32, check its with or without in Frame with or without correctly responding and extract corresponding valid data to CPU application program operation-interface, when CPU receives previous frame data feedback, fully can recognize the state of EtherCAT network, and then again bus is controlled according to the demand of the corresponding control task of CPU, thus back and forth complete the mutual of data and controlling functions successively.
Also comprise cpu i/f in FPGA module simultaneously and select operational module, inside can integrated conventional pci interface and ARM interface, all the other kind of interface can as required again FPGA inside expand.User can expand different types of cpu i/f as required and select module, thus can extend out the mode of FPGA to realize EtherCAT master station communication device easily on the basis not changing original platform.
In general, the above technical scheme conceived by the utility model compared with prior art, has following beneficial effect:
(1) the utility model utilizes the data link layer of the ardware feature process EtherCAT agreement of FPGA, improves stability and the fast-response of data link communication;
(2) the utility model utilizes the parallel work-flow characteristic of FPGA can multiple pipeline deal with data, improves the efficiency of protocol processes;
(3) FPGA module of the present utility model is integrated with different types of cpu i/f, can be applicable to different operating system platforms, improves the compatibility of EtherCAT master station communication device;
(4) the utility model utilizes FPGA to produce hardware interrupts, improves the real-time of master station communication control device.
Accompanying drawing explanation
Fig. 1 is the general structure schematic diagram of the device according to the utility model embodiment;
Fig. 2 is the structural representation of FPGA module inside in the device according to the utility model embodiment;
Fig. 3 is application program operation-interface schematic diagram in the device according to the utility model embodiment;
Fig. 4 is the Frame transmitting-receiving operation-interface schematic diagram according to the utility model embodiment;
Fig. 5 performs schematic flow sheet according to the EtherCAT protocol-driven module of the utility model embodiment;
Fig. 6 is periodic data according to the utility model embodiment and aperiodicity data dispatch strategy schematic diagram;
Fig. 7 is that in the method according to the utility model embodiment, Frame transceiver checking computations module performs schematic flow sheet;
Fig. 8 is according to the master station communication device in the device of the utility model embodiment.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the utility model, and be not used in restriction the utility model.
The utility model embodiment proposes a kind of EtherCAT master station implementation method based on FPGA and device, on the basis making full use of FPGA ardware feature and parallel work-flow characteristic, achieve the function that can facilitate integrated EtherCAT Industrial Ethernet fieldbus master station communication device at different operating system, different hardware platforms.
Fig. 1 is the general structure schematic diagram of the utility model embodiment, and this device comprises PCI/ARM interface 1, FPGA module 2, PHY chip 3, network isolation transformer 4 and EtherCAT bus RJ45 interface 5.Wherein, described PCI/ARM interface 1 can carry out selecting corresponding interface module according to the kind of connect CPU, compatible interface comprise pci interface and ARM extends out bus interface, user also can increase corresponding interface module according on the basis self needing or else to change other modules.Described FPGA module 2 is used for processing application layer and the data link layer of EtherCAT agreement; Described PHY chip 3 is used for changing accordingly the differential signal in EtherCAT network and plate level signal; Described network isolation transformer 4 to be used on isolation network signal to the impact of plate level signal; Described EtherCAT bus RJ45 interface 5 is used for realizing communicator to access in EtherCAT network, and one of them RJ45 interface is EtherCAT bus interface, and another interface is optional EtherCAT bus interface.
Fig. 2 is the structural representation of the FPGA module inside in the utility model embodiment device, and this inside modules comprises cpu i/f and selects operational module 21, CPU application program operation-interface 22, EtherCAT protocol-driven module 23, Frame transmitting-receiving operation-interface 24, Frame transmitting-receiving and checking computations module 25 and PHY chip transceiving data interface (26).Wherein, described cpu i/f selects operational module 21 to be connected with CPU, provides exchange channels at a high speed for CPU operates CPU application program operation-interface 22; Described CPU application program operation-interface (22) can carry out read and write access for CPU and EtherCAT protocol-driven module 23 simultaneously, as the operation-interface of CPU and described FPGA module 2 interactive information; Described EtherCAT protocol-driven module 23 is EtherCAT application program process core, its effect is instruction and the valid data of response CPU application program operation-interface 22, complete corresponding director data is dispatched according to EtherCAT standard agreement, framing conciliates the process of frame, realizes the data interaction function of Frame and CPU application program operation-interface 22; Described Frame transmitting-receiving operation-interface 24 can receive the Framed Data frame from EtherCAT protocol-driven module 23, also can receive the Frame received from network from Frame transmitting-receiving and checking computations module 25 simultaneously; The transmission buffering area valid data that Frame is received and dispatched in operation-interface 24 by described Frame transmitting-receiving and checking computations module 25 send successively according to network communication protocol, and calculate the CRC32 checking computations value of these frame data simultaneously, receiving data frames calculates CRC32 checking computations value while writing Frame transmitting-receiving operation-interface 24 at the same time, and compares the validity of decision data frame with postamble CRC32; Described PHY chip transceiving data interface 26 and PHY chip 3 carry out data interaction, and what complete between data flow is mutual.
Fig. 3 is the application program operation-interface schematic diagram of the utility model embodiment, and this interface comprises three parts, is respectively control command data buffer area 221, state feedback data buffer area 222 and process data buffer area 223.Wherein, described control command data buffer area 221 is instruction configuration datas that CPU writes toward application programming interfaces, comprise control data and interruption arranges instruction, control data can complete the non real-time nature functions such as the operation-interface of acyclic state machine switches order and mailbox communication service command, interrupts arranging instruction and can complete CPU to the interruption in described FPGA module 2 and carry out setting and enable control; Described state feedback data buffer area 222 is data buffer area that CPU reads application programming interfaces state, what status data buffer area reflected is that EtherCAT network writes the coomand mode response condition of instruction to CPU, comprise the feedback of state machine information, diagnosis of program information and mailbox communication order, described state feedback data buffer area 222 also comprises the feedback of the bus states such as number of dropped packets feedback, instruction errors feedback and diagnostic message feedback simultaneously; Described process data buffer area 223 comprises real-time command data and the real-time feedback data of each slave station, and the interrupt cycle that the update cycle of its buffer area is set by CPU is determined.
Fig. 4 is the Frame transmitting-receiving operation-interface schematic diagram of the utility model embodiment, and this interface comprises three parts, is respectively the data frame buffer memory district 243 that configuration data frame sends buffer area 241, data frame receipt feedback buffer area 242 and receives and dispatches.Wherein, described configuration data frame transmission buffer area 241 comprises the transmission enable control in buffering area, transmission buffering area 1 sends length setting, send buffering area 2 sends the control registers such as length setting, the setting of timed sending cycle, the setting of buffering area 1 sending times and hardware interrupts control; Described data frame receipt feedback buffer area 242 comprise receive that valid data frame upgrades, the data frame number that receives in one-period, CRC32 effective marker position, the status register such as low 16, low 16 of calculating in the CRC32 of gained in CRC32 in Frame; The data frame buffer memory district 243 of described transmitting-receiving comprises transmission buffer area 1, transmission buffer area 2, receives buffer area 1 and receive buffer area 2, and corresponding periodicity sends buffer area respectively, aperiodicity transmission buffer area, periodic receipt buffer area and aperiodicity receive buffer area for it.
Fig. 5 is that the EtherCAT protocol-driven module of the utility model embodiment performs schematic flow sheet, comprising feedback data frame processing module 231, periodically command process module 232, application command respond module 233, application command processing module 234, generates Frame command module 235 and controls transceiving data frame register log-on data frame sending module 236.Described feedback data frame processing module 231 receives CPU and configures interrupt cycle that FPGA produces after signal, first the process of a upper cycle return period feedback data is carried out, then aperiodicity Frame has been judged whether according to the frame number received of receiving register, if had, process corresponding aperiodicity feedback data, if without, carry out the operation of next module, when described feedback data frame processing module 231 process feedback data pass to application program operation-interface 22 time, utilize the characteristic of FPGA parallel processing to trigger described periodicity command process module 232 and described application command respond module 233 simultaneously, described periodicity command process module 232 takes out valid data and according to EtherCAT frame standard production cycle process data frame from the described process data buffer area 223 described application program operation-interface 22, simultaneously described application command respond module 233 from the data cached middle inspection application program operation-interface 22 with or without command operating, if had, carry out the triggering process of respond module, and then form the aperiodicity Frame in this cycle, as do not sent periodic data frame in nothing then this cycle, after described creation data frame ordering module 235 receives the Frame of band transmission, trigger described control transceiving data frame interface register log-on data frame and send 236, director data frame is sent.
Fig. 6 is periodic data and the aperiodicity data dispatch strategy schematic diagram of the utility model embodiment.Interruption pulse when utilizing the ardware feature of FPGA can produce very strict grade, when interrupt signal produces, described FPGA module 2 can produce periodic data respectively, as as described in application program operation-interface 22 have cpu instruction, then produce data aperiodic in addition, and insert described Frame transmitting-receiving operation-interface 24, under the configuration delivery time of configuration register, then within the same cycle, sending periodic data frame and aperiodicity Frame respectively as there is aperiodicity Frame, then only sending aperiodicity Frame if do not existed.
Fig. 7 is that the Frame transceiver checking computations module of the utility model embodiment performs schematic flow sheet, comprises terminal pulse and produces sequence 251, delivery time pulses generation sequence 252, sends data flow control module 253, dataframe and hardware CRC32 computing module 254, receiving data stream control module 255 and data frame receipt and hardware CRC32 checking computations module 256.Wherein, described interruption pulse produces sequence 251 and arranges the cycle according to interruption and interrupt that enable control produces interrupt signal when waiting, described delivery time pulses generation sequence 252 produces dataframe time-ofday signals according to interrupt signal during the grade produced, described transmission data flow control module 253 is according to dataframe time-ofday signals and send configuration register, inside transmission buffer area, read corresponding data send to described dataframe and hardware CRC32 computing module 254, Frame is converted to data flow and also calculates CRC32 transmission to PHY chip simultaneously by described dataframe and hardware CRC32 computing module 254.Described data frame receipt and hardware CRC32 checking computations module 256 receive the data flow from PHY chip, calculate CRC32 simultaneously, and compare with postamble CRC32 value the validity verified and receive Frame, after described receiving data stream control module 255 receives Frame, Frame is inserted and receive in buffer area, write the register of corresponding state simultaneously.
Fig. 8 is the master station communication device of the utility model embodiment.Described FPGA module 2 is connected with jtag interface 27, for the debugging to FPGA; Described FPGA module 2 is connected by ARM expansion interface 1 with the arm processor 0 in embodiment, and PCI/ARM expansion interface 1 described in the utility model embodiment is ARM expansion bus GPMC agreement.Described arm processor 0 is connected with SD card 01, be connected with described Ethernet Ethernet interface 02 by PHY chip 03, be connected with USB interface 04, be connected with RS232 interface 05 by RS232 driving chip 06, be connected with USB interface 08 by VGA driving chip 07, form the peripheral interface of arm processor.Processor A RM processor 0 in the utility model embodiment is connected with FPGA module 2 by PCI/ARM expansion interface 1, easily and flexibly at the field-bus interface of the peripheral integrated EtherCAT Industrial Ethernet of arm processor 0, and the performance of EtherCAT protocol realization can be guaranteed by the characteristic of FPGA simultaneously.
Those skilled in the art will readily understand; the foregoing is only preferred embodiment of the present utility model; not in order to limit the utility model; all do within spirit of the present utility model and principle any amendment, equivalent to replace and improvement etc., all should be included within protection range of the present utility model.
Claims (1)
1. the EtherCAT master station device based on FPGA, it is characterized in that, this device comprises PCI/ARM expansion interface (1), FPGA module (2), PHY chip (3), network isolation transformer (4) and EtherCAT bus interface RJ45 (5), wherein
Described FPGA module (2) is connected with described PCI/ARM expansion connection module (1) and PHY chip (3) respectively, it receives by described PCI/ARM expansion connection module (1) data that CPU sends FPGA module to, and by the EtherCAT protocol-driven module of its inside, the director data of CPU is carried out encapsulating and dispatching according to EtherCAT agreement, composition EtherCAT Frame sends to PHY chip (3) by dataframe module in FPGA module; Described PHY chip (3) is connected with network isolation transformer (4), network isolation transformer (4) is connected with corresponding slave station by EtherCAT bus interface RJ45 (5), described PHY chip (3) is for being converted to differential signal by the EtherCAT received Frame, and send it among EtherCAT network by after network isolation transformer (4), and described EtherCAT bus interface RJ45 (5) is utilized to input each slave station; Each slave station returns main website after processing accordingly after receiving EtherCAT Frame, after network isolation transformer (4) and PHY chip (3), enter into FPGA module (2), in this FPGA module (2), Frame is resolved, and carries out reading state and feedback data for CPU.
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| CN107389972A (en) * | 2017-07-18 | 2017-11-24 | 北京华电天仁电力控制技术有限公司 | A kind of analyzer for boiler tubing wind powder flow parameter on-line measurement |
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| CN110109849A (en) * | 2019-04-30 | 2019-08-09 | 湖北三江航天万峰科技发展有限公司 | A kind of CAN device driving device and method based on pci bus |
| CN111158285A (en) * | 2019-12-30 | 2020-05-15 | 上海铼钠克数控科技股份有限公司 | Control system based on EtherCAT bus |
| CN111327502A (en) * | 2020-03-03 | 2020-06-23 | 南京岸鸣智能科技有限公司 | Communication method based on pulse extension protocol |
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2015
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107389972A (en) * | 2017-07-18 | 2017-11-24 | 北京华电天仁电力控制技术有限公司 | A kind of analyzer for boiler tubing wind powder flow parameter on-line measurement |
| CN107389972B (en) * | 2017-07-18 | 2020-05-22 | 北京华电天仁电力控制技术有限公司 | Analyzer for on-line measuring boiler pipeline air-powder flow parameter |
| CN109902049A (en) * | 2019-04-26 | 2019-06-18 | 广东阿达智能装备有限公司 | PCI expanding unit |
| CN110109849A (en) * | 2019-04-30 | 2019-08-09 | 湖北三江航天万峰科技发展有限公司 | A kind of CAN device driving device and method based on pci bus |
| CN111158285A (en) * | 2019-12-30 | 2020-05-15 | 上海铼钠克数控科技股份有限公司 | Control system based on EtherCAT bus |
| CN111327502A (en) * | 2020-03-03 | 2020-06-23 | 南京岸鸣智能科技有限公司 | Communication method based on pulse extension protocol |
| CN111327502B (en) * | 2020-03-03 | 2021-12-14 | 南京岸鸣智能科技有限公司 | Communication method based on pulse extension protocol |
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