CN105450475A - FC switch test device - Google Patents
FC switch test device Download PDFInfo
- Publication number
- CN105450475A CN105450475A CN201510889503.3A CN201510889503A CN105450475A CN 105450475 A CN105450475 A CN 105450475A CN 201510889503 A CN201510889503 A CN 201510889503A CN 105450475 A CN105450475 A CN 105450475A
- Authority
- CN
- China
- Prior art keywords
- module
- frame
- test
- control machine
- state
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/50—Testing arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Small-Scale Networks (AREA)
Abstract
The invention discloses a FC switch test device, and belongs to the computer communication technology. The FC switch test device disclosed by the invention is composed of a hardware circuit, test logic and test software, the hardware circuit is mainly composed of an FPGA, a PPC processor, a photoelectric conversion circuit, a power supply, a clock, a reset, the Ethernet and a serial port, the test logic is realized based on the FPGA and is mainly composed of an FC MAC module, an excitation source module, a sending buffer module, a receiving buffer module, a sending and receiving control module and a monitoring processing module, the FC switch test device disclosed by the invention supports unicast, multicast, broadcast, monitoring, timing and other function tests, and has the advantages of small volume, low power consumption, convenience for carrying and capability of automatically storing a test result, etc.
Description
Technical field
The invention belongs to computer communication technology, relate to a kind of implementation method of FC switch test equipment.
Background technology
FC communication network is made up of Node station and switch, and all Node station are all connected with switch by link, realize distributed communication.
At present, commercial FC switch test equipment generally controls complexity, and power consumption is comparatively large, and volume is comparatively large, is not easy to outfield and carries and environmental test use; Secondly, commercial FC switch test equipment, when testing, only verifies CRC and the EOF polarity etc. of Frame, does not compare to data frame content, have certain limitation; In addition, commercial FC switch is staggered the time testing out, and automatically cannot stop test, automatically cannot preserve test result; Commercial FC switch cannot judge the correctness of FC switch monitoring automatically, and need people for judging, efficiency is lower.
Summary of the invention
The invention provides a kind of FC switch test equipment, support clean culture, multicast, broadcast, monitoring, time the functional test such as system, and have volume little, low in energy consumption, be easy to carry, the advantage such as preservation test result automatically.
Technical solution of the present invention is,
A kind of FC switch test equipment, its special character is:
Comprise hardware circuit and test logic;
Hardware circuit comprises FPGA, and test logic operates on FPGA;
Test logic is primarily of the composition such as FCMAC module, driving source module, transmission buffer module, reception buffer module, transmission and reception control module, monitor processing module;
FCMAC module, encapsulates Frame to be sent, resolves the Frame received;
Transmission and reception control module comprises transmission control module, sends state of a control machine and receive control module, sends state of a control machine and sends control module transmission data for controlling;
Driving source module is made up of parameter configuration logic, Payload formation logic, framing logic, state of a control machine, CRC calculating and EOF polarity computational logic;
Send control module for start CRC calculate and EOF polarity computational logic by dataframe to sending buffer module;
Payload formation logic is used for producing pseudo-random data, incremental data or fixed data, and sends to framing logic; Framing logic carries out corresponding filling according to the pseudo-random data received, incremental data or fixed data SOF, head, Payload, CRC or EOF field to Frame to be sent;
State of a control machine is used for SOF, head field contents of controling parameters configuration logic to Frame to be sent and is configured, and for controlling the filling of framing logic to Frame to be sent, and is calculated and EOF polarity computational logic to CRC by the dataframe of filling;
CRC calculates and EOF polarity computational logic calculates the crc value of the Frame received and EOF polarity, crc field and the EOF field of result of calculation being inserted Frame to be sent upgrade the Frame received, and by the dataframe upgraded to sending buffer module;
Send the Frame that buffer module receives for buffer memory, and give reception control module and FCMAC module by the dataframe of buffer memory;
Receive the Frame that buffer module is used for the reception of buffer memory FCMAC module, and by the dataframe of buffer memory to receiving control module;
Receive control module to from sending the Frame of buffer module and comparing from receiving the Frame of buffer module, compare whether they consistent;
Whether monitor processing module is correct for monitoring tested FC switch data that each policing port sends.
The transmission buffering area sending buffer module adopts dual port RAM to realize, and be divided into side a and b, side a and b is separate.
Above-mentioned transmission buffer module carries out buffer memory to the Frame received in the following manner:
Send buffer module and write enable and write address according to the Frame generation received, by A end, Frame is written in dual port RAM.
Send control module also for sending read command to transmission buffer module;
Send buffer module be in the following manner by the dataframe of buffer memory to receiving control module:
After transmission buffer module receives the read command sending control module, hold sense data from the B of dual port RAM and send the data to reception control module.
Send control module also for starting transmission buffer module;
Sending buffer module is in the following manner by the dataframe of buffer memory to FCMAC module:
When sending buffer module after receiving the starting command sending control module, producing and reading enable and read address, holding sense data frame and by dataframe to FCMAC module from the A of dual port RAM.
The reception buffer zone receiving buffer module adopts dual port RAM to realize, and be divided into side a and b, side a and b is separate, and wherein B end is used for for CPU access.
Above-mentioned reception buffer module carries out buffer memory to the Frame received in the following manner:
After reception buffer module receives the Frame of FCMAC module transmission, produce and write enable and write address accordingly, Frame is written in dual port RAM by A end.
Above-mentioned reception control module is used for sending read command to reception buffer module;
Receive buffer module be in the following manner by the dataframe of buffer memory to receiving control module:
When receiving buffer module after receiving the read command receiving control module, producing and reading enable and read address accordingly, holding sense data frame and by dataframe to receiving control module from the A of dual port RAM.
The redirect flow process of above-mentioned transmission state of a control machine is as follows:
1) time initially, send state of a control machine and be in dummy status, host configuration singlecast router testing time, clean culture competition testing time, multicast testing time and on-air testing number of times;
2) under dummy status, if test enable signals detected, send state of a control machine and then jump to configuration status; Otherwise, send state of a control machine and rest on dummy status;
3) under configuration status, if tested, sent state of a control machine and jumped to dummy status; Otherwise, send state of a control machine and jump to singlecast router test mode;
4) under singlecast router test mode, if test stops, then send state of a control machine and jump to dummy status; If singlecast router testing time be 0 or singlecast router tested, send state of a control machine and jump to clean culture competition test mode; Otherwise, send state of a control machine and rest on singlecast router test mode;
5) under clean culture competition test mode, if test stops, then send state of a control machine and jump to dummy status; Otherwise, if clean culture competition testing time be 0 or clean culture competition test complete, send state of a control machine and jump to multicast test mode; Otherwise, send state of a control machine and rest on clean culture competition test mode;
6) under multicast test mode, if test stops, then send state of a control machine and jump to dummy status; Otherwise, if multicast testing time be 0 or multicast tested, send state of a control machine and jump to on-air testing state; Otherwise, send state of a control machine and rest on multicast test mode;
7) under on-air testing state, if test stops, then send state of a control machine and jump to dummy status; Otherwise, if on-air testing number of times be 0 or on-air testing complete, send state of a control machine and jump to configuration status; Otherwise, send state of a control machine and rest on on-air testing state.
The monitoring mode of the policing port of tested FC switch is input monitoring pattern, output monitoring pattern and message monitoring pattern;
Monitor processing module is whether monitor tested FC switch Frame that each policing port sends in the following manner correct:
Under input monitoring pattern or message monitoring pattern, after policing port receives Frame, extract the SID of this frame, then according to the transmission buffering area transmission read request of SID to corresponding ports, the Frame that the Frame read back and policing port receive is compared, if made a mistake, then stop test, reporting interruption; Otherwise test proceeds;
Under output monitoring pattern, after policing port receives Frame, extract the DID of this frame, then according to the reception buffer zone transmission read request of DID to corresponding ports, the Frame that the Frame read back and policing port receive is compared, if made a mistake, then stop test, reporting interruption, otherwise test proceeds.
The advantage that the present invention has is:
Adopt veneer FPGA exploitation, volume be little, low in energy consumption, be easy to carry, loadings can be configured, automatically report mistake, automatically preserve test result, can carry out the communication function tests such as clean culture, multicast, broadcast, control and measuring, time unified test try.
Accompanying drawing explanation
Fig. 1 is embedded-type software architecture schematic diagram;
Fig. 2 is test logic overall architecture schematic diagram;
Fig. 3 is FCMAC module diagram;
Fig. 4 is driving source module diagram;
Fig. 5 sends state of a control machine schematic diagram.
Embodiment
FC switch test equipment of the present invention primarily of hardware circuit, testing software and test logic three part composition.
Hardware circuit is primarily of compositions such as FPGA, PPC processor, photoelectric conversion circuit, power supply, clock, reset, Ethernet, serial ports.
Test logic realizes based on FPGA, primarily of FCMAC module, driving source module, sends the composition such as buffer module, reception buffer module, transmission and reception control module, monitor processing module.
Testing software comprises embedded software and PC and holds software two parts, wherein embedded software be operate in PPC processor inside results acquisition, run and to control and state sends software, PC holds software to be the display and control software operated in PC terminal.
Hardware circuit, testing software, test logic are specially:
1, hardware circuit
The hardware circuit of FC switch test equipment is primarily of compositions such as FPGA, PPC processor, photoelectric conversion circuit, power supply, clock, reset, Ethernet, serial ports.
Wherein, FPGA is the core devices of FC switch test equipment, is the carrier that test logic runs; PPC processor is the carrier of embedded software running; The signal of telecommunication that FPGA produces is converted to light signal and passes to optical fiber by photoelectric switching circuit, and the light signal of external fiber is converted to the signal of telecommunication passes to FPGA; External power source adopts 28V, is converted to the various voltage such as 3.3V, 1.8V, passes to related device through voltage conversion device; Clock and reset circuit provide clock and reset for FPGA and PPC processor; Ethernet is used to provide PC and holds the path carrying out high-speed data communication with testing equipment; Serial ports adopts UART interface, is used for supporting debugging.
2, testing software
FC switch test software comprises two parts, and one of them is embedded software, operates on the inner PPC processor of testing equipment; Another is PC end software, operates in PC terminal.
(1) embedded software
Embedded software is developed based on VxWorks plateform system, and software architecture as shown in Figure 1, is divided into three funtion parts, comprises command analysis and management component, state outcome acquisition component and Ethernet data interactive component.
A) Ethernet data interactive component: use the SOCKET interface that provides of vxworks operating system to programme, realizes and control terminal data mutual, and is responsible for shunting the information of the control terminal received, classifies and legitimacy verifies;
B) command analysis and management component: for realizing the response to control terminal order, perform corresponding initialization and control action, realize the configuration to test logic and management, be responsible for carrying out alternately with state outcome acquisition component simultaneously, realize data consistency when test configurations switches and statistics renewal control; C) state outcome acquisition component: for collecting test result, line pipe of going forward side by side is managed, and is sent to control terminal carries out display translation according to setting cycle.
(2) PC holds software
PC holds software to be run on the graphic software platform of windows platform, control and management software, the mutual of parameter, operational order and test mode/object information is configured based on SOCKET communication mode and testing equipment in house software by Ethernet, realize the function such as data stimuli source test configurations, configuration loading, testing and control, collection display, and can report be generated.
3, test logic
Test logic is the core of FC switch test equipment, is described in detail to the embodiment of test logic now.
As shown in Figure 2, test logic is primarily of the composition such as FCMAC module, driving source module, transmission buffer module, reception buffer module, transmission and reception control module, monitor processing module for test logic overall architecture.
(1) FCMAC module
FCMAC module, the Primitive signal of main process optical-fibre channel and primitive sequence, realize port status collection, and need to resolve Frame and encapsulate.As shown in Figure 3, FCMAC module is made up of receive state machine, frame unit and port state machine.
Receive state machine is used for receiving from GT (GigabitTransceiver, high speed serialization transceiver) 16 bit data, 2 K codes, 2 receive mistake and synchronization loss signals, under the control of 2 aligned condition of inner aligned condition machine generation, produce 32 alignment reception data, 4 alignment receive mark and 4 alignment reception mistakes, produce word synchronization loss signal simultaneously;
Frame unit receives data, 4 alignment reception marks and word synchronization loss signal for 32 alignment received from receive state machine, produce 32 FC and receive data, 4 FC reception marks, FC reception useful signal and 48 bit clock synchronization primitives values, meanwhile, produce primitive effectively, 5 primitive codings and frame abandon signal;
Port state machine for receive from frame unit primitive effectively, 5 primitive codings and frame abandon signal, receive from receive state machine word synchronization loss signal, receive and come from that 32 FC sending buffer module send data, 4 FC send mark, send faithlessness, receive faithlessness and frame overlength signals, realize the link state machine that meets FC network standard, and produce according to the state of port the link_up signal that 16 GT send data, 2 GT send K code and representative arrival link synchronization state.
(2) driving source module
As shown in Figure 4, driving source module is made up of parameter configuration logic, Payload formation logic, framing logic, state of a control machine, CRC calculating and EOF polarity computational logic driving source module.
Wherein, parameter configuration logic, after receiving the starting command sending control module, under the control of state of a control machine, is configured SOF, head field contents of this Frame; Payload formation logic can be used for producing various types of data such as pseudo-random data, incremental data, fixed data, and sends to framing logic; Framing logic, under the control of state of a control machine, is filled SOF, head, Payload, CRC, EOF field respectively, produces complete Frame and sends to CRC to calculate and EOF polarity computational logic; CRC calculates and EOF polarity computational logic is responsible for calculating the crc value of Frame and EOF polarity, and inserts respective field, then sends to transmission buffer module.
(3) buffer module is sent
Send buffer module to be responsible for needing the data sent to carry out buffer memory, and be used for and receive data and compare.Sending buffering area adopts dual port RAM to realize, and be divided into side a and b, side a and b is separate.
After transmission buffer module receives the Frame of driving source module transmission, produce and write enable and write address accordingly, Frame is written in dual port RAM by A end; When sending buffer module after receiving the order sending control module, producing and read enable accordingly and read address, hold sense data from the A of dual port RAM and send the data to FCMAC module; When sending after buffer module receives the read command receiving control module, holding sense data from the B of dual port RAM and sending the data to and receive control module and compare.
(4) buffer module is received
The data that reception buffer module is responsible for receiving from FCMAC module carry out buffer memory, and are used for comparing with the data sending buffer module.Reception buffer zone adopts dual port RAM to realize, and be divided into side a and b, side a and b is separate, and wherein B end is used for for CPU access, convenient debugging.
After reception buffer module receives the Frame of FCMAC module transmission, produce and write enable and write address accordingly, Frame is written in dual port RAM by A end; When receiving buffer module after receiving the order receiving control module, producing and read enable accordingly and read address, hold sense data from the A of dual port RAM and send the data to transmission and reception control module.
(5) transmission and reception control module
Transmission and reception control module comprises transmission control module, sends state of a control machine and receive control module.
Send state of a control machine and send data for controlling to send control module, send state of a control machine as shown in Figure 5, redirect flow process is as follows:
1) time initially, send state of a control machine and be in dummy status, the contents such as host configuration test-types, test port, test interval timeout threshold, singlecast router testing time, clean culture competition testing time, multicast testing time, on-air testing number of times, multicast table and broadcast register, also configure the collocation strategy of each port, comprise the contents such as initial frame length, maximum frame length, stepping length;
2) under dummy status, if test enable signals (condition 1) detected, send state of a control machine and then jump to configuration status; Otherwise (condition 2), sends state of a control machine and rests on dummy status;
3) under configuration status, if tested (condition 3), sent state of a control machine and jumped to dummy status; Otherwise (condition 4), sends state of a control machine and jumps to singlecast router test mode;
4) under singlecast router test mode, if test stops (condition 5), then send state of a control machine and jump to dummy status; If singlecast router testing time be 0 or singlecast router tested (condition 6), send state of a control machine and jump to clean culture competition test mode; Otherwise (condition 7), sends state of a control machine and rests on singlecast router test mode;
5) under clean culture competition test mode, if test stops (condition 8), then send state of a control machine and jump to dummy status; Otherwise, if clean culture competition testing time be 0 or clean culture competition test complete (condition 9), send state of a control machine and jump to multicast test mode; Otherwise (condition 10), sends state of a control machine and rests on clean culture competition test mode;
6) under multicast test mode, if test stops (condition 11), then send state of a control machine and jump to dummy status; Otherwise, if multicast testing time be 0 or multicast tested (condition 12), send state of a control machine and jump to on-air testing state; Otherwise (condition 13), sends state of a control machine and rests on multicast test mode;
7) under on-air testing state, if test stops (condition 14), then send state of a control machine and jump to dummy status; Otherwise, if on-air testing number of times be 0 or on-air testing complete (condition 15), send state of a control machine and jump to configuration status; Otherwise (condition 16), sends state of a control machine and rests on on-air testing state.
Send the operation of control module under each state as follows:
Under configuration status, obtain the collocation strategy of each port of host configuration, and be configured; Under singlecast router test mode, carry out singlecast router test, according to the singlecast router testing time of configuration, calculate DID and the frame length of each frame, and send starting command to driving source module; Under clean culture competition test mode, carry out clean culture competition test, according to the clean culture competition testing time of configuration, calculate DID and the frame length of each frame, and send starting command to driving source module; Under multicast test mode, carry out multicast test, according to the multicast testing time of configuration, calculate DID and the frame length of each frame, and send starting command to driving source module; Under on-air testing state, extensively test, according to the on-air testing number of times of configuration, calculate DID and the frame length of each frame, and send starting command to driving source module.
In addition, receive reception and the comparison of control module key data frame, extract the SID of Frame when receiving data frames, and send buffering area transmission read request to corresponding source port, then the data of the data of reading back and reception are compared.If all upper line caps all comparison complete and do not have mistake, then judge that this test is passed through; Otherwise, stop testing and reporting mistake.
(6) monitor processing module
Monitor processing module is used for carrying out the test of supervisor of switch, and the monitoring mode of the policing port of tested FC switch is input monitoring pattern, output monitoring pattern and message monitoring pattern;
Whether monitor processing module monitors tested FC switch Frame that each policing port sends in the following manner correct:
Under input monitoring pattern or message monitoring pattern, after policing port receives Frame, extract the SID of this frame, then according to the transmission buffering area transmission read request of SID to corresponding ports, the Frame that the Frame read back and policing port receive is compared, if made a mistake, then stop test, reporting interruption; Otherwise test proceeds;
Under output monitoring pattern, after policing port receives Frame, extract the DID of this frame, then according to the reception buffer zone transmission read request of DID to corresponding ports, the Frame that the Frame read back and policing port receive is compared, if made a mistake, then stop test, reporting interruption, otherwise test proceeds.
Claims (10)
1. a FC switch test equipment, is characterized in that:
Comprise hardware circuit and test logic unit;
Hardware circuit comprises FPGA, and test logic operates on FPGA;
Test logic is primarily of FCMAC module, driving source module, transmission buffer module, reception buffer module, transmission and reception control module, monitor processing module composition;
FCMAC module, encapsulates Frame to be sent, resolves the Frame received;
Transmission and reception control module comprises transmission control module, sends state of a control machine and receive control module, sends state of a control machine and sends control module transmission data for controlling;
Driving source module is made up of parameter configuration logic, Payload formation logic, framing logic, state of a control machine, CRC calculating and EOF polarity computational logic;
Send control module for start CRC calculate and EOF polarity computational logic by dataframe to sending buffer module;
Payload formation logic is used for producing pseudo-random data, incremental data or fixed data, and sends to framing logic; Framing logic carries out corresponding filling according to the pseudo-random data received, incremental data or fixed data SOF, head, Payload, CRC or EOF field to Frame to be sent;
State of a control machine is used for SOF, head field contents of controling parameters configuration logic to Frame to be sent and is configured, and for controlling the filling of framing logic to Frame to be sent, and is calculated and EOF polarity computational logic to CRC by the dataframe of filling;
CRC calculates and EOF polarity computational logic calculates the crc value of the Frame received and EOF polarity, crc field and the EOF field of result of calculation being inserted Frame to be sent upgrade the Frame received, and by the dataframe upgraded to sending buffer module;
Send the Frame that buffer module receives for buffer memory, and give reception control module and FCMAC module by the dataframe of buffer memory;
Receive the Frame that buffer module is used for the reception of buffer memory FCMAC module, and by the dataframe of buffer memory to receiving control module;
Receive control module to from sending the Frame of buffer module and comparing from receiving the Frame of buffer module, compare whether they consistent;
Whether monitor processing module is correct for monitoring tested FC switch data that each policing port sends.
2. FC switch test equipment according to claim 1, is characterized in that: the transmission buffering area sending buffer module adopts dual port RAM to realize, and be divided into side a and b, side a and b is separate.
3. FC switch test equipment according to claim 2, is characterized in that: described transmission buffer module carries out buffer memory to the Frame received in the following manner:
Send buffer module and write enable and write address according to the Frame generation received, by A end, Frame is written in dual port RAM.
4. FC switch test equipment according to claim 3, is characterized in that: send control module also for sending read command to transmission buffer module;
Send buffer module be in the following manner by the dataframe of buffer memory to receiving control module:
After transmission buffer module receives the read command sending control module, hold sense data from the B of dual port RAM and send the data to reception control module.
5. FC switch test equipment according to claim 4, is characterized in that: send control module also for starting transmission buffer module;
Sending buffer module is in the following manner by the dataframe of buffer memory to FCMAC module:
When sending buffer module after receiving the starting command sending control module, producing and reading enable and read address, holding sense data frame and by dataframe to FCMAC module from the A of dual port RAM.
6. FC switch test equipment according to claim 5, is characterized in that: the reception buffer zone receiving buffer module adopts dual port RAM to realize, and be divided into side a and b, side a and b is separate, and wherein B end is used for for CPU access.
7. FC switch test equipment according to claim 6, is characterized in that: described reception buffer module carries out buffer memory to the Frame received in the following manner:
After reception buffer module receives the Frame of FCMAC module transmission, produce and write enable and write address accordingly, Frame is written in dual port RAM by A end.
8. FC switch test equipment according to claim 7, is characterized in that: described reception control module is used for sending read command to reception buffer module;
Receive buffer module be in the following manner by the dataframe of buffer memory to receiving control module:
When receiving buffer module after receiving the read command receiving control module, producing and reading enable and read address accordingly, holding sense data frame and by dataframe to receiving control module from the A of dual port RAM.
9., according to the arbitrary described FC switch test equipment of claim 1 to 8, it is characterized in that:
The redirect flow process of described transmission state of a control machine is as follows:
1) time initially, send state of a control machine and be in dummy status, host configuration singlecast router testing time, clean culture competition testing time, multicast testing time and on-air testing number of times;
2) under dummy status, if test enable signals detected, send state of a control machine and then jump to configuration status; Otherwise, send state of a control machine and rest on dummy status;
3) under configuration status, if tested, sent state of a control machine and jumped to dummy status; Otherwise, send state of a control machine and jump to singlecast router test mode;
4) under singlecast router test mode, if test stops, then send state of a control machine and jump to dummy status; If singlecast router testing time be 0 or singlecast router tested, send state of a control machine and jump to clean culture competition test mode; Otherwise, send state of a control machine and rest on singlecast router test mode;
5) under clean culture competition test mode, if test stops, then send state of a control machine and jump to dummy status; Otherwise, if clean culture competition testing time be 0 or clean culture competition test complete, send state of a control machine and jump to multicast test mode; Otherwise, send state of a control machine and rest on clean culture competition test mode;
6) under multicast test mode, if test stops, then send state of a control machine and jump to dummy status; Otherwise, if multicast testing time be 0 or multicast tested, send state of a control machine and jump to on-air testing state; Otherwise, send state of a control machine and rest on multicast test mode;
7) under on-air testing state, if test stops, then send state of a control machine and jump to dummy status; Otherwise, if on-air testing number of times be 0 or on-air testing complete, send state of a control machine and jump to configuration status; Otherwise, send state of a control machine and rest on on-air testing state.
10. FC switch test equipment according to claim 9, is characterized in that: the monitoring mode of the policing port of tested FC switch is input monitoring pattern, output monitoring pattern and message monitoring pattern;
Monitor processing module is whether monitor tested FC switch Frame that each policing port sends in the following manner correct:
Under input monitoring pattern or message monitoring pattern, after policing port receives Frame, extract the SID of this frame, then according to the transmission buffering area transmission read request of SID to corresponding ports, the Frame that the Frame read back and policing port receive is compared, if made a mistake, then stop test, reporting interruption; Otherwise test proceeds;
Under output monitoring pattern, after policing port receives Frame, extract the DID of this frame, then according to the reception buffer zone transmission read request of DID to corresponding ports, the Frame that the Frame read back and policing port receive is compared, if made a mistake, then stop test, reporting interruption, otherwise test proceeds.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510889503.3A CN105450475B (en) | 2015-12-07 | 2015-12-07 | A kind of FC switch test equipments |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510889503.3A CN105450475B (en) | 2015-12-07 | 2015-12-07 | A kind of FC switch test equipments |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105450475A true CN105450475A (en) | 2016-03-30 |
| CN105450475B CN105450475B (en) | 2018-10-26 |
Family
ID=55560279
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510889503.3A Active CN105450475B (en) | 2015-12-07 | 2015-12-07 | A kind of FC switch test equipments |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105450475B (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107835103A (en) * | 2017-10-20 | 2018-03-23 | 郑州云海信息技术有限公司 | A kind of FC interchangers virtualization test system and method for testing |
| CN108225479A (en) * | 2016-12-12 | 2018-06-29 | 中国航空工业集团公司西安航空计算技术研究所 | Circuit occurs for aviation fuel-quantity transducer AC sine variable excitation source |
| CN108449287A (en) * | 2016-12-12 | 2018-08-24 | 中国航空工业集团公司西安航空计算技术研究所 | FC exchanger chip architectural frameworks |
| CN108616411A (en) * | 2016-12-12 | 2018-10-02 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of FC monitor cards |
| CN108616372A (en) * | 2016-12-12 | 2018-10-02 | 中国航空工业集团公司西安航空计算技术研究所 | FC switch status inquiry based on serial ports and control method |
| CN112995809A (en) * | 2021-04-22 | 2021-06-18 | 北京国科天迅科技有限公司 | Control method and device of FC switch, FC switch and storage medium |
| CN114006678A (en) * | 2021-11-01 | 2022-02-01 | 合肥国科天迅科技有限公司 | Method for FC-AE equipment to quickly obtain received frame source |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020147569A1 (en) * | 2001-04-09 | 2002-10-10 | Lay Samuel C. | Automatic testing of redundant switching element and automatic switchover |
| CN104253723A (en) * | 2014-09-29 | 2014-12-31 | 电子科技大学 | Software and hardware collaborative implementation-based switch verification test method and device |
| CN104639395A (en) * | 2015-01-08 | 2015-05-20 | 中国航空无线电电子研究所 | Simple simulation testing device for AFDX (avionics full duplex switched Ethernet) switch and testing method for simple simulation testing device |
| CN204425370U (en) * | 2014-12-09 | 2015-06-24 | 中国航空工业集团公司第六三一研究所 | A kind of FC switch supervisory circuit |
-
2015
- 2015-12-07 CN CN201510889503.3A patent/CN105450475B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020147569A1 (en) * | 2001-04-09 | 2002-10-10 | Lay Samuel C. | Automatic testing of redundant switching element and automatic switchover |
| CN104253723A (en) * | 2014-09-29 | 2014-12-31 | 电子科技大学 | Software and hardware collaborative implementation-based switch verification test method and device |
| CN204425370U (en) * | 2014-12-09 | 2015-06-24 | 中国航空工业集团公司第六三一研究所 | A kind of FC switch supervisory circuit |
| CN104639395A (en) * | 2015-01-08 | 2015-05-20 | 中国航空无线电电子研究所 | Simple simulation testing device for AFDX (avionics full duplex switched Ethernet) switch and testing method for simple simulation testing device |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108225479A (en) * | 2016-12-12 | 2018-06-29 | 中国航空工业集团公司西安航空计算技术研究所 | Circuit occurs for aviation fuel-quantity transducer AC sine variable excitation source |
| CN108449287A (en) * | 2016-12-12 | 2018-08-24 | 中国航空工业集团公司西安航空计算技术研究所 | FC exchanger chip architectural frameworks |
| CN108616411A (en) * | 2016-12-12 | 2018-10-02 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of FC monitor cards |
| CN108616372A (en) * | 2016-12-12 | 2018-10-02 | 中国航空工业集团公司西安航空计算技术研究所 | FC switch status inquiry based on serial ports and control method |
| CN108616411B (en) * | 2016-12-12 | 2021-12-24 | 中国航空工业集团公司西安航空计算技术研究所 | FC monitoring card |
| CN108225479B (en) * | 2016-12-12 | 2021-12-24 | 中国航空工业集团公司西安航空计算技术研究所 | Alternating current sine variable excitation source generating circuit of aviation oil mass sensor |
| CN107835103A (en) * | 2017-10-20 | 2018-03-23 | 郑州云海信息技术有限公司 | A kind of FC interchangers virtualization test system and method for testing |
| CN112995809A (en) * | 2021-04-22 | 2021-06-18 | 北京国科天迅科技有限公司 | Control method and device of FC switch, FC switch and storage medium |
| CN112995809B (en) * | 2021-04-22 | 2021-11-23 | 北京国科天迅科技有限公司 | Control method and device of FC switch, FC switch and storage medium |
| CN114006678A (en) * | 2021-11-01 | 2022-02-01 | 合肥国科天迅科技有限公司 | Method for FC-AE equipment to quickly obtain received frame source |
| CN114006678B (en) * | 2021-11-01 | 2024-04-19 | 合肥华控天芯科技有限公司 | Method for quickly acquiring source of received frame by FC-AE equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105450475B (en) | 2018-10-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105450475A (en) | FC switch test device | |
| CN104954198B (en) | A kind of transformer station process layer switch state monitoring apparatus and method | |
| CN103825696A (en) | Device for realizing high-speed real-time communication by optical fibers based on FPGA (Field Programmable Gate Array) | |
| CN102307118B (en) | Back plate test method, apparatus thereof and system thereof | |
| CN105573239A (en) | High speed backboard bus communication control device and method | |
| CN105357070A (en) | FPGA-based ARINC818 bus analysis and test apparatus | |
| CN102752166A (en) | Debugging method, chip, single board and system | |
| CN108282375B (en) | Computer interlocking interface general simulation system and method based on PLC series-parallel technology | |
| CN106598889A (en) | SATA (Serial Advanced Technology Attachment) master controller based on FPGA (Field Programmable Gate Array) sandwich plate | |
| CN105243044B (en) | Management system and management method based on serial ports | |
| CN104407279A (en) | Code type data, apparatus and test method for automatically testing chip MDIO bus protocol | |
| CN104780333A (en) | High-bandwidth video source interface adaptation device based on FPGA (Field Programmable Gate Array) | |
| CN104320317B (en) | A kind of transfer approach and device of ethernet physical layer chip status | |
| CN102664902A (en) | Hardware implementing method for kernels of POWERLINK communication protocol master and slave stations | |
| CN107741915A (en) | A kind of FPGA plate level communicators and communication means based on SDIO interfaces | |
| CN108419336B (en) | LED light screen control system and implementation method thereof | |
| CN103475493A (en) | Intelligent multi-internet-port network card and data processing method | |
| CN111683021A (en) | Multi-protocol terminal with double-path redundant output for switch | |
| CN110457744A (en) | A kind of SD/SDIO device emulation model framework and its design method | |
| WO2016184170A1 (en) | Smi interface device debugging apparatus and method, and storage medium | |
| CN104951385A (en) | Channel health state recording device of dynamic reconfigurable bus monitoring system | |
| CN103428115B (en) | A kind of based on multicasting optical interconnection network framework method between the plate of development board | |
| CN104168172A (en) | Inter-board data interaction device and method based on SWITCH chip | |
| CN205121274U (en) | Serial ports stipulations message signal testing terminal row | |
| CN104717109A (en) | Simulation testing method and system for wide area network links |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |