CN110413464B - Configuration table item testing method and system - Google Patents
Configuration table item testing method and system Download PDFInfo
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- CN110413464B CN110413464B CN201910630183.8A CN201910630183A CN110413464B CN 110413464 B CN110413464 B CN 110413464B CN 201910630183 A CN201910630183 A CN 201910630183A CN 110413464 B CN110413464 B CN 110413464B
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- 238000012360 testing method Methods 0.000 title claims abstract description 151
- 238000000034 method Methods 0.000 claims abstract description 44
- 238000012545 processing Methods 0.000 claims abstract description 25
- 238000004088 simulation Methods 0.000 claims abstract description 20
- 238000010998 test method Methods 0.000 claims description 3
- 230000008676 import Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 5
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- 238000005516 engineering process Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2247—Verification or detection of system hardware configuration
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The application provides a method and a system for testing configuration list items, wherein the method comprises the following steps: the test equipment sends a test instruction to the equipment to be tested through the universal interface; after receiving the test instruction, a CPU in the device to be tested copies a configuration table entry and sends the configuration table entry to the test device through a universal interface; and the test equipment imports the configuration table item into a preset simulation platform, and simulates the query configuration table item in the process of processing the message by the FPGA so as to test the configuration table item.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a method and a system for testing a configuration table entry.
Background
In modern digital circuit design, FPGA (Field-Programmable Gate Array, field programmable gate array) is used as a programmable logic chip, which not only solves the defect of custom circuit, but also overcomes the defect of limited gate number of the original programmable chip. The FPGA has the characteristics of flexible structure, shorter design period, high density, better performance and the like, and based on the characteristics, a CPU and FPGA heterogeneous architecture gradually becomes a common architecture in network equipment, and the architecture can effectively share the load of the CPU.
The FPGA is dynamically configured by the CPU via configuration entries that are typically stored in a memory space corresponding to the FPGA, such as DRAM (Dynamic Random Access Memory ) connected to the FPGA. In the process of processing the message, the FPGA inquires the contents of configuration table entries in the storage space according to service requirements, wherein the configuration table entries are important basis for the FPGA to correctly process the message, and the correct configuration table entries can ensure that network equipment can work normally. When an FPGA processing message fails in network equipment processing, whether the configuration list item is correct or not needs to be determined first, so that a technical scheme capable of testing the configuration list item is urgently needed, and the FPGA problem positioning time is shortened.
In the related art, a developer checks whether the configuration table entry is correct or not by reading the configuration table entry in the storage space through a debugging interface in the network device, but this mode is inefficient.
Disclosure of Invention
In view of the above, the present application provides a method and a system for testing configuration table entries.
Specifically, the application is realized by the following technical scheme:
in a first aspect, an embodiment of the present application provides a configuration table item testing method, which is applied to a configuration table item testing system, where the system includes a testing device and a device to be tested, where the testing device and the device to be tested are connected through a universal interface, and the method includes:
the test equipment sends a test instruction to the equipment to be tested through the universal interface;
after receiving the test instruction, a CPU in the device to be tested copies a configuration table entry and sends the configuration table entry to the test device through a universal interface;
and the test equipment imports the configuration table item into a preset simulation platform, and simulates the query configuration table item in the process of processing the message by the FPGA so as to test the configuration table item.
In a second aspect, an embodiment of the present application provides a configuration table item testing method, which is applied to a configuration table item testing system, where the system includes a testing device and a device to be tested, and the testing device and the device to be tested are connected through a universal interface, and the method includes:
the method comprises the steps that test equipment sends a test instruction to equipment to be tested, wherein the test instruction carries an output port of a configuration table item;
after receiving the test instruction, a CPU in the equipment to be tested issues a configuration table item to a storage space corresponding to an FPGA in the equipment to be tested, and an output port of the configuration table item is set according to the test instruction;
the FPGA in the equipment to be tested copies the configuration list item, packages the configuration list item into a data message, and forwards the data message to an exchange chip in the equipment to be tested, wherein the data message carries the output port;
the exchange chip in the equipment to be tested sends the data message to the test equipment according to the output port;
the test equipment analyzes the data message to obtain the configuration table entry, the configuration table entry is imported into a preset simulation platform, and the configuration table entry is queried and simulated in the process of processing the message by the FPGA so as to test the configuration table entry.
In a third aspect, an embodiment of the present application provides a configuration entry testing system, the system including: the device comprises test equipment and equipment to be tested, wherein the test equipment is connected with the equipment to be tested through a universal interface;
the test equipment sends a test instruction to the equipment to be tested through the universal interface;
after receiving the test instruction, a CPU in the device to be tested copies a configuration table entry and sends the configuration table entry to the test device through a universal interface;
and the test equipment imports the configuration table item into a preset simulation platform, and simulates the query configuration table item in the process of processing the message by the FPGA so as to test the configuration table item.
In a fourth aspect, an embodiment of the present application provides a configuration entry testing system, including: the device comprises test equipment and equipment to be tested, wherein the test equipment is connected with the equipment to be tested through a universal interface;
the method comprises the steps that test equipment sends a test instruction to equipment to be tested, wherein the test instruction carries an output port of a configuration table item;
after receiving the test instruction, a CPU in the equipment to be tested issues a configuration table item to a storage space corresponding to an FPGA in the equipment to be tested, and an output port of the configuration table item is set according to the test instruction;
the FPGA in the equipment to be tested copies the configuration list item, packages the configuration list item into a data message, and forwards the data message to an exchange chip in the equipment to be tested, wherein the data message carries the output port;
the exchange chip in the equipment to be tested sends the data message to the test equipment according to the output port;
the test equipment analyzes the data message to obtain the configuration table entry, the configuration table entry is imported into a preset simulation platform, and the configuration table entry is queried and simulated in the process of processing the message by the FPGA so as to test the configuration table entry.
According to the technical scheme provided by the embodiment of the application, the configuration list items are copied and imported into the preset simulation platform, and the configuration list items are inquired and simulated in the process of processing the message by the FPGA so as to test the configuration list items, so that the problem of the FPGA can be positioned more conveniently, and the efficiency is improved effectively.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may be obtained according to these drawings for those of ordinary skill in the art.
FIG. 1 is a schematic diagram illustrating a connection between a test device and a device under test according to an exemplary embodiment of the present application;
FIG. 2 is a schematic diagram illustrating an interactive flow of a configuration entry testing method according to an exemplary embodiment of the present application;
FIG. 3 is a schematic diagram illustrating an interactive flow of another configuration entry testing method according to an exemplary embodiment of the present application.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the application. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "responsive to a determination", depending on the context.
In the related art, a developer checks whether the configuration table entry is correct or not by reading the configuration table entry in the storage space through a debugging interface in the network device, but this mode is inefficient.
In view of the above technical problems, the embodiments of the present application provide a technical solution, where a test device and a device to be tested are connected through a universal interface (in the embodiments of the present application, the universal interface includes a USB interface, a serial port, a network port, etc.), as shown in fig. 1, by copying a configuration table entry and importing a preset simulation platform, a configuration table entry is queried and simulated in a process of processing a message by an FPGA, so as to test the configuration table entry, thereby enabling positioning of the FPGA problem to be more convenient and efficient.
In order to describe the technical solution provided by the embodiments of the present application in detail, the following embodiments are provided:
taking connection between a test device and a device to be tested through a serial port as an example, as shown in fig. 2, an interactive flow diagram of a configuration table item test method provided by an embodiment of the present application is shown, where the method specifically may include the following steps:
s201, test equipment sends a test instruction to equipment to be tested through a universal interface;
in the embodiment of the application, after the test function of the test equipment configuration table item is started, the test equipment sends a test instruction to the equipment to be tested. For example, the test device sends a test instruction to the device under test through the serial port.
S202, after a CPU in the device to be tested receives the test instruction, copying a configuration table entry, and sending the configuration table entry to the test device through a universal interface;
and the CPU in the equipment to be tested receives the test instruction and copies the configuration list item after receiving the test instruction, wherein the configuration list item can be copied while the configuration list item is issued to the FPGA in the equipment to be tested, and the configuration list item is generated by the CPU in the equipment to be tested.
In this way, on one hand, the CPU in the device to be tested issues the configuration table item to the FPGA in the device to be tested, and stores the configuration table item in a storage space corresponding to the FPGA in the device to be tested, for example, in the DRAM connected to the FPGA, and on the other hand, the CPU in the device to be tested copies the configuration table item and sends the configuration table item to the test device through the serial port.
S203, the test equipment imports the configuration table item into a preset simulation platform, and simulates the configuration table item queried in the process of processing the message by the FPGA so as to test the configuration table item.
After receiving the configuration list item, the test equipment stores the configuration list item locally, generates a configuration file according to the configuration list item, guides the configuration file into a preset simulation platform, and simulates the query configuration list item in the process of processing the message by the FPGA so as to test the configuration list item.
In this way, in the embodiment of the application, the configuration list item is copied and converted into the file, and the file is imported into the preset simulation platform to simulate the query configuration list item in the process of processing the message by the FPGA so as to test the configuration list item, thereby ensuring that the problem of the FPGA is positioned more conveniently and effectively improving the efficiency.
Taking connection between a test device and a device to be tested through a network port as an example, as shown in fig. 3, an interactive flow diagram of another configuration table item test method provided by an embodiment of the present application is shown, where the method specifically may include the following steps:
s301, test equipment sends a test instruction to equipment to be tested, wherein the test instruction carries an output port of a configuration table item;
in the embodiment of the application, after the test function of the test equipment configuration table item is started, the test equipment sends a test instruction to the equipment to be tested. For example, the test device sends a test instruction to the device under test through the portal.
And for the test instruction, the output port carrying the configuration table entry is used for guiding the output port of the configuration table entry.
S302, after receiving the test instruction, a CPU in the device to be tested issues a configuration table item to a storage space corresponding to an FPGA in the device to be tested, and an output port of the configuration table item is set according to the test instruction;
and after receiving the test instruction, the CPU in the device to be tested issues the configuration list item to a storage space corresponding to the FPGA in the device to be tested, for example, issues the configuration list item to a DRAM connected with the FPGA.
And setting the output port of the configuration table item according to the output port of the configuration table item carried in the test instruction.
S303, the FPGA in the equipment to be tested replicates the configuration list item, encapsulates the configuration list item into a data message and forwards the data message to an exchange chip in the equipment to be tested, wherein the data message carries the output port;
and for the configuration list item in the storage space, the FPGA in the equipment to be tested copies the configuration list item and encapsulates the configuration list item into an Ethernet data message, wherein the data message carries an output port, namely the set output port is added in the message header of the data message.
After the processing, the data message is forwarded to a switching chip in the equipment to be tested.
S304, the exchange chip in the equipment to be tested sends the data message to the test equipment according to the output port;
and the exchange chip in the equipment to be tested analyzes the message header of the data message to obtain the set output port, and the data message is sent to the testing equipment according to the output port.
S305, analyzing the data message by the testing equipment to obtain the configuration table item, importing the configuration table item into a preset simulation platform, and simulating the query configuration table item in the process of processing the message by the FPGA so as to test the configuration table item.
The test equipment receives the data message, analyzes the data message to obtain the configuration list item, and stores the configuration list item to the local.
For the configuration list items, a configuration file can be generated, the configuration file is imported into a preset simulation platform, and the configuration list items are queried and simulated in the process of processing the message by the FPGA so as to test the configuration list items.
In this way, in the embodiment of the application, the configuration list item is copied and converted into the file, and the file is imported into the preset simulation platform to simulate the query configuration list item in the process of processing the message by the FPGA so as to test the configuration list item, thereby ensuring that the problem of the FPGA is positioned more conveniently and effectively improving the efficiency.
Corresponding to the method embodiment, the embodiment of the application also provides a configuration table item testing system, which comprises: the device comprises test equipment and equipment to be tested, wherein the test equipment is connected with the equipment to be tested through a universal interface;
the test equipment sends a test instruction to the equipment to be tested through the universal interface;
after receiving the test instruction, a CPU in the device to be tested copies a configuration table entry and sends the configuration table entry to the test device through a universal interface;
and the test equipment imports the configuration table item into a preset simulation platform, and simulates the query configuration table item in the process of processing the message by the FPGA so as to test the configuration table item.
The embodiment of the application also provides a configuration list item testing system, which comprises: the device comprises test equipment and equipment to be tested, wherein the test equipment is connected with the equipment to be tested through a universal interface;
the method comprises the steps that test equipment sends a test instruction to equipment to be tested, wherein the test instruction carries an output port of a configuration table item;
after receiving the test instruction, a CPU in the equipment to be tested issues a configuration table item to a storage space corresponding to an FPGA in the equipment to be tested, and an output port of the configuration table item is set according to the test instruction;
the FPGA in the equipment to be tested copies the configuration list item, packages the configuration list item into a data message, and forwards the data message to an exchange chip in the equipment to be tested, wherein the data message carries the output port;
the exchange chip in the equipment to be tested sends the data message to the test equipment according to the output port;
the test equipment analyzes the data message to obtain the configuration table entry, the configuration table entry is imported into a preset simulation platform, and the configuration table entry is queried and simulated in the process of processing the message by the FPGA so as to test the configuration table entry.
The implementation process of the functions and roles of each unit in the above device is specifically shown in the implementation process of the corresponding steps in the above method, and will not be described herein again.
Through the description of the technical scheme provided by the embodiment of the application, the storage address is allocated to the received message, the occupied time length of the storage address is counted, whether the occupied time length of the storage address exceeds a preset threshold value is judged, whether the storage address is released is detected under the condition that the occupied time length of the storage address exceeds the preset threshold value, and the FPGA state is determined according to the detection result. Because the occupied time of the storage address is generally shorter, the FPGA state can be fed back quickly, and the feedback time of the FPGA state is shortened.
For system embodiments, reference is made to the description of method embodiments for the relevant points, since they essentially correspond to the method embodiments. The system embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purposes of the present application. Those of ordinary skill in the art will understand and implement the present application without undue burden.
The application may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The application may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.
The foregoing is merely illustrative of the embodiments of this application and it will be appreciated by those skilled in the art that variations and modifications may be made without departing from the principles of the application, and it is intended to cover all modifications and variations as fall within the scope of the application.
Claims (4)
1. The utility model provides a configuration table item test method, is applied to configuration table item test system, the system includes test equipment and equipment to be tested, test equipment and equipment to be tested are connected through general interface, characterized in that, the method includes:
the method comprises the steps that test equipment sends a test instruction to equipment to be tested, wherein the test instruction carries an output port of a configuration table item;
after receiving the test instruction, a CPU in the equipment to be tested issues a configuration table item to a storage space corresponding to an FPGA in the equipment to be tested, and an output port of the configuration table item is set according to the test instruction;
the FPGA in the equipment to be tested copies the configuration list item, packages the configuration list item into a data message, and forwards the data message to an exchange chip in the equipment to be tested, wherein the data message carries the output port;
the exchange chip in the equipment to be tested sends the data message to the test equipment according to the output port;
the test equipment analyzes the data message to obtain the configuration table entry, the configuration table entry is imported into a preset simulation platform, and the configuration table entry is queried and simulated in the process of processing the message by the FPGA so as to test the configuration table entry.
2. The method of claim 1, wherein the importing the configuration table entry into a preset simulation platform simulates a query configuration table entry in a process of processing a message by the FPGA to test the configuration table entry, and comprises:
generating a configuration file according to the configuration list item, importing the configuration file into a preset simulation platform, and simulating the query configuration list item in the process of processing the message by the FPGA so as to test the configuration list item.
3. A configuration entry testing system, the system comprising: the device comprises test equipment and equipment to be tested, wherein the test equipment is connected with the equipment to be tested through a universal interface;
the method comprises the steps that test equipment sends a test instruction to equipment to be tested, wherein the test instruction carries an output port of a configuration table item;
after receiving the test instruction, a CPU in the equipment to be tested issues a configuration table item to a storage space corresponding to an FPGA in the equipment to be tested, and an output port of the configuration table item is set according to the test instruction;
the FPGA in the equipment to be tested copies the configuration list item, packages the configuration list item into a data message, and forwards the data message to an exchange chip in the equipment to be tested, wherein the data message carries the output port;
the exchange chip in the equipment to be tested sends the data message to the test equipment according to the output port;
the test equipment analyzes the data message to obtain the configuration table entry, the configuration table entry is imported into a preset simulation platform, and the configuration table entry is queried and simulated in the process of processing the message by the FPGA so as to test the configuration table entry.
4. A system according to claim 3, characterized in that the test equipment tests the configuration table entry in particular by:
generating a configuration file according to the configuration list item, importing the configuration file into a preset simulation platform, and simulating the query configuration list item in the process of processing the message by the FPGA so as to test the configuration list item.
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