CN103426862A - 铜互连结构及其形成方法 - Google Patents

铜互连结构及其形成方法 Download PDF

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CN103426862A
CN103426862A CN2013101810247A CN201310181024A CN103426862A CN 103426862 A CN103426862 A CN 103426862A CN 2013101810247 A CN2013101810247 A CN 2013101810247A CN 201310181024 A CN201310181024 A CN 201310181024A CN 103426862 A CN103426862 A CN 103426862A
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D·C·埃德尔斯坦
T·诺加米
C·帕克斯
T-L·泰
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Abstract

本发明的实施例涉及铜互连结构及其形成方法。一种具有提高的电迁移抗性的结构和用于制作该结构的方法。一种具有提高的电迁移抗性的结构包括具有双层盖和电介质覆盖层的本体互连。该双层盖包括底部金属部分和顶部金属氧化物部分。优选地，金属氧化物部分是MnO或MnSiO并且金属部分是Mn或CuMn。该结构通过用(在优选实施例中为Mn的)杂质掺杂互连，然后在互连的顶部部分创造晶格缺陷。缺陷将增加的杂质迁移驱向互连的定表面。在形成电介质覆盖层时，部分与分凝的杂质反应，从而在互连上形成双层。Cu表面的晶格缺陷可以通过等离子处理、离子注入、压缩薄膜或其他手段来创造。

Description

铜互连结构及其形成方法
技术领域
本发明总体涉及微电子器件的互连结构。具体而言，本发明涉及用于通过在互连中创造缺陷以增强杂质分凝来提高电迁移抗性的方法和结构。
背景技术
电迁移是在导体中由于电流所引起的金属原子迁移。金属原子迁移意指金属原子从第一区移动至第二区。结果，迁移的金属原子在第一区中留下空洞。空洞可以随着时间生长到足以增加互连的电阻的尺寸；或者空洞可以在互连中形成开路。无论哪种方式，互连都会失效。形成造成互连失效的空洞所需的时间被称为电迁移寿命。在微电子器件中所使用的铜互连中，电迁移寿命由铜与电介质覆盖层之间的介面处的质量输送所确定。相应地，许多提高电迁移抗性(electromigration resistance)的方案旨在提高电介质帽与铜之间的粘附。
一种方案在互连的顶表面上使用自对准CuSiN盖；另一种方案使用CoWP的自对准金属盖，而其他方案使用合金籽层。在该合金方案中，在铜(Cu)籽层中引入了掺杂剂(杂质)。在随后处理期间，杂质分凝至电介质盖/Cu介面以形成杂质氧化层。杂质的量越多，电迁移抗性就越大(即更长的电迁移寿命)。然而，杂质增加互连的电阻。此外，杂质至介面的分凝被认为受到杂质氧化物形成的限制。因此，一旦形成所有杂质氧化物，则不再存在杂质分凝的驱动力，并且杂质就保留在本体铜中，由此增加了互连电阻。此外，随着互连线宽缩小，需要更多杂质以增长电迁移寿命，从而进一步加剧了电阻增加的问题。
因此，需要一种用于提高电迁移抗性的方法和结构，其提高电迁移寿命而不过度增加铜互连的电阻。此外，该方法和结构可以是可缩放的以适应减小的互连线宽。
发明内容
本发明的一般原理在于通过在铜互连的表面有意地创造晶格缺陷来提高电迁移寿命而不过分增加互连电阻的方法。该缺陷驱动杂质(掺杂剂)分凝至该区域。因此，可以使用杂质的更高的原子百分比而不增加互连的电阻。
在一个实施例中，互连结构包括金属氧化物部分、金属部分、以及具有顶部区域的本体导体部分。金属部分位于本体导体的顶部区域，并且金属氧化物部分在金属部分的上方。
在另一实施例中，互连结构包括氧化锰部分、金属锰部分，以及具有顶部区域的铜部分。金属锰部分位于铜的顶部区域，并且氧化锰部分在金属锰部分的上方。
一种形成具有提高的电迁移抗性的互连结构的方法的实施例包括：在衬底上的电介质区域中形成开口、形成含杂质层、用本体导体基本填充开口、对本体导体的顶部区域加压或者在本体导体的顶部区域创造缺陷，以及对衬底进行热处理，由此在本体导体的顶部区域形成含杂质氧化物层和金属杂质层。
附图说明
图1A是根据本发明的实施例的互连结构的截面图；
图1B是根据本发明的实施例的另一互连结构的截面图；
图2是示出了用于创造图1A的双层互连结构的方法的实施例的流程图；
图3A示出了根据本发明的方法步骤的实施例的在电介质中的开口中形成的衬垫；
图3B示出了根据本发明的方法步骤的实施例的在电介质中的开口中的本体导体；
图3C示出了根据本发明的方法步骤的实施例在本体导体的顶部部分创造晶格损伤；
图3D示出了根据本发明的方法步骤另一实施例在本体导体的顶部部分创造晶格损伤；以及
图3E示出了根据本发明的方法步骤的实施例形成覆盖层。
本发明的其他目的、方面和优点将结合对附图的描述变得明显，其中相同的标号代表所有图中的相同或相似的部分。
具体实施方式
结合图1A-图1B描述了本发明的互连结构的实施例。结合图2-图3E描述了用于形成本发明的互连结构的方法的实施例。
参照图1A，示出了本发明的互连结构100的实施例。互连结构100包括本体导体130，该本体导体130具有顶部132和底部134区域。互连结构100基本上嵌入电介质110。在图1A的实施例中，该本体导体被衬垫120三面包围。在其他一些实施例中，可以没有衬垫120，仅在侧壁上存在衬垫120，或者在本体导体130的底部区域134上仅存在衬垫120的部分。在本体导体130的顶部区域132存在金属部分140。在金属部分140上方的是金属氧化物部分150。在图1A的优选实施例中，金属部分140和金属氧化物部分150都在两侧具有衬垫120。因此，在优选实施例中，互连包括本体导体130，其在顶部区域132具有双层(金属部分140和金属氧化物部分150)，都被在电介质110开口中的衬垫120所包围，使得衬垫120、金属氧化物部分150和电介质110基本共面。图1A还示出了电介质110上方的覆盖层160、衬垫120和氧化物部分150。在图1B中所示的另一实施例中，电介质110、衬垫120和金属部分140基本共面。在此，金属氧化物部分150在金属部分140上方，但不以衬垫120为边界。互连结构具有互连线宽170。
在一个优选实施例中，本体导体130基本是铜，这意味着在本体导体中可以或很可能会存在杂质，但是导体主要是铜。衬垫120可以包括一层或多层材料。衬垫120的功能在于提升本体导体130与电介质110的粘附，和/或防止铜从本体导体130扩散至电介质110。衬垫材料可以包括元素周期表的IVB至VIB族元素、VIIIB族元素、本体导体的合金、金属氧化物以及金属氮化物。在一个优选实施例中，衬垫120包括钽(Ta)层以及氮化钽(TaN)层。在另一个优选实施例中，衬垫120包括Ta层、TaN层以及含锰(Mn)合金部分。
在一个优选实施例中，金属部分140是含有金属键合状态(与氧化键合状态相对)的金属杂质(掺杂剂)。金属键合状态存在于纯金属、金属合金(即，两种或更多种金属的固溶体或混合物)，或金属间化合物(即，存在固定的化学计量)中。在一个优选实施例中，金属杂质(掺杂剂)是Mn。在一个优选实施例中，因为Mn与优选为铜的本体导体130合铸，所以Mn处于金属键合状态。因此，在该优选实施例中，金属部分140是CuMn。要注意的是，在先前对本体导体130的描述中，谈到过本体导体可以具有杂质。本体导体130中的杂质可以是Mn。因此，在该优选实施例中，具有Mn杂质的本体导体130与金属部分140之间的区别是金属部分140中Mn的量大于本体导体130中Mn的量。因此，金属部分140是互连结构中的、已被金属杂质(掺杂剂)优先分凝至的部分。虽然所优选实施例描述了金属部分140中的一种杂质(掺杂剂)，但是在金属部分140中可以存在多种杂质(掺杂剂)。举例而非限制而言，金属部分140的杂质(掺杂剂)可以包括一种或多种如下过渡金属元素或其他金属元素：Mn、Al、Ti、Zn、Sn和In。
金属氧化物部分150是包括金属和氧的层。在一个优选实施例中，金属是Mn，从而金属氧化物部分是MnO。金属氧化物部分150还可以包括除金属和氧之外的元素，例如Si。因此，另一实施例可以是MnSiO。
如图1A所示，金属部分140和金属氧化物150在本体导体的顶部形成双层。在一个优选实施例中，金属氧化物部分150的金属与金属部分140的金属为同一类型的金属，即Mn。在一个优选实施例中，本体导体130是具有Mn杂质的铜。在该优选实施例中，在双层中所发现的Mn的量大于或等于在整个互连结构中所发现的Mn的量的60％并且在其间变化。
电介质110可以包括一层或多层绝缘材料。绝缘材料通常包括纯净或掺杂的硅酸盐玻璃；在一个优选实施例中，掺杂是氟或碳。绝缘材料可以是有孔的。优选地，电介质110具有小于4的介电常数。
覆盖层160是含氮绝缘材料。在一个优选实施例中，覆盖层160是SiCN。在另一个优选实施例中，覆盖层160具有比本体导体130的热膨胀系数更大的热膨胀系数。
上述双层结构的优点在于，更多的金属掺杂剂(优选为Mn)可以分凝到本体导体(优选为铜)的顶表面。顶表面的双层提供更强的覆盖层-本体导体耦合，这阻碍铜迁移并且因此延长电迁移寿命。金属氧化物(优选为MnO或MnSiO)和金属部分的双层结构提供更多地掺入金属掺杂剂(即杂质)而不过分增加本体导体的电阻。
参照图2，呈现了用于创造图1A的双层结构的方法的实施例的流程图。该方法包括如下步骤：提供具有开口的电介质；形成衬垫；形成本体导体；抛光该导体；在本体导体中创造晶格损伤；以及形成覆盖层。
参照图3A，示出了具有开口115的电介质110。电介质110的开口115具有在其中形成的衬垫120。在此实施例中，衬垫120包括含杂质(掺杂剂)合金。如先前结合图1A和图1B描述的，除含杂质(掺杂剂)合金之外，其他层也可以被包括在衬垫120中。合金的杂质(掺杂剂)可以包括一种或多种如下过渡金属元素或其他金属元素：Mn、Al、Ti、Zn、Sn和In。在一个优选实施例中，杂质是Mn，从而合金是CuMn。合金中沉积的杂质的百分比从约0.25原子百分比至约2.0原子百分比，并且在其间变化。衬垫120层可以通过一种或多种如下方法形成：化学气相沉积(CVD)、原子层沉积(ALD)，以及物理气相沉积(PVD)。
参照图3B，本体导体130被形成为填充并且溢出开口115。参照图3C和图3D，本体导体130被抛光成：或者(1)与衬垫共面，如图3C；或者(2)与电介质110共面，如图3D。在任一点处(在图3C中的本体导体抛光之后或在图3D中的衬垫抛光之后)，可以应用晶格损伤技术260(由箭头表示)中的一种。
晶格损伤技术260包括向本体导体的顶部区域加压，以及在本体导体的顶部区域中创造缺陷。向导体的顶部加压可以通过在本体导体之上形成具有比本体导体更低的热膨胀系数的覆盖层来实现。在此情况中形成了过度压应力。加压还可以通过形成电介质层和UV固化以在本体导体的顶部区域中引起过度压应力来实现。可以通过如下方式创造缺陷：等离子轰击本体导体130以嵌入原子(优选为中性原子，例如氩)，对本体导体130进行离子注入，对具有高初始偏置(bias)的覆盖层进行沉积以创造损伤，以及在氧化本体导体130之后进行还原。氧化可以通过将本体导体的顶部区域暴露在含氧的氛围中来完成。还原可以通过将本体导体的顶部区域暴露在含氮或氢的环境中来完成。对同一结构可以应用一种或多种晶格损伤技术260。可以随覆盖层160形成原位执行晶格损伤技术，或者可以在覆盖层160形成之前非原位执行此类技术。对本体导体130应用晶格损伤技术260的目的是在导体的顶部区域创造晶格缺陷。晶格缺陷将作为杂质(掺杂)宿(sink)。
参照图3E，形成了覆盖层160。通过在从约300C至约400C并且在其间变化的温度下进行的等离子增强气相沉积(PECVD)来形成该覆盖层。升高的温度将杂质从衬垫120的含杂质合金层和/或本体导体130驱向覆盖层-本体导体层介面。在覆盖层-本体导体介面处，杂质与覆盖层反应形成金属氧化薄膜160。即便覆盖层是SiCN，仍会形成金属氧化物薄膜160，因为来自于覆盖工具真空系统中H2O的残余分压的偶生氧通常在盖(cap)沉积处理的陈化和预清洗步骤期间引入Cu/盖介面处。正常地，一旦形成金属氧化物160，杂质至覆盖层-本体导体介面的迁移驱动力在很大程度上得以满足。然而，本体导体的顶部存在的晶格缺陷将杂质的迁移进一步驱向该介面。因此，杂质继续分凝至本体导体的顶表面132并且形成金属部分140。结果，在衬垫层120将发现更少量的杂质或无杂质。
晶格缺陷的附加分凝驱动力意指杂质(掺杂剂)主要被发现在双层中而不是本体导体130中。结果，可以在衬垫120的合金籽层中使用更高百分比的掺杂剂。该更高百分比迁移至双层而不增加本体导体的电阻。因此，通过使用这些晶格损伤方法以创造双层的方式，可以达到更小线宽的电迁移抗性。在此，更小的线宽包括小于约100nm至约30nm的线宽和更低的线宽。
虽然已经参照目前所认为的优选实施例描述了本发明，要理解的是本发明并不限于所公开的实施例。与此相反，本发明旨在涵盖所附权利要求的精神和范围所包括的各种修改和等同的布置。以下权利要求的范围应符合最广义的解释以便包含所有此类修改和等同的结构和功能。

Claims (19)

1.一种互连结构，包括：
金属氧化物部分；
金属部分；以及
具有顶部区域的本体导体部分。
其中所述金属部分在所述顶部区域处并且所述金属氧化物部分在所述金属部分上方。
2.根据权利要求1所述的结构，进一步包括：
覆盖层，所述覆盖层具有比所述本体导体的热膨胀系数更小的热膨胀系数。
3.根据权利要求2所述的结构，其中所述覆盖层是含氮绝缘体层，或者是包括含氮绝缘体层的薄膜堆叠。
4.根据权利要求1所述的结构，其中所述金属部分包括从由Mn、Al、Ti、Zn、Sn和In所组成的组中所选择的元素中的至少一种。
5.根据权利要求1所述的结构，其中所述金属氧化物部分的金属与所述金属部分的金属是相同金属元素。
6.根据权利要求5所述的结构，其中所述相同金属元素在所述金属氧化物部分中的百分比与所述相同金属元素在所述金属锰部分中的百分比之和比所述相同金属元素在所述本体导体中的百分比大1.5倍。
7.根据权利要求5所述的结构，其中所述相同金属元素是Mn。
8.根据权利要求1所述的结构，其中所述互连结构具有线宽，其中所述线宽小于或等于30纳米。
9.一种互连结构，包括：
锰氧化物部分；
金属锰部分；以及
具有顶部区域的铜部分；
其中所述金属锰部分在所述顶部区域处，并且所述锰氧化物部分在所述金属锰部分上方。
10.根据权利要求9所述的结构，进一步包括：在所述锰氧化物部分上方的覆盖层，其中所述覆盖层包括含氮绝缘体层。
11.根据权利要求9所述的结构，其中Mn在所述锰氧化物部分中的百分比与Mn在所述金属锰部分中的百分比之和比Mn在所述本体导体中的百分比大1.5倍。
12.根据权利要求9所述的结构，其中所述互连具有线宽，其中所述线宽小于或等于100纳米。
13.一种用于形成具有提高的电迁移抗性的互连结构的方法，所述方法包括：
在衬底上的电介质区域中形成开口；
形成含杂质层；
用本体导体基本填充所述开口；
对所述本体导体的顶部区域加压或者在所述本体导体的顶部区域处创造缺陷；以及
对所述衬底热处理，由此在所述本体导体的顶部区域处形成含杂质氧化物层和金属杂质层。
14.根据权利要求13所述的方法，其中对所述本体导体的顶部区域加压是通过在所述本体导体之上形成覆盖层，其中所述覆盖层具有比所述本体导体更低的热膨胀系数。
15.根据权利要求13所述的方法，其中加压包括形成电介质层以及UV固化以在所述本体导体的顶部区域中引起压应力。
16.根据权利要求13所述的方法，其中所述本体导体的顶部区域被压缩。
17.根据权利要求13所述的方法，其中创造缺陷包括用惰性气体对所述本体导体的顶部区域进行离子注入。
18.根据权利要求13所述的方法，其中创造缺陷包括对所述本体导体的顶部区域进行等离子处理。
19.根据权利要求13所述的方法，其中创造缺陷包括在氧化所述本体导体的顶部区域之后还原所述顶部区域。
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