CN103390596A - Insulation packaging device of semiconductor and manufacturing method of insulation packaging device - Google Patents
Insulation packaging device of semiconductor and manufacturing method of insulation packaging device Download PDFInfo
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- CN103390596A CN103390596A CN2012101415737A CN201210141573A CN103390596A CN 103390596 A CN103390596 A CN 103390596A CN 2012101415737 A CN2012101415737 A CN 2012101415737A CN 201210141573 A CN201210141573 A CN 201210141573A CN 103390596 A CN103390596 A CN 103390596A
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Abstract
The invention discloses an insulation packaging device of a semiconductor. The semiconductor is provided with a substrate and at least one semiconductor assembly arranged on the substrate. The insulation packaging device of the semiconductor is suitable for covering the semiconductor and comprises a metal base material, metal plating and an insulation adhesion layer. The metal base material is in a sheet shape. The metal plating covers the surface of the metal base material in a plating mode. The insulation adhesion layer is combined to one side of the metal plating and arranged on the semiconductor.
Description
Technical field
The invention relates to a kind of packaging system and manufacture method thereof, refer to especially a kind of for semi-conductive insulation-encapsulated device and manufacture method thereof.
Background technology
Lasting progress along with the semiconductor preparation, existing semiconductor subassembly is except usefulness promotes gradually, its volume also progressively dwindles, but relative, the heat that produces while also causing existing semiconductor subassembly running increases gradually,, cause efficiency to glide or even damage to avoid semiconductor subassembly because of excess Temperature for improving heat radiation efficiency, therefore the existence of the fin of semiconductor chip has just been arranged.
Consult Fig. 1, general semiconductor chip 1, usually be arranged on semiconductor substrate 10 and be coated with thereon a fin 2, utilize this fin 2 to contact with this semiconductor chip 1, the mode that the thermal source utilization that is produced with 1 running of this semiconductor chip the time increases area of dissipation conducts, to alleviate the too much problem of semiconductor chip 1 heat.
But, as everyone knows, progress along with the science and technology preparation, the volume of electronic product is more done less, the related volume of the semiconductor chip 1 that uses that makes is also more and more little, also more contracting is less for the volume that relatively causes this metal fin 2, so, can cause this semiconductor chip 1 with this fin 2 in the scolding tin seam of packaging operation or the difficulty in chimeric operation.In addition, along with semiconductor chip 1 and the volume of this fin 2 more contract less, also can make the gap H of 2 of this semiconductor chip 1 and this fin more and more little, careless slightly (for example the deflection of fin 2 is larger), will make metal fin 2 produce improper the contact and short circuit with this semiconductor chip 1, or exterior static interference, cause this semiconductor chip 1 to break down, therefore the yield of this semiconductor chip 1 encapsulation just reduces.
Therefore, how at this fin 2 and this semiconductor chip 1 gradually under the situation of microminiaturization, still have high stability and can improve the inconvenience of seam or chimeric operation, improve the yield of semiconductor chip 1 encapsulation, simultaneously can keep good radiating effect, just become relevant dealer and need the target of effort badly.
Summary of the invention
In view of this, the technical problem to be solved in the present invention is to provide a kind of and applies conveniently, stability is high, and excellent in heat dissipation effect be used for semi-conductive insulation-encapsulated device.
For solving the problems of the technologies described above, technical scheme of the present invention is achieved in that a kind of semi-conductive insulation-encapsulated device, this semiconductor has a substrate, and at least one semiconductor subassembly that is arranged on this substrate, this semi-conductive insulation-encapsulated device is applicable to be covered on this semiconductor, and comprise: a metal base, a coat of metal, and an insulation adhesion layer.Generally in the form of sheets, this coat of metal plating is in the surface of this metal base for this metal base, and this insulation adhesion layer is incorporated into a side of this coat of metal.
And another object of the present invention, namely providing a kind of and apply conveniently, stability is high, and the manufacture method that is used for semi-conductive insulation-encapsulated device of excellent in heat dissipation effect.
So the manufacture method of insulation-encapsulated device of the present invention, comprise the following step.At first, prepare a metal base.Then, plating one coat of metal on this metal base.Then, apply an insulation adhesion layer on this coat of metal, and be attached on this semiconductor substrate.
The technique effect that the present invention reaches is as follows: utilize the rough surface of this coat of metal to promote and this insulation adhesion layer between adhesion, coordinate insulation that this insulation adhesion layer can produce and stick together effect, not only can be directly and semiconductor subassembly bind, the problem of avoiding the seam operation to be difficult for, more can really avoid this semiconductor subassembly to contact with this coat of metal, and then improve stability and radiating effect.
Description of drawings
Fig. 1 is a cross-sectional schematic, and the existing structure that is used for semi-conductive packaging system is described;
Fig. 2 is a partial schematic sectional view, and the first preferred embodiment of the semi-conductive insulation-encapsulated device of the present invention is described;
Fig. 3 is a partial schematic sectional view, and another enforcement structure of this first preferred embodiment is described;
Fig. 4 is a partial schematic sectional view, and the second preferred embodiment of the semi-conductive insulation-encapsulated device of the present invention is described;
Fig. 5 is a partial schematic sectional view, and the 3rd preferred embodiment of the semi-conductive insulation-encapsulated device of the present invention is described;
Fig. 6 is a partial schematic sectional view, and another enforcement structure of the 3rd preferred embodiment is described;
Fig. 7 is a partial schematic sectional view, and the 4th preferred embodiment of the semi-conductive insulation-encapsulated device of the present invention is described;
Fig. 8 is a flow chart, and first preferred embodiment of manufacture method of the insulation-encapsulated device of semiconductor 88 chips of the present invention is described;
Fig. 9 is a local enlarged diagram, the rough surface of aid illustration one coat of metal; And
Figure 10 is a partial schematic sectional view, aid illustration with a metal base punch forming for generally being the shape of falling U, on the substrate that can be covered in semiconductor chip.
Embodiment
, about aforementioned and other technology contents, characteristics and effect of the present invention, in the following detailed description that coordinates with reference to graphic a plurality of preferred embodiments, can clearly present.
In addition, it should be noted, before being elaborated, similarly assembly is to represent with identical numbering.
Consult Fig. 2, Fig. 3, be the first preferred embodiment of the insulation-encapsulated device 6 of semiconductor 5 of the present invention.This semiconductor 5 has a substrate 51, and at least one assembly 52 that is arranged on this substrate 51.It should be noted, this assembly 52 can be semiconductor chip, electronic building brick or passive component etc. one of them, in this first preferred embodiment, this assembly 52 is semiconductor chips.
The insulation-encapsulated device 6 of this semiconductor 5 is applicable to be covered on this semiconductor 5, and comprises: a metal base 61, a coat of metal 62, and an insulation adhesion layer 63.This metal base 61 generally is laminar, this coat of metal 62 be plating on the surface of this metal base 61, this insulation adhesion layer 63 is to be incorporated on a side of this coat of metal 62, and with the assembly 52 on this semiconductor substrate 51, links together.This metal base 61 has a first surface 611 and a second surface in contrast to this first surface 611 612, and this coat of metal 62 is that plating is on the first surface 611 and second surface 612 of this metal base 61.
It is worth mentioning that, in the insulation-encapsulated device 6 of semiconductor 5 of the present invention, the material of this metal base 61 can be to be selected from copper, aluminium, iron, and stainless steel etc. one of them.The material of this coat of metal 62 is to be selected from nickel, chromium or these combination.The material of this insulation adhesion layer 63 is epoxy resin (epoxy), and epoxy resin is a kind of thermoset plastics, has simultaneously the functions such as adhesive, coating.
During practical application, due to this metal base 61 be by this insulation adhesion layer 63 directly and the assembly 52 of this semiconductor 5 mutually bind, so except improving because semiconductor prepares seam that volume-diminished causes, operate the problem that is difficult for, also can utilize this insulation adhesion layer 63 to avoid this semiconductor 5 to contact with this coat of metal 62 and produce interference or short circuit, and that the epoxy resin transferring heat by essence also is better than air is isolated, therefore has advantages of yield and the chip cooling effect that improves the encapsulation preparation.
And due to the diversity of semiconductor packages preparation, so in this first preferred embodiment, also can be as shown in Figure 3 with insulation adhesion layer 63 that epoxy resin was formed, be fill up this metal base 61 and 51 of this substrates gapped.Because this insulation adhesion layer 63 has insulation effect, can avoid exterior static to see through this insulation adhesion layer 63 and import, and affect the running of this assembly 52 through substrate 51, also can protect this assembly 52 and avoid being subject to the interference of external electromagnetic ripple.
Consult Fig. 4, be the second preferred embodiment of the insulation-encapsulated device 6 of semiconductor 5 of the present invention.This second preferred embodiment and this first preferred embodiment are roughly the same, something in common repeats no more in this, difference is, this metal base 61 has a body 613, and one be surrounded on these body 613 peripheries and extend downward this substrate 51 around section 614, and this assembly 52 is comprised of a plurality of electronic building bricks and passive component.
Because the conductive effect of this insulation adhesion layer 63 is poor, import except avoiding exterior static to see through this insulation adhesion layer 63, and affect the running of this electronic building brick 52 through substrate 51, be subject to so can reduce this electronic building brick 52 probability that extraneous static imports and generation is disturbed, also have the function of electromagnetic wave proof simultaneously.
Consult Fig. 5, Fig. 6, be the 3rd preferred embodiment of the insulation-encapsulated device 6 of semiconductor 5 of the present invention.The 3rd preferred embodiment and this first preferred embodiment are roughly the same, and something in common repeats no more in this, and difference is, in the 3rd preferred embodiment, this metal base 61 generally is an inverted U and is arranged on the substrate 51 of this semiconductor chip 5.
This metal base 61 have a body 613, be surrounded on these body 613 peripheries and extend downward this semiconductor substrate 51 around section 614, an and extension 616 that is connected with this semiconductor substrate 51, this body 613, around section 614, and this semiconductor substrate 51 defines an accommodation space 615 jointly, this extension 616 is be connected and stretch out with this bottom around section 614, and with this body 613, be arranged in parallel.This insulation adhesion layer 63 is to be arranged in this accommodation space 615 and to be arranged at this body 613 belows.
And due to the diversity of semiconductor packages preparation, so in the 3rd preferred embodiment, with the insulation adhesion layer 63 that epoxy resin was formed, can as shown in Figure 6, be also to fill up all spaces in this accommodation space 615.Because this insulation adhesion layer 63 has insulation effect, can avoid exterior static to see through the importing of this insulation adhesion layer 63, affect the running of this assembly 52 through substrate 51, also can protect this assembly 52 and avoid being subject to the interference of external electromagnetic ripple.
Consult Fig. 7, be the 4th preferred embodiment of the insulation-encapsulated device 6 of semiconductor 5 of the present invention.The 4th preferred embodiment and the 3rd preferred embodiment are roughly the same, and something in common repeats no more in this, and difference is, these insulation adhesion layer 23 coats of metal 62 be only plating on the second surface 612 of this metal base 61.There is no metal lining coating 62 on this first surface 611, use being applicable to this first surface 611 and needing the situation of other preparation, for example carry out black oxidation processes or the anode of copper, aluminum metal and process on this first surface 611.
Consult Fig. 8, Fig. 9, the first preferred embodiment for the manufacture method of the insulation-encapsulated device 6 of semiconductor 5 of the present invention, it is mainly the method for a plurality of preferred embodiments of above-mentioned this insulation-encapsulated device 6 of making in order to explanation, therefore, the structure that reaches described in this preferred embodiment, be a plurality of preferred embodiments of above-mentioned insulation-encapsulated device 6, therefore in this, no longer add to repeat.
At first, as shown in step 71, prepare a laminar metal base 61.Next, as shown in step 72, this coat of metal 62 of plating on this metal base 61.Because this coat of metal 62 is that plating is on this metal base 61, therefore can be as shown in Figure 9, the rough surface that produces while utilizing this coat of metal 62 of plating, increase contact area and the frictional force of 62 of this insulation adhesion layer 63 and this coats of metal, promote the adhesion of 62 of this insulation adhesion layer 63 and this coats of metal.
Consult Fig. 8, Figure 10, then, as shown in step 73, with these metal base 61 punch formings for generally being the shape of falling U, on the substrate 51 that can be covered in this semiconductor chip 5.Through after punching press, this metal base 61 have a body 613, be surrounded on these body 613 peripheries and extend downward this semiconductor substrate 51 around section 614, an and extension 616 that is connected with this semiconductor substrate 51.Finally, as shown in step 74, apply epoxy resin to form this insulation adhesion layer 63 on a wherein side of this coat of metal 62, and in the mode that adds hot pressing, this metal base 61 and the assembly 52 on this semiconductor substrate 51 are sticked together.Certainly, the first ~ the 4th preferred embodiment of the insulation-encapsulated device 6 of corresponding aforesaid semiconductor 5, whether this metal base 61 needs this around section 614 or this extension 616, can decide by punching press or the preparation of the progressive die, in this, no longer adds to repeat.
Via above explanation as can be known, in the process of semiconductor 5 encapsulation, because scolding tin is easier to be stained with the glutinous tin coating that is incorporated into homogeneous material, but epoxy resin and the tin coating material character of the adhesion layer 63 that should insulate are different, therefore can avoid scolding tin to be stained with glutinous puzzlement.Same reason, in encapsulation preparation, also have from outside encapsulating in semiconductor substrate on 51, and this metal base 61 is combined more closely with this semiconductor 5.
In addition,, because this insulation adhesion layer 63 has insulation effect, can avoid exterior static to see through this insulation adhesion layer 63 and import, and affect the running of this assembly 52 through this metal base 61, also have the function of electromagnetic wave proof simultaneously.Therefore, coordinate the effect of sticking together that this insulation adhesion layer 63 produces, not only can more easily with this semiconductor 5, directly bind, avoid welded encapsulation in conjunction with the problem that is difficult for, and then the stability while improving semiconductor 5 running, and strengthen radiating effect.
in sum, insulation-encapsulated device 6 and the manufacture method thereof of semiconductor 5 of the present invention, rough surface while utilizing this coat of metal 62 plating, can promote the adhesion of 63 of this coat of metal 62 and this insulation adhesion layers, coordinate 63 insulation that can produce of this insulation adhesion layer and stick together effect, so except improving because semiconductor prepares seam that volume-diminished causes, operate the problem that is difficult for, also can utilize this insulation adhesion layer 63 to avoid this semiconductor chip 5 to contact with this coat of metal 62 and produce interference or short circuit, and it is isolated also to be better than simple air by the epoxy resin transferring heat, therefore have advantages of also that the encapsulation of raising prepares yield and chip cooling effect, therefore really can reach purpose of the present invention.
Only as described above, it is only a plurality of preferred embodiment of the present invention, when not limiting scope of the invention process with this, the simple equivalence of namely generally according to the present patent application the scope of the claims and invention description content, doing changes and modifies, and all still remains within the scope of the patent.
The above, be only preferred embodiment of the present invention, not is used for limiting protection scope of the present invention.
Claims (10)
1. semi-conductive insulation-encapsulated device, this semiconductor has a substrate, and at least one semiconductor subassembly that is arranged on this substrate, and this semi-conductive insulation-encapsulated device is applicable to be covered on this semiconductor, and comprises:
One metal base, generally in the form of sheets;
One coat of metal, be arranged at the surface of this metal base; And
One insulation adhesion layer, be incorporated into a side of this coat of metal, and with the semiconductor subassembly on this semiconductor substrate, link together.
2. semi-conductive insulation-encapsulated device as claimed in claim 1, it is characterized in that, this metal base has a first surface and an opposite second surface, and this coat of metal is to be arranged on the second surface of this metal base, and the material of this coat of metal is to be selected from nickel, chromium or this combination.
3. semi-conductive insulation-encapsulated device as claimed in claim 2, is characterized in that, the material of this insulation adhesion layer is epoxy resin.
4. semi-conductive insulation-encapsulated device as claimed in claim 3, it is characterized in that, this metal base is arranged on this semiconductor substrate, generally be an inverted U, and has a body, and one be surrounded on this body periphery and extend downward this semiconductor substrate around section, this body, around section and this semiconductor substrate, jointly define an accommodation space, this insulation adhesion layer is be arranged in this accommodation space and be arranged at below this body.
5. semi-conductive insulation-encapsulated device as claimed in claim 4, is characterized in that, this metal base has more an extension that is connected with this semiconductor substrate, and this extension is be connected and stretch out with this bottom around section, and with this body, be arranged in parallel.
6. the manufacture method of a semi-conductive insulation-encapsulated device, this semiconductor has a substrate, and at least one semiconductor subassembly that is arranged on this substrate, and this semi-conductive insulation-encapsulated device is applicable to be covered on this semiconductor, and comprises the following step:
A) prepare a sheet metal base;
B) plating one coat of metal on this metal base; And
C) apply an insulation adhesion layer on this coat of metal, and with this semiconductor subassembly, stick together and be integrated.
7. the manufacture method of semi-conductive insulation-encapsulated device as claimed in claim 6, it is characterized in that, more comprise one between step B) and step C) between step D), with this metal base punch forming for generally being the shape of falling U, so that it is covered on this substrate, after this metal base punching press, be formed with a body, and one be surrounded on this body periphery and extend downward this semiconductor substrate around section, this body, around section, and this semiconductor substrate defines an accommodation space jointly.
8. the manufacture method of semi-conductive insulation-encapsulated device as claimed in claim 7, it is characterized in that, this step D) in, this metal base is after punching press, more be formed with an extension that is connected with this semiconductor substrate, this extension is be connected and stretch out with this bottom around section, and with this body, be arranged in parallel.
9. the manufacture method of semi-conductive insulation-encapsulated device as claimed in claim 6, is characterized in that this step C) be to apply epoxy resin to form this insulation adhesion layer on a side of this coat of metal, and be attached on this semi-conductive assembly.
10. the manufacture method of semi-conductive insulation-encapsulated device as claimed in claim 9, it is characterized in that, the material of metal base this steps A) is to be selected from copper, aluminium, iron, and stainless steel etc. one of them, and this step B) the coat of metal be to be selected from nickel, chromium or this combination.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210141573.7A CN103390596B (en) | 2012-05-09 | 2012-05-09 | The insulation-encapsulated device of quasiconductor and its manufacture method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210141573.7A CN103390596B (en) | 2012-05-09 | 2012-05-09 | The insulation-encapsulated device of quasiconductor and its manufacture method |
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| CN103390596A true CN103390596A (en) | 2013-11-13 |
| CN103390596B CN103390596B (en) | 2017-03-01 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449557A (en) * | 2015-08-12 | 2017-02-22 | 旭宏科技有限公司 | Semiconductor radiating fin device and packaging structure using radiating fin |
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|---|---|---|---|---|
| TW200501361A (en) * | 2003-06-18 | 2005-01-01 | Siliconware Precision Industries Co Ltd | Electrically insulating heat sink and semiconductor package with the heat sink |
| CN1663042A (en) * | 2002-07-17 | 2005-08-31 | 住友电气工业株式会社 | Member for semiconductor device |
| TW200620586A (en) * | 2004-12-09 | 2006-06-16 | Advanced Semiconductor Eng | Chip package structure |
| US20100052156A1 (en) * | 2008-08-27 | 2010-03-04 | Advanced Semiconductor Engineering, Inc. | Chip scale package structure and fabrication method thereof |
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2012
- 2012-05-09 CN CN201210141573.7A patent/CN103390596B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1663042A (en) * | 2002-07-17 | 2005-08-31 | 住友电气工业株式会社 | Member for semiconductor device |
| TW200501361A (en) * | 2003-06-18 | 2005-01-01 | Siliconware Precision Industries Co Ltd | Electrically insulating heat sink and semiconductor package with the heat sink |
| TW200620586A (en) * | 2004-12-09 | 2006-06-16 | Advanced Semiconductor Eng | Chip package structure |
| US20100052156A1 (en) * | 2008-08-27 | 2010-03-04 | Advanced Semiconductor Engineering, Inc. | Chip scale package structure and fabrication method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449557A (en) * | 2015-08-12 | 2017-02-22 | 旭宏科技有限公司 | Semiconductor radiating fin device and packaging structure using radiating fin |
| CN106449557B (en) * | 2015-08-12 | 2019-05-31 | 旭宏科技有限公司 | Semiconductor heat-dissipating sheet devices and the encapsulating structure for using the cooling fin |
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| CN103390596B (en) | 2017-03-01 |
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