CN103390596B - The insulation-encapsulated device of quasiconductor and its manufacture method - Google Patents
The insulation-encapsulated device of quasiconductor and its manufacture method Download PDFInfo
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- CN103390596B CN103390596B CN201210141573.7A CN201210141573A CN103390596B CN 103390596 B CN103390596 B CN 103390596B CN 201210141573 A CN201210141573 A CN 201210141573A CN 103390596 B CN103390596 B CN 103390596B
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Abstract
The invention discloses a kind of insulation-encapsulated device of quasiconductor, this quasiconductor has a substrate, and at least one is arranged at semiconductor subassembly on this substrate, and the insulation-encapsulated device of this quasiconductor is applied to and is covered on this quasiconductor, and comprise a metal base, a coat of metal, an and insulation adhesion layer.This metal base is general in the form of sheets, this coat of metal be plating on the surface of this metal base, this insulation adhesion layer is then incorporated into the side of this coat of metal and is arranged on this quasiconductor.
Description
Technical field
The invention relates to a kind of packaging system and its manufacture method, particularly relate to a kind of insulator seal for quasiconductor
Assembling device and its manufacture method.
Background technology
With quasiconductor preparation continuous advancement, existing semiconductor subassembly in addition to efficiency is gradually lifted, its volume
Also progressively reduce, but relative, and when also resulting in existing semiconductor subassembly running, produced heat is gradually increased, in order to be lifted
Radiating efficiency, to avoid semiconductor subassembly too high because of temperature, leads to efficiency to glide and even damages, therefore there has been semiconductor core
The presence of the fin of piece.
Refering to Fig. 1, general semiconductor chip 1, it is generally disposed on semiconductor substrate 10 and be coated with one thereon
Fin 2, is contacted with this semiconductor chip 1 using this fin 2, produced heat when this semiconductor chip 1 is operated
Source is conducted using the mode increasing area of dissipation, the problem excessive to alleviate semiconductor chip 1 heat.
It is well known that ground, with the progress of science and technology preparation, the volume of electronic product heal make less, related so that institute
The volume of the semiconductor chip 1 using is also more and more little, and the volume of the relative fin 2 causing this metal to make also heal by more contracting
Little, so, difficulty with this fin 2 in the scolding tin seam or chimeric operation of packaging operation for this semiconductor chip 1 can be caused.
Additionally, the volume more contracting with semiconductor chip 1 and this fin 2 is less, this semiconductor chip 1 and this fin also can be made
Gap H between 2 is more and more little, careless slightly (deflection of such as fin 2 is larger), will make the fin that metal is made
2 produce improper contact with this semiconductor chip 1 and short-circuit, or exterior static interference, lead to this semiconductor chip 1 to occur therefore
Barrier, therefore the yield of this semiconductor chip 1 encapsulation just reduces.
Therefore, how in the case of this fin 2 is with this semiconductor chip 1 gradually microminiaturization, still have highly stable
Property and can improve seam or the inconvenience of chimeric operation, improve the yield of semiconductor chip 1 encapsulation, good radiating can be kept simultaneously
Effect, becomes the target needing effort for related dealer badly.
Content of the invention
In view of this, the technical problem to be solved in the present invention is to provide one kind to apply convenience, stability height, and the effect that radiates
The really good insulation-encapsulated device for quasiconductor.
For solving above-mentioned technical problem, the technical scheme is that and be achieved in that：A kind of insulation-encapsulated of quasiconductor
Device, this quasiconductor has a substrate, and at least one is arranged at semiconductor subassembly on this substrate, the insulation-encapsulated of this quasiconductor
Device is applied to and is covered on this quasiconductor, and comprises：One metal base, a coat of metal, and an insulation adhesion layer.This metal
Base material is general in the form of sheets, and in the surface of this metal base, this insulation adhesion layer is incorporated into this coat of metal to this coat of metal plating
Side.
And another object of the present invention, that is, provide one kind apply conveniently, stability high, and excellent in heat dissipation effect for half
The manufacture method of the insulation-encapsulated device of conductor.
Then, the manufacture method of the insulation-encapsulated device of the present invention, comprises the steps of.First, prepare a metal base.
Then, plating one coat of metal on this metal base.Then, coating one insulation adhesion layer on this coat of metal, and stick together
On this semiconductor substrate.
The technique effect that the present invention reaches is as follows：Can be lifted and this insulation adhesion layer using the rough surface of this coat of metal
Between adhesion, coordinate the insulation that this insulation adhesion layer can be generated by and stick together effect, not only can directly stick with semiconductor subassembly
Close, it is to avoid the problem that seam operation is difficult, more can really avoid this semiconductor subassembly to contact with this coat of metal, and then improve
Stability and radiating effect.
Brief description
Fig. 1 is a cross-sectional schematic, illustrates to be currently used for the structure of the packaging system of quasiconductor；
Fig. 2 is a partial schematic sectional view, and the first preferred embodiment of the insulation-encapsulated device of quasiconductor of the present invention is described；
Fig. 3 is a partial schematic sectional view, and another enforcement structure of this first preferred embodiment is described；
Fig. 4 is a partial schematic sectional view, and the second preferred embodiment of the insulation-encapsulated device of quasiconductor of the present invention is described；
Fig. 5 is a partial schematic sectional view, and the 3rd preferred embodiment of the insulation-encapsulated device of quasiconductor of the present invention is described；
Fig. 6 is a partial schematic sectional view, and another enforcement structure of the 3rd preferred embodiment is described；
Fig. 7 is a partial schematic sectional view, and the 4th preferred embodiment of the insulation-encapsulated device of quasiconductor of the present invention is described；
Fig. 8 is a flow chart, illustrate quasiconductor 88 chip of the present invention the manufacture method of insulation-encapsulated device first relatively
Good embodiment；
Fig. 9 is a close-up schematic view, aids in illustrating the rough surface of a coat of metal；And
Figure 10 is a partial schematic sectional view, and aiding in illustrating a metal base punch forming is generally in U-shaped, so that its
Can be covered on the substrate of semiconductor chip.
Specific embodiment
For the present invention aforementioned and other technology contents, feature and effect, following cooperation with reference to schema multiple relatively
In the detailed description of good embodiment, can clearly present.
It is moreover observed that, before being described in detail, similar assembly is to be represented with being identically numbered.
Refering to Fig. 2, Fig. 3, it is the first preferred embodiment of the insulation-encapsulated device 6 of quasiconductor 5 of the present invention.This quasiconductor 5
There is a substrate 51, and at least one is arranged at the assembly 52 on this substrate 51.It should be noted that this assembly 52 can be quasiconductor
One of chip, electronic building brick or passive component etc., in this first preferred embodiment, this assembly 52 is semiconductor core
Piece.
The insulation-encapsulated device 6 of this quasiconductor 5 is applied to and is covered on this quasiconductor 5, and comprises：One metal base 61,
One coat of metal 62, and an insulation adhesion layer 63.This metal base 61 is in generally flake, and this coat of metal 62 is plating in this gold
Belong to base material 61 surface on, this insulation adhesion layer 63 is on the side be incorporated into this coat of metal 62, and with this semiconductor substrate
Assembly 52 on 51 links together.This metal base 61 has a first surface 611 and in contrast to this first surface 611
Second surface 612, this coat of metal 62 is plating on the first surface 611 and second surface 612 of this metal base 61.
It is noted that in the insulation-encapsulated device 6 of quasiconductor 5 of the present invention, the material of this metal base 61 is permissible
It is selected from one of copper, aluminum, ferrum, and rustless steel etc..The material of this coat of metal 62 is selected from nickel, chromium or these group
Close.The material of this insulation adhesion layer 63 is then epoxy resin (epoxy), and epoxy resin is a kind of thermosetting plastics, has simultaneously
There is adhesive, the function such as coating.
During practical application, because this metal base 61 is direct by this insulation adhesion layer 63 and this quasiconductor 5 assembly
52 mutually bind, so preparing, because of quasiconductor, the problem that seam operation caused by volume-diminished is difficult except improving, also can
Avoid this quasiconductor 5 to contact with this coat of metal 62 using this insulation adhesion layer 63 and produce interference or short circuit, and pass through reality
The epoxy resin transmission heat of matter, also superior to air exclusion, therefore has the yield improving encapsulation preparation and chip cooling effect
Advantage.
And the multiformity due to semiconductor packages preparation, so in this first preferred embodiment, being constituted with epoxy resin
Insulation adhesion layer 63 can also be as shown in figure 3, all gaps of being to fill up between this metal base 61 and this substrate 51.Due to this
Insulation adhesion layer 63 has insulation effect, exterior static can be avoided to pass through this insulation adhesion layer 63 and import, and through substrate 51
Affect the running of this assembly 52, this assembly 52 also can be protected to be protected from the interference of external electromagnetic ripple.
Refering to Fig. 4, it is the second preferred embodiment of the insulation-encapsulated device 6 of quasiconductor 5 of the present invention.This second is preferably implemented
Example is roughly the same with this first preferred embodiment, and something in common repeats no more in this, and difference is, this metal base 61 has
There is a body 613, and one is surrounded on this body 613 periphery and extends downward the cincture portion 614 of this substrate 51, and this group
Part 52 is made up of a plurality of electronic building bricks and passive component.
Because the conductive effect of this insulation adhesion layer 63 is poor, except exterior static can be avoided to pass through this insulation adhesion layer
63 importings, and affect the running of this electronic building brick 52 through substrate 51, it is subject to the external world quiet so this electronic building brick 52 can be reduced
Conductance enters and produces the probability of interference, also has the function of electromagnetic wave proof simultaneously.
Refering to Fig. 5, Fig. 6, it is the 3rd preferred embodiment of the insulation-encapsulated device 6 of quasiconductor 5 of the present invention.3rd is preferable
Embodiment is roughly the same with this first preferred embodiment, and something in common repeats no more in this, and difference is, the 3rd relatively
In good embodiment, this metal base 61 is in generally an inverted U and is arranged on the substrate 51 of this semiconductor chip 5.
This metal base 61 has a body 613, and is surrounded on this body 613 periphery and extends downward this and partly lead
The cincture portion 614 of structure base board 51, and an extension 616 being connected with this semiconductor substrate 51, this body 613, cincture portion
614, and this semiconductor substrate 51 defines an accommodation space 615 jointly, this extension 616 is the bottom with this cincture portion 614
Connect and stretch out, and be arranged in parallel with this body 613.This insulation adhesion layer 63 is in this accommodation space 615 simultaneously
It is arranged at below this body 613.
And the multiformity due to semiconductor packages preparation, so in the 3rd preferred embodiment, being constituted with epoxy resin
Insulation adhesion layer 63 can also be as shown in fig. 6, being to fill up all of space in this accommodation space 615.Because this insulation is sticked together
Layer 63 has insulation effect, exterior static can be avoided to pass through the importing of this insulation adhesion layer 63, affect this group through substrate 51
The running of part 52, also can protect this assembly 52 to be protected from the interference of external electromagnetic ripple.
Refering to Fig. 7, it is the 4th preferred embodiment of the insulation-encapsulated device 6 of quasiconductor 5 of the present invention.4th preferably implements
Example is roughly the same with the 3rd preferred embodiment, and something in common repeats no more in this, and difference is, this insulation adhesion layer 23
The coat of metal 62 is only plating on the second surface 612 of this metal base 61.This first surface 611 has no metal lining
Coating 62, uses and is applied to this first surface 611 and needs the situations of other preparations, for example carry out on this first surface 611 copper,
The black oxidation processes of aluminum metal or anodising.
Refering to Fig. 8, Fig. 9, it is the first preferred embodiment of the manufacture method of insulation-encapsulated device 6 of quasiconductor 5 of the present invention,
Method mainly in order to the multiple preferred embodiments manufacturing this insulation-encapsulated device 6 above-mentioned to be described, therefore, this preferred embodiment
Described in and structure, multiple preferred embodiments of as above-mentioned insulation-encapsulated device 6, therefore no longer add to repeat in this.
First, as shown in step 71, prepare a laminar metal base 61.Next, as shown in step 72, in this gold
Belong to this coat of metal 62 of plating on base material 61.Due to this coat of metal 62 be plating on this metal base 61, therefore can be as
Shown in Fig. 9, using produced rough surface during this coat of metal 62 of plating, increase this insulation adhesion layer 63 and this coat of metal
Contact area between 62 and frictional force, lift the adhesion between this insulation adhesion layer 63 and this coat of metal 62.
Refering to Fig. 8, Figure 10, then, as shown in step 73, this metal base 61 punch forming is generally in U-shaped, so that
It can be covered on the substrate 51 of this semiconductor chip 5.After punching press, this metal base 61 has a body 613,
It is surrounded on this body 613 periphery and extend downward the cincture portion 614 of this semiconductor substrate 51, and one and this semiconductor substrate
The extension 616 of 51 connections.Finally, as shown in step 74, on the wherein side of this coat of metal 62 coating epoxy resin with
Form this insulation adhesion layer 63, and by the assembly 52 on this metal base 61 and this semiconductor substrate 51 in the way of heating pressing
Stick together.Certainly, the first ~ the 4th preferred embodiment of the insulation-encapsulated device 6 of corresponding aforesaid semiconductor 5, this Metal Substrate
Material 61, the need of this cincture portion 614 or this extension 616, can be determined by punching press or the preparation of the progressive die, in this
No longer add to repeat.
Understand via described above, during quasiconductor 5 encapsulation, cohere together in same material because scolding tin is easier to be stained with
The tin coating of material, but the epoxy resin of this insulation adhesion layer 63 is different with tin coating material character, and scolding tin therefore can be avoided to be stained with
Glutinous puzzlement.Same reason, in encapsulation preparation, also has from outside encapsulating in semiconductor substrate 51, makes this Metal Substrate
Material 61 is more closely combined together with this quasiconductor 5.
Further, since this insulation adhesion layer 63 has insulation effect, exterior static can be avoided to pass through this insulation adhesion layer 63
Import, and affect the running of this assembly 52 through this metal base 61, also there is the function of electromagnetic wave proof simultaneously.Therefore,
Coordinate and stick together effect produced by this insulation adhesion layer 63, not only can more easily directly bind with this quasiconductor 5, it is to avoid encapsulation
The problem that solder bond is difficult, and then improve stability during quasiconductor 5 running, with reinforcement radiating effect.
In sum, the insulation-encapsulated device 6 of quasiconductor 5 of the present invention and its manufacture method, is plated using this coat of metal 62
Rough surface when covering, can lift the adhesion between this coat of metal 62 and this insulation adhesion layer 63, coordinate this insulation adhesion layer
63 insulation that can be generated by with stick together effect, so except can improve because quasiconductor preparation volume-diminished caused by seam operation
The problem being difficult, also can be avoided this semiconductor chip 5 to be contacted with this coat of metal 62 using this insulation adhesion layer 63 and produce
Interference or short circuit, and by epoxy resin transmission heat also superior to simple air exclusion, therefore also there is raising encapsulation preparation
Yield and the advantage of chip cooling effect, therefore really can reach the purpose of the present invention.
Only as described above, only multiple preferred embodiments of the present invention, when can not with this limit the present invention implement
Scope, the simple equivalence changes generally made according to scope of the present invention patent and invention description content and modification, all
Still remain within the scope of the patent.
The above, only presently preferred embodiments of the present invention, it is not intended to limit protection scope of the present invention.
Claims (7)
1. the insulation-encapsulated device of a kind of quasiconductor, this quasiconductor has a substrate, and at least one is arranged on this substrate half
Conductor assembly, the insulation-encapsulated device of this quasiconductor is applied to and is covered on this quasiconductor, and comprises：
One metal base, is lamellar, and has a first surface and a contrary second surface, and this second surface is this Metal Substrate
The bottom surface of material；
One coat of metal, is arranged on the second surface of this metal base, and the material of this coat of metal is selected from nickel, chromium or two
The combination of person；And
One insulation adhesion layer, is incorporated into the side of this coat of metal, and is connected to the semiconductor subassembly on this semiconductor substrate
Together, the material of this insulation adhesion layer is epoxy resin, and this insulation adhesion layer is directly formed on this coat of metal.
2. the insulation-encapsulated device of quasiconductor as claimed in claim 1 is it is characterised in that this metal base is arranged at this quasiconductor
On substrate, it is an inverted U, and there is a body, and one is surrounded on this body periphery and to extend downward this semiconductor-based
The cincture portion of plate, this body, cincture portion and this semiconductor substrate define an accommodation space jointly, and this insulation adhesion layer is position
In this accommodation space and be arranged at below this body.
3. the insulation-encapsulated device of quasiconductor as claimed in claim 2 is it is characterised in that this metal base has more one and is somebody's turn to do half
The extension of conductor substrate connection, this extension is to be connected with the bottom in this cincture portion and stretch out, and puts down with this body
Row setting.
4. the manufacture method of the insulation-encapsulated device of a kind of quasiconductor, this quasiconductor has a substrate, and at least one is arranged at this
Semiconductor subassembly on substrate, the insulation-encapsulated device of this quasiconductor is applied to and is covered on this quasiconductor, and comprises following step
Suddenly：
A) prepare a sheet-shaped metal substrate, this metal base has a first surface and a contrary second surface, this second table
Face is the bottom surface of this metal base；
B) plating one coat of metal on the second surface of this metal base, this coat of metal is selected from nickel, chromium or both groups
Close；And
C) epoxy resin is coated on this coat of metal and forms an insulation adhesion layer, and stick together for one with this semiconductor subassembly
Body.
5. the manufacture method of the insulation-encapsulated device of quasiconductor as claimed in claim 4 is it is characterised in that further include one between step
Rapid B) with step C) between step D), this metal base punch forming is U-shaped so that it is covered on this substrate, this gold
After belonging to base material punching press, it is formed with a body, and one is surrounded on this body periphery and extends downward this semiconductor substrate
Cincture portion, this body, cincture portion, and this semiconductor substrate define an accommodation space jointly.
6. the manufacture method of the insulation-encapsulated device of quasiconductor as claimed in claim 5 is it is characterised in that this step D) in this gold
After genus base material is stamped, more it is formed with an extension being connected with this semiconductor substrate, this extension is and this cincture portion
Bottom connects and stretches out, and be arranged in parallel with this body.
7. the manufacture method of the insulation-encapsulated device of quasiconductor as claimed in claim 6 is it is characterised in that this step A) metal
The material of base material is selected from one of copper, aluminum, ferrum, and rustless steel.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210141573.7A CN103390596B (en) | 2012-05-09 | 2012-05-09 | The insulation-encapsulated device of quasiconductor and its manufacture method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210141573.7A CN103390596B (en) | 2012-05-09 | 2012-05-09 | The insulation-encapsulated device of quasiconductor and its manufacture method |
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| CN103390596A CN103390596A (en) | 2013-11-13 |
| CN103390596B true CN103390596B (en) | 2017-03-01 |
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| CN106449557B (en) * | 2015-08-12 | 2019-05-31 | 旭宏科技有限公司 | Semiconductor heat-dissipating sheet devices and the encapsulating structure for using the cooling fin |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200501361A (en) * | 2003-06-18 | 2005-01-01 | Siliconware Precision Industries Co Ltd | Electrically insulating heat sink and semiconductor package with the heat sink |
| CN1663042A (en) * | 2002-07-17 | 2005-08-31 | 住友电气工业株式会社 | Member for semiconductor device |
| TW200620586A (en) * | 2004-12-09 | 2006-06-16 | Advanced Semiconductor Eng | Chip package structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100052156A1 (en) * | 2008-08-27 | 2010-03-04 | Advanced Semiconductor Engineering, Inc. | Chip scale package structure and fabrication method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1663042A (en) * | 2002-07-17 | 2005-08-31 | 住友电气工业株式会社 | Member for semiconductor device |
| TW200501361A (en) * | 2003-06-18 | 2005-01-01 | Siliconware Precision Industries Co Ltd | Electrically insulating heat sink and semiconductor package with the heat sink |
| TW200620586A (en) * | 2004-12-09 | 2006-06-16 | Advanced Semiconductor Eng | Chip package structure |
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