CN103367453A - Ultrathin transverse double diffusion metal-oxide semiconductor field-effect transistor and preparing method thereof - Google Patents
Ultrathin transverse double diffusion metal-oxide semiconductor field-effect transistor and preparing method thereof Download PDFInfo
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- CN103367453A CN103367453A CN2013103017090A CN201310301709A CN103367453A CN 103367453 A CN103367453 A CN 103367453A CN 2013103017090 A CN2013103017090 A CN 2013103017090A CN 201310301709 A CN201310301709 A CN 201310301709A CN 103367453 A CN103367453 A CN 103367453A
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Abstract
The invention discloses an ultrathin transverse double diffusion metal-oxide semiconductor field-effect transistor which comprises a P-type substrate. An oxide buried layer is arranged on the P-type substrate, an N-type well region and a P-type well region are arranged on the oxide buried layer, an N-type buffering region is arranged inside the N-type well region, a field oxide is arranged on the N-type well region, an N-type draining region is arranged inside the N-type buffering region, and a P-type contact region and an N-type source region are arranged inside the P-type well region. A P-type well region array composed of P-type well region units is arranged below the field oxide, and is located between the N-type buffering region and the P-type well region. The width of each P-type well region unit gradually becomes large from the N-type buffering region to the P-type well region. The capability for resisting the high-voltage parasitic effect of the ultrathin transverse double diffusion metal-oxide semiconductor field-effect transistor in an electrical level shift circuit is greatly enhanced, and the performance of an intelligent power module can be greatly improved. The invention further discloses a method for preparing the ultrathin transverse double diffusion metal-oxide semiconductor field-effect transistor.
Description
Technical field
The present invention relates to power semiconductor, particularly relate to a kind of ultra-thin lateral double diffusion metal oxide semiconductor field effect transistor that is used in the level shift circuit.
Background technology
Intelligent Power Module in the high-voltage power integrated circuit can be used for various fields, as driving and control various industry and civilian, single-phase and three phase electric machine.And the level shift circuit in the Intelligent Power Module becomes the key component of whole Intelligent Power Module for high-voltage output circuit provides output voltage, has a withstand voltage as the LDMOS of the switch element in the level shift circuit high, the advantages such as drive circuit is simple, and switching speed is fast.Just because of this, these years, LDMOS is applied in the power integrated circuit frequently.But, when LDMOS is applied in the level shift circuit, the drain electrode of LDMOS need to be drawn interconnection line and be provided output voltage for high-voltage output circuit, certainly will will be by the drift region of LDMOS in the process of drawing with this part interconnection line of high-voltage signal, the electric field that forms around the high pressure interconnection line, to have a strong impact on the distribution of electromotive force in the drift region, and then so that the puncture voltage of LDMOS reduces greatly, finally cause level shift circuit to lose function.The ability that how to strengthen the anti-high pressure interconnection line impact of LDMOS in the level shift circuit becomes the key that improves whole performance of integrated circuits.So be undoubtedly the important content of Intelligent power module circuit and technique as the research to the anti-high pressure interconnection line of the ultra-thin LDMOS capability of influence in the power switch component.
The most effective and the outstanding isolation structure for lateral high-voltage device in the bulk silicon technological of mentioning in the US Patent No. 5894156 of Mitsubishi among the whole bag of tricks of existing solution LDMOS drain terminal high pressure interconnection line impact, LDMOS is embedded in the isolation structure, and the metal connecting line that the LDMOS drain terminal is drawn and the high basin of whole isolation structure terminate at one, and finally drawn by high basin end, avoid the high pressure interconnection line directly from top, LDMOS drift region process, affected the distribution of electromotive force in the drift region.But, for the level shift circuit of realizing under the ultrathin membrane technique platform, its isolation structure adopts the isolation of the LOCOS method of mentioning among the US Patent No. 7510927B2, the isolation structure that this isolation technology is compared under the bulk silicon technological has reduced area greatly, therefore, because the isolation structure that both adopt is different, the method for about how the high pressure interconnection line being drawn among the US5894156 is impracticable under ultra-thin technique platform.
Summary of the invention
The invention provides silicon LDMOS on a kind of ultrathin insulating body of anti-high pressure interconnection line impact, the invention solves the problem of the high pressure ghost effect that level shift circuit mesohigh interconnection line brings, drawing the drain metal line success of LDMOS under the condition of not sacrificing puncture voltage.
The present invention adopts following technical scheme:
A kind of ultra-thin lateral double diffusion metal oxide semiconductor field effect transistor, comprise: P type substrate, be provided with oxygen buried layer at P type substrate, be provided with N-type well region and P type well region at oxygen buried layer, in the N-type well region, be provided with the N-type buffering area, in the N-type buffering area, be provided with the N-type drain region, in P type well region, be provided with P type contact zone and N-type source region, be provided with field oxide at the N-type well region, and, border in N-type drain region and a borderline phase of field oxide support, the borderline region surface adjacent with the N-type source region at field oxide is provided with polysilicon gate, and polysilicon gate extends to the top in N-type source region towards N-type source region direction from the border of field oxide, below the elongated area of polysilicon gate, be provided with gate oxide, at field oxide, polysilicon gate, P type well region, P type contact zone, the N-type source region, N-type buffering area and N-type drain region are provided with the medium isolating oxide layer, in P type contact zone, connect the source metal line on the N-type source region, connect the drain metal line in the N-type drain region, connect the gate metal line at polysilicon gate, it is characterized in that, below field oxide, be provided with the P type well region array by P type well region cell formation, described P type well region array is between N-type buffering area and P type well region, and the width of P type well region unit increases to P type well region gradually from the N-type buffering area.
The preparation method of described a kind of ultra-thin lateral double diffusion metal oxide semiconductor field effect transistor is as follows:
The first step: prepare P type silicon substrate,
Second step: the deposit oxygen buried layer, carry out again the growth of extension, Implantation phosphorus generates the N-type well region, and Implantation arsenic and phosphorus form the N-type buffering area, annealing,
The 3rd step: the deposit photoresist, to prepare window size and begin ascending mask plate from the N-type buffering area, photoetching, boron ion implantation generate P type well region unit, annealing,
The 4th step: deposit silicon nitride, photoetching are formed with the source region, etch silicon nitride, then carry out the growth of an oxygen, and carry out the field and annotate, the Implantation boron fluoride changes channel doping concentration and adjusts channel threshold voltage, and a layer thickness of then growing is 500 gate oxide, and the deposit etch polysilicon forms polysilicon gate and polysilicon field plate, boron ion implantation forms P type well region
The 5th step: photoetching, Implantation phosphorus and arsenic generate N-type source region and N-type drain region, and photoetching, Implantation boron fluoride generate P type contact zone,
The 6th step: deposit medium isolating oxide layer, contact hole etching, depositing metal aluminium, etching aluminium is to form drain metal line and drain metal line directly over P type well region array, etching aluminium carries out the medium Passivation Treatment at last to form source metal line and gate metal line.
In the method for the invention, the thickness of the photoresist of deposit is 1.2 μ m in the 3rd step, and the Implantation Energy of boron ion is 50kev, and the implantation dosage of boron ion is 8e12cm
-2
Compared with prior art, the present invention has following advantage:
(1) a kind of ultra-thin lateral double diffusion metal oxide semiconductor field effect transistor of the present invention has adopted new construction (Fig. 1), namely under the drain metal line, the below of field oxide is provided with the P type well region array by P type well region cell formation, described P type well region array is between N-type buffering area and P type well region, and the width of P type well region unit increases to P type well region gradually from the N-type buffering area.With respect to traditional lateral double diffusion metal oxide semiconductor field effect transistor (Fig. 2) that does not have P type well region array structure, the present invention has realized under the level shift circuit normal running conditions, on the drain metal line, pass through high-voltage signal, this high-voltage signal is identical with the voltage swing that is added in LDMOS N-type drain region, but along with LDMOS from the N-type drain region to the N-type source region with current potential reduce gradually, to form electrical potential difference between high pressure interconnection line and the N-type well region and produce electric field, formed electric field strengthens to the N-type source region gradually from the N-type drain region, so need to be from the N-type drain region to the P type well region unit that N-type source region width increases gradually, stop this electric field on the impact (with reference to Fig. 8) of electron distributions situation in the N-type well region, so that the N-type well region can exhaust with P type well region fully mutually, finally avoided the reduction (with reference to Fig. 9) of puncture voltage.
(2) a kind of ultra-thin lateral double diffusion metal oxide semiconductor field effect transistor of the present invention, because P type well region array has stoped the impact of high pressure interconnection line on N-type well region electron distributions, add and adopt the LOCOS isolation structure that LDMOS is isolated (Fig. 7) with high-pressure area and area of low pressure, the tradition isolation has reduced area greatly because the LOCOS isolation is compared, can under the condition of not sacrificing puncture voltage, well the high pressure interconnection line be drawn again simultaneously, therefore, realized greatly having improved puncture voltage than traditional structure under the equal area condition.
(3) a kind of ultra-thin lateral double diffusion metal oxide semiconductor field effect transistor of the present invention, the concentration of described P type well region unit can adopt from the N-type buffering area and increase gradually to P type well region, because the closer to the N-type source region, the electrical potential difference that forms between high pressure interconnection line and the N-type well region is larger, therefore, need the P type well region unit of high concentration to shield high electric field to the impact of electron distributions situation in the N-type well region.
(4) a kind of ultra-thin lateral double diffusion metal oxide semiconductor field effect transistor of the present invention based on silicon LDMOS technique on the horizontal ultrathin insulating body of existing preparation, does not increase extra processing step fully, and preparation is simple.
Description of drawings
Fig. 1 is a kind of ultra-thin lateral double diffusion metal oxide semiconductor field effect transistor schematic diagram of the present invention;
Fig. 2 is traditional ultra-thin lateral double diffusion metal oxide semiconductor field effect transistor schematic diagram;
Fig. 3 is the transverse cross-sectional view along the I-I ' line of Fig. 1;
Fig. 4 is the transverse cross-sectional view along the II-II ' line of Fig. 1;
Fig. 5 is the transverse cross-sectional view along the I-I ' line of Fig. 2;
Fig. 6 is the transverse cross-sectional view along the II-II ' line of Fig. 2;
Fig. 7 is a kind of ultra-thin lateral double diffusion metal oxide semiconductor field effect transistor of the present invention and its isolation structure schematic diagram;
Fig. 8 is the puncture voltage comparison diagram of a kind of ultra-thin lateral double diffusion metal oxide semiconductor field effect transistor of the present invention when adopting after the different P of formation type well regions unit mode on the high pressure interconnection line with high-voltage signal;
Fig. 9 is a kind of ultra-thin lateral double diffusion metal oxide semiconductor field effect transistor of the present invention and the traditional ultra-thin lateral double diffusion metal oxide semiconductor field effect transistor puncture voltage comparison diagram during with high-voltage signal on the high pressure interconnection line;
Figure 10 is the puncture voltage comparison diagram after a kind of ultra-thin lateral double diffusion metal oxide semiconductor field effect transistor P type well region of the present invention unit junction depth changes;
Figure 11 is the puncture voltage comparison diagram after a kind of ultra-thin lateral double diffusion metal oxide semiconductor field effect transistor P type well region unit concentration of the present invention changes;
Figure 12 is the preparation flow figure of a kind of ultra-thin lateral double diffusion metal oxide semiconductor field effect transistor of the present invention;
Embodiment
With reference to Fig. 1,2,3, a kind of ultra-thin lateral double diffusion metal oxide semiconductor field effect transistor, comprise: P type substrate 1, be provided with oxygen buried layer 2 at P type substrate 1, be provided with N-type well region 4 and P type well region 6a at oxygen buried layer 2, in N-type well region 4, be provided with N-type buffering area 5, in N-type buffering area 5, be provided with N-type drain region 9, in P type well region 6a, be provided with P type contact zone 7 and N-type source region 8, be provided with field oxide 11 at N-type well region 4, and, border in N-type drain region 9 and a borderline phase of field oxide 11 support, the borderline region surface adjacent with N-type source region 8 at field oxide 11 is provided with polysilicon gate 12, and polysilicon gate 12 extends to the top in N-type source region 8 towards N-type source region 8 directions from the border of field oxide 11, below the elongated area of polysilicon gate 12, be provided with gate oxide 10, at field oxide 11, polysilicon gate 12, P type well region 6a, P type contact zone 7, N-type source region 8, N-type buffering area 5 and N-type drain region 9 are provided with medium isolating oxide layer 13, in P type contact zone 7, connect source metal line 14 on the N- type source region 8,9 connect drain metal line 15 in the N-type drain region, connect gate metal line 16 at polysilicon gate 12, it is characterized in that, below field oxide 11, be provided with the P type well region array 17 that is consisted of by P type well region unit 6b, described P type well region array 17 is between N-type buffering area 5 and P type well region 6a, and the width of P type well region unit 6b increases gradually from N-type buffering area 5 to P type well region 6a.
P type well region array 17 can adopt the single file multiple row, in the present embodiment, it is P type well region arrays of 1 that the P type well region array 17 that is made of P type well region unit 6b adopts line numbers, and columns is greater than 1 row, both can be 3 row, 4 row or more, as long as can optimize the electric field of high pressure interconnection line below.
The present embodiment can also adopt following technical measures further to improve puncture voltage:
(1) width of the P type well region unit (6b) in the P type well region array (17) can increase to N-type source region (8) gradually from N-type drain region (9), and the width of P type well region unit (6b) has an optimal value, this is because the electric field between high pressure interconnection line and the N-type well region (4) is strengthened to N-type source region (8) gradually by N-type drain region (9), this just require get over the closer to the place in N-type source region the wider P type well region unit (6b) of needs hinder highfield on the drift region in the impact of electron distributions.
(2) P type well region unit (6b) junction depth in the P type well region array (17) has an optimal value, thinner P type well region unit (6b) can not hinder the highfield of drain metal line formation on every side to the impact of drift region electron distributions, and darker P type well region unit (6b) can take excessive drift region area, so that the drift region area that participates in exhausting diminishes and causes withstand voltage reduction, with reference to Figure 10, the puncture voltage comparison diagram after P type well region unit (6b) junction depth changes.In like manner, the concentration of P type well region unit (6b) equally also has individual optimal value, and concentration is excessively light, can not effectively isolate electric field, and the concentration overrich affects the raising of device withstand voltage, with reference to Figure 11, and the puncture voltage comparison diagram after P type well region unit (6b) change in concentration.
With reference to Figure 12, the preparation method of a kind of ultra-thin lateral double diffusion metal oxide semiconductor field effect transistor among the present invention is described in detail:
The first step: prepare P type silicon substrate 1,
Second step: deposit a layer thickness is the oxygen buried layer 2 of 3 μ m, carry out the growth 3 of extension, generating a layer thickness is the epitaxial loayer of 1.5 μ m, the deposit photoresist again, the mask plate etching photoresist that preparation increases to the drain region window gradually from the source region, ion implantation dosage is 9e12cm
-2Phosphorus generate N-type well region 4, remove photoresist, the deposit photoresist, photoetching, ion implantation dosage is 5e13cm
-2Arsenic and phosphorus form N-type resilient coating 5, remove photoresist, annealing,
The 3rd step: deposit a layer thickness is the photoresist of 1.2 μ m, prepares window size and begins ascending mask plate from the N-type buffering area, according to window size etching photoresist, take the energetic ion implantation dosage of 50keV as 8e12cm
-2The boron ion generate P type well region unit 6b, remove photoresist, anneal under the high temperature,
The 4th step: deposit silicon nitride, photoetching are formed with the source region, etch silicon nitride, then carry out the growth of an oxygen, and carry out the field and annotate, the Implantation boron fluoride changes channel doping concentration and adjusts channel threshold voltage, then a layer thickness of growing is 500 gate oxide 10, and the deposit etch polysilicon forms polysilicon gate and polysilicon field plate, and ion implantation dosage is 1.2e13cm
-2Boron form P type well region 6a,
The 5th step: the deposit photoresist, photoetching, ion implantation dosage is 4.2e15cm
-2Phosphorus and arsenic generate N-type source region 8 and N-type drain region 9, photoetching, ion implantation dosage are 2.5e15cm
-2Boron fluoride generate P type contact zone 7, remove photoresist,
The 6th step: deposit medium isolating oxide layer 13, contact hole etching, depositing metal aluminium, the deposit photoresist, photoetching, etching aluminium is to form drain metal line 15 and drain metal line directly over P type well region array 17, and etching aluminium is to form source metal line 14 and gate metal line 16, remove photoresist, carry out at last the medium Passivation Treatment.
Claims (5)
1. ultra-thin lateral double diffusion metal oxide semiconductor field effect transistor, comprise: P type substrate (1), be provided with oxygen buried layer (2) at P type substrate (1), be provided with N-type well region (4) and P type well region (6a) at oxygen buried layer (2), in N-type well region (4), be provided with N-type buffering area (5), in N-type buffering area (5), be provided with N-type drain region (9), in P type well region (6a), be provided with P type contact zone (7) and N-type source region (8), be provided with field oxide (11) at N-type well region (4), and, border in N-type drain region (9) and a borderline phase of field oxide (11) support, the borderline region surface adjacent with N-type source region (8) at field oxide (11) is provided with polysilicon gate (12), and polysilicon gate (12) extends to the top of N-type source region (8) towards N-type source region (8) direction from the border of field oxide (11), below, elongated area at polysilicon gate (12) is provided with gate oxide (10), in field oxide (11), polysilicon gate (12), P type well region (6a), P type contact zone (7), N-type source region (8), N-type buffering area (5) and N-type drain region (9) are provided with medium isolating oxide layer (13), in P type contact zone (7), the upper source metal line (14) that connects in N-type source region (8), connect drain metal line (15) in N-type drain region (9), connect gate metal line (16) at polysilicon gate (12), it is characterized in that, be provided with the P type well region array (17) that is consisted of by P type well region unit (6b) in field oxide (11) below, described P type well region array (17) is positioned between N-type buffering area (5) and the P type well region (6a), and the width of P type well region unit (6b) increases to P type well region (6a) gradually from N-type buffering area (5).
2. a kind of ultra-thin lateral double diffusion metal oxide semiconductor field effect transistor according to claim 1 is characterized in that, the junction depth of P type well region unit (6b) is in 0.5 μ m.
3. a kind of ultra-thin lateral double diffusion metal oxide semiconductor field effect transistor according to claim 1 is characterized in that, by the P type well region array (17) of P type well region unit (6b) formation, under drain metal line (15).
4. the preparation method of an a kind of ultra-thin lateral double diffusion metal oxide semiconductor field effect transistor claimed in claim 1 is characterized in that, may further comprise the steps:
The first step: prepare P type silicon substrate (1),
Second step: deposit oxygen buried layer (2), carry out again the growth (3) of extension, Implantation phosphorus generates N-type well region (4), and Implantation arsenic and phosphorus form N-type buffering area (5), annealing,
The 3rd step: the deposit photoresist, to prepare window size and begin ascending mask plate from the N-type buffering area, photoetching, boron ion implantation generate P type well region unit (6b), annealing,
The 4th step: deposit silicon nitride, photoetching are formed with the source region, etch silicon nitride, then carry out the growth of an oxygen, and carry out the field and annotate, the Implantation boron fluoride changes channel doping concentration and adjusts channel threshold voltage, and a layer thickness of then growing is 500 gate oxide (10), and the deposit etch polysilicon forms polysilicon gate and polysilicon field plate, boron ion implantation forms P type well region (6a)
The 5th step: photoetching, Implantation phosphorus and arsenic generate N-type source region (8) and N-type drain region (9), and photoetching, Implantation boron fluoride generate P type contact zone (7),
The 6th step: deposit medium isolating oxide layer (13), contact hole etching, depositing metal aluminium, etching aluminium is to form drain metal line (15) and drain metal line directly over P type well region array (17), etching aluminium carries out the medium Passivation Treatment at last to form source metal line (14) and gate metal line (16).
5. preparation method according to claim 4 is characterized in that, the thickness of the photoresist of deposit is 1.2 μ m in the 3rd step, and the Implantation Energy of boron ion is 50kev, and the implantation dosage of boron ion is 8e12cm
-2
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| US20020125530A1 (en) * | 2001-03-07 | 2002-09-12 | Semiconductor Components Industries, Llc. | High voltage metal oxide device with multiple p-regions |
| US6773997B2 (en) * | 2001-07-31 | 2004-08-10 | Semiconductor Components Industries, L.L.C. | Method for manufacturing a high voltage MOSFET semiconductor device with enhanced charge controllability |
| US7655978B2 (en) * | 2007-11-27 | 2010-02-02 | Vanguard International Semiconductor Corporation | Semiconductor structure |
| CN102097480A (en) * | 2010-12-22 | 2011-06-15 | 东南大学 | N-type super-junction transverse double-diffusion metal oxide semiconductor tube |
| CN102832232A (en) * | 2012-08-14 | 2012-12-19 | 东南大学 | Silicon-controlled rectifier lateral double diffused metal oxide semiconductor with high maintaining voltage |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020125530A1 (en) * | 2001-03-07 | 2002-09-12 | Semiconductor Components Industries, Llc. | High voltage metal oxide device with multiple p-regions |
| US6773997B2 (en) * | 2001-07-31 | 2004-08-10 | Semiconductor Components Industries, L.L.C. | Method for manufacturing a high voltage MOSFET semiconductor device with enhanced charge controllability |
| US7655978B2 (en) * | 2007-11-27 | 2010-02-02 | Vanguard International Semiconductor Corporation | Semiconductor structure |
| CN102097480A (en) * | 2010-12-22 | 2011-06-15 | 东南大学 | N-type super-junction transverse double-diffusion metal oxide semiconductor tube |
| CN102832232A (en) * | 2012-08-14 | 2012-12-19 | 东南大学 | Silicon-controlled rectifier lateral double diffused metal oxide semiconductor with high maintaining voltage |
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