CN103367440A - 用于FinFET器件的鳍结构 - Google Patents

用于FinFET器件的鳍结构 Download PDF

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CN103367440A
CN103367440A CN2012103624101A CN201210362410A CN103367440A CN 103367440 A CN103367440 A CN 103367440A CN 2012103624101 A CN2012103624101 A CN 2012103624101A CN 201210362410 A CN201210362410 A CN 201210362410A CN 103367440 A CN103367440 A CN 103367440A
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conducting material
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CN103367440B (zh
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乔治斯·威廉提斯
马克·范·达尔
布兰丁·迪里耶
查理德·奥克斯兰德
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

提供一种用于鳍式场效应晶体管(FinFET)器件的鳍结构。器件包括：衬底、设置在衬底上的第一半导体材料、设置在衬底上方并且形成在第一半导体材料的相对两侧的浅沟槽隔离(STI)区、以及形成在STI区上设置的第一鳍和第二鳍的第二半导体材料，第一鳍与第二鳍间隔第一半导体材料的宽度。鳍结构可以用于通过形成在第一鳍、在第一鳍和第二鳍之间设置的第一半导体材料的顶面、以及第二鳍上方形成的栅极层来生成FinFET器件。

Description

用于FinFET器件的鳍结构
技术领域
本发明一般地涉及半导体技术领域，更具体地来说，涉及FinFET器件。
背景技术
半导体器件在大量电子器件中使用，诸如，计算机、蜂窝电话等。半导体器件包括集成电路，通过在半导体晶圆上方沉积多种类型的薄膜材料，并且图案化薄膜材料以形成集成电路在半导体晶圆上形成集成电路。集成电路包括场效应晶体管(FET)，诸如，金属氧化物半导体(MOS)晶体管。
半导体工业的目标之一是继续减小独立FET的尺寸并且提高独立FET的速度。为了实现这些目标，将在先进的晶体管节点中使用鳍式FET(FinFET)或多个栅极晶体管。例如，FinFET不仅改进了面密度而且改进了沟道的栅极控制。
在提高性能和减少互补金属氧化物半导体(CMOS)和MOSFET器件的功耗的努力中，半导体工业采用高迁移率半导体以代替作为晶体管沟道的硅。例如，半导体工业还通过绝缘体上硅(SOI)和异质结构器件促进衬底隔离技术，从而可以改进截止状态的特性。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，提供了一种用于鳍式场效应晶体管(FinFET)器件的鳍结构，包括：衬底；第一半导体材料，设置在所述衬底上；浅沟槽隔离(STI)区，设置在所述衬底上方并形成在所述第一半导体材料的相对侧上；以及第二半导体材料，形成在所述STI区上设置的第一鳍和第二鳍，所述第一鳍与所述第二鳍间隔所述第一半导体材料的宽度。
在该鳍结构中，能够相对于所述第二半导体材料选择性地蚀刻所述第一半导体材料。
在该鳍结构中，所述第一半导体材料的顶面通常与所述第一鳍和所述第二鳍的底面共面。
在该鳍结构中，所述第一鳍和所述第二鳍在所述第一半导体材料的顶面上方竖直凸出。
在该鳍结构中，所述第一半导体材料是IV族、III-V族以及II-VI族半导体材料中的一种。
在该鳍结构中，所述第二半导体材料是IV族、III-V族以及II-VI族半导体材料中的一种。
在该鳍结构中，所述第一半导体材料是第一硅锗(SiGe)合金，以及所述第二半导体材料是第二SiGe合金。
在该鳍结构中，所述第一半导体材料是锗，以及所述第二半导体材料是硅。
在该鳍结构中，所述第二半导体材料是外延生长半导体材料。
根据本发明的另一方面，提供了一种场效应晶体管(FinFET)器件，包括：衬底；第一半导体材料，设置在所述衬底上；浅沟槽隔离(STI)区，设置在所述衬底上方并形成在所述第一半导体材料的相对侧上；第二半导体材料，形成在所述STI区上设置的第一鳍和第二鳍，所述第一鳍与所述第二鳍间隔所述第一半导体材料的宽度；以及栅极层，形成在所述第一鳍、在所述第一鳍和所述第二鳍之间设置的所述第一半导体材料的顶面以及所述第二鳍的上方。
在该器件中，能够相对于所述第二半导体材料选择性地蚀刻所述第一半导体材料。
在该器件中，所述第一半导体材料的顶面通常与所述第一鳍和所述第二鳍的底面共面。
在该器件中，所述栅极层形成在所述第一鳍和所述第二鳍的侧壁和顶面上。
在该器件中，所述栅极层不形成在所述第一半导体材料的侧壁上。
在该器件中，掺杂所述第一半导体材料，以禁止通过所述第一半导体材料导电。
在该器件中，所述第二半导体材料是外延生长半导体材料。
根据本发明的又一方面，提供了一种形成鳍式场效应晶体管(FinFET)器件的方法，包括：在衬底上形成第一半导体材料；在所述衬底和所述第一半导体材料的下部上方形成浅沟槽隔离(STI)区；沿着所述第一半导体材料的上部的侧壁外延生长第二半导体材料；以及选择性地蚀刻掉所述第一半导体材料的所述上部以形成第一鳍和第二鳍，所述第一鳍与所述第二鳍间隔所述第一半导体材料的宽度。
该方法进一步包括：在所述第一鳍、设置在所述第一鳍和所述第二鳍之间的所述第一半导体材料的顶面以及所述第二鳍的上方形成栅极层。
在该方法中，在外延生长所述第二半导体材料之前，在所述第一半导体材料的顶面上进一步形成硬掩模。
该方法进一步包括：掺杂所述第一半导体材料，以禁止通过所述第一半导体材料导电。
附图说明
为了更完整地理解本公开内容及其优点，现在将结合附图所进行的以下描述作为参考，其中：
图1a至图1h共同示出了形成用于FinFET器件的鳍结构的工艺的一个实施例；
图2是使用图1的工艺制造的鳍结构的一个实施例的截面图；
图3a至图3i共同示出了形成图2的鳍结构的工艺的一个实施例；
图4a至图4f共同示出了形成图2的鳍结构的工艺的一个实施例；
图5a至图5g共同示出了使用在图1a至图1h、图3a至图3i、或图4a至图4f中共同示出的工艺之一形成FinFET器件的工艺的一个实施例；以及
图6是形成图2的鳍结构的方法的一个实施例。
除非另外说明，否则不同图中的相应数字和符号通常是指相应部分。绘制图以清楚地示出实施例的相关方面并且并不必按比例绘制。
具体实施方式
以下详细论述了本优选实施例的制造和使用。然而，应该想到，本公开内容提供了许多可以在各种具体环境中实现的可应用的发明思想。所论述的特定实施例仅是示意性的，而不限制本公开内容的范围。
结合具体上下文的优选实施例描述了本公开内容，即，FinFET金属氧化物半导体(MOS)。然而，本发明还可以应用于其他集成电路、电子结构等。
图1a至图1h共同示出了形成用于FinFET器件12(在图5g中示出)的鳍结构10(在图2中示出)的工艺的一个实施例。如以下更加全面地说明，鳍结构10通过使鳍密度加倍并且改进衬底隔离来制造具有增强的晶体管性能和改进的功耗的FinFET器件12。实际上，实现鳍结构10的FinFET器件12提供优良性能、短沟道效应以及期望的截止状态下的泄漏控制。另外，使用本文中公开的鳍结构10所形成的FinFET器件12增加了栅极控制面积，并且减小了FinFET器件的栅极宽度而没有增加器件占位面积(footprint)。
现在，参考图1a，浅沟槽隔离(STI)区14形成在衬底16周围。在一个实施例中，STI区14由二氧化硅或其他合适的介电材料形成。在一个实施例中，衬底16是硅或其他合适的半导体材料。如图所示，衬底16通常在STI区14的部分之间向上凸出。另外，衬底16的顶面18和STI区14的顶面20通常是共面的。
现在，参考图1b，通过蚀刻掉衬底16的上部形成凹槽22。此后，在图1c中，第一半导体材料24(也叫作材料A)形成在凹槽22中。在一个实施例中，在凹槽22中外延生长第一半导体材料24。在一个实施例中，在凹槽22填充有第一半导体材料24之后，实施化学机械抛光(CMP)工业以使第一半导体材料24的顶面26和相邻STI区14的顶面20平滑。
在一个实施例中，第一半导体材料24是锗(Ge)、磷化铟(InP)、砷化铟镓(InGaAs)、砷化铟(InAs)、锑化镓(GaSb)、或硅锗(SiGe)。在一个实施例中，第一半导体材料24是IV族、III-V族、或II-VI族半导体材料。在一个实施例中，第一半导体材料24是具有公式Si1-xGex(其中，1＞x＞0)的SiGe合金。
参考图1d，硬掩模28形成在第一半导体材料24上方。在一个实施例中，硬掩模28由氮化硅或其他合适掩模材料形成。一旦沉积硬掩模28，就实施光刻工艺以图案化如图1d所示的硬掩模。接下来，相对于如图1e所示的硬掩模选择性地蚀刻STI区14的上部。如图1e所示，现在，暴露来自第一半导体材料24的上部32的相对侧壁30。
现在，参考图1f，第二半导体材料34(也叫作材料B)形成在第一半导体材料24的侧壁30上。在一个实施例中，第二半导体材料34沿着第一半导体材料24的侧壁30外延生长。如图所示，第二半导体材料34位于STI区上并且在STI区34上方凸出。因为未去除硬掩模28，所以在第一半导体材料24的顶面26上不生长或形成第二半导体材料34。
在在第一半导体材料24的侧壁30上设置第二半导体材料34的情况下，如图1g所示，可以去除硬掩模28。在一个实施例中，去除硬掩模28，而不影响相邻的第二半导体材料34和STI区14。此后，如图1h所示，实施选择性蚀刻工艺以去除第一半导体材料24的上部32(图1e)。如图1h所示，在蚀刻掉第一半导体材料24之后，第二半导体材料24形成整个鳍结构10的第一鳍36和第二鳍38。
第一鳍36和第二鳍38通常设置在STI区14上并且与STI区14直接接触，并且具有介于第一鳍36和第二鳍38之间的凹槽40。另外，在一个实施例中，第一鳍36与第二鳍38间隔第一半导体材料24的宽度42。再次参考图1h，第一半导体材料24的顶面26和/或STI区14的顶面20通常与第一鳍36和第二鳍38的底面44共面。在一个实施例中，第一半导体材料24的顶面26可以竖直地设置在STI区14的顶面20之下。如图所示，第一鳍36和第二鳍38竖直地在第一半导体材料24的顶面上方凸出。在一个实施例中，掺杂第一半导体材料24以禁止或防止通过第一半导体材料24导电。
在一个实施例中，当第一半导体材料是锗(Ge)时，第二半导体材料34是硅(Si)。在这样的实施例中，锗可以使用盐酸(HCI)溶液以非常高的选择性被蚀刻掉。在一个实施例中，当第一半导体材料24是磷化铟(InP)时，第二半导体材料34是砷化铟镓(InGaAs)。在这样的实施例中，磷化铟可以使用盐酸(HCI)溶液以非常高的选择性被蚀刻掉。
在一个实施例中，当第一半导体材料24是砷化铟镓(InGaAs)时，第二半导体材料34是磷化铟(InP)。在这样的实施例中，砷化铟镓可以使用磷酸和过氧化氢(H3PO4+H2O2)以非常高的选择性被蚀刻掉。在一个实施例中，当第一半导体材料24是砷化铟(InAs)时，第二半导体材料34是锑化镓(GaSb)。在这样的实施例中，砷化铟(InAs)可以使用柠檬酸和过氧化氢(C6H8O7+H2O2)溶液以非常高的选择性被蚀刻掉。
在一个实施例中，当第一半导体材料24是锑化镓(GaSb)时，第二半导体材料34是砷化铟(InAs)。在这样的实施例中，锑化镓可以使用氢氧化铵(NH4OH)溶液以非常高的选择性被蚀刻掉。在其他实施例中，其他结合和其他蚀刻化合物是可能的。在一些实施例中，选择性可以接近或实现百分之一百。
在一个实施例中，第二半导体材料34是IV族、III-V族、II-VI族半导体材料。在一个实施例中，当第一半导体材料24是具有公式Si1-xGex(其中，1＞x＞0)的SiGe合金时，第二半导体材料34是具有公式Si1-yGey(其中，1＞y＞0)的SiGe合金，其中，x＞y。在这样的实施例中，具有公式Si1-xGex的SiGe合金可以使用盐酸(HCI)溶液以非常高的选择性被蚀刻掉。
现在，参考图2，在一个实施例中，鳍结构10上的第一鳍36和第二鳍38的高度46可以在约5纳米(5nm)和约40纳米(40nm)之间。在一个实施例中，第一鳍36和第二鳍38的宽度48可以在约2纳米(2nm)和10纳米(10nm)之间。在一个实施例中，在第一鳍36和第二鳍38之间的距离50(如图1h所示，通常等于第一半导体材料24的上部的宽度42)可以在约5纳米(5nm)和约20纳米(20nm)之间。在其他实施例中，其他尺寸是可能的。
图3a至图3i共同示出形成用于FinFET器件的鳍结构的工艺的另一个实施例。在实施如之前所描述的图3a至3c的步骤之后，使第一半导体材料24凹进，并且如图3d所示，形成硬掩模层52。此后，如图3e所示，实施CMP工艺以生成嵌入STI区14中的硬掩模28。此后，实施之前所描述的图3f至图3i的步骤。
图4a至图4f共同示出形成用于FinFET器件的鳍结构的工艺的另一个实施例。如图4a所示，在衬底16上方生长或沉积第一半导体材料24的覆盖层。此后，如图4b所示，蚀刻掉第一半导体材料24的一部分并且通过STI区14代替。在图4b中，也蚀刻第一半导体材料24，以提供用于在其上形成硬掩模26的空间。此后，执行如之前所描述的图4c-4f的步骤。
图5a至图5g共同示出使用例如图1a至图1h、图3a至图3i或图4a至图4f中共同示出的生成鳍结构10的工艺之一形成FinFET器件12的工艺的实施例。如图5a所示，在半导体材料24上方形成通过STI区14包围的硬掩模28。此后，在图5b中，去除STI区14的上部以暴露第一半导体材料24的侧壁30。注意，硬掩模28仍然存在。接下来，如图5c所示，第二半导体材料34在侧壁30上和上方并且在STI区14上方外延生长。
一旦形成第二半导体材料34，就去除硬掩模28，然后去除第一半导体材料24的上部(即，在STI区14上方设置的第一半导体材料24的一部分)，从而保留鳍结构10。如上所述，相对于第二半导体材料34选择性地去除第一半导体材料24。如图5d所示，去除第一半导体材料24的上部留下第一鳍36和第二鳍38，第一鳍36和第二鳍38彼此间隔等于第一半导体材料24的宽度的距离。鳍36、38由第二半导体材料34形成。
如图5e所示，栅极层54形成在STI区14的一部分、第一鳍36的一部分、第一半导体材料24的顶面26的一部分、第二鳍38的一部分、以及STI区14的附加部分上方。如图5f至图5g所示，形成隔离件56和源极/漏极接触件58。为了便于说明，在图5g中仅示出了隔离件56之一和源极/漏极接触件58之一。然而，本领域技术人员应该理解，可以形成附加隔离件56和附加源极/漏极接触件58并且通过FinFET器件12利用附加隔离件56和附加源极/漏极接触件58。在一个实施例中，源极/漏极接触件58通过外延生长工艺形成。
现在，参考图6，提供形成FinFET器件的方法60。在框62中，第一半导体材料24在衬底上形成。在框64中，STI区14在衬底16和第一半导体材料24的下部上方形成。在框66中，沿着第一半导体材料24的上部32的侧壁30外延生长第二半导体材料。在框68中，选择性地蚀刻掉第一半导体材料的上部以形成第一鳍36和第二鳍38，第一鳍36和第二鳍38彼此间隔第一半导体材料24的宽度。
一种用于鳍式场效应晶体管(FinFET)器件的鳍结构。该器件包括衬底、设置在衬底上的第一半导体材料、设置在衬底上方并且形成在第一半导体材料的相对两侧上的浅沟槽隔离(STI)区、以及形成在STI区上设置的第一鳍和第二鳍的第二半导体材料、第一鳍与第二鳍间隔第一半导体材料的宽度。
一种场效应晶体管(FinFET)器件。该器件包括：衬底；设置在衬底上的第一半导体材料；设置在衬底上方并且形成在第一半导体材料的相对两侧上的浅沟槽隔离(STI)区；形成在STI区上设置的第一鳍和第二鳍的第二半导体材料，其中，第一鳍与第二鳍间隔第一半导体材料的宽度；以及在第一鳍上方、设置在第一鳍和第二鳍之间的第一半导体材料的顶面上方、以及第二鳍上方形成的栅极层。
一种形成鳍式场效应晶体管(FinFET)器件的方法。该方法包括：在衬底上形成第一半导体材料；在衬底和第一半导体材料的下部上方形成浅沟槽隔离(STI)区；沿着第一半导体材料的上部的侧壁外延生长第二半导体材料；以及选择性地蚀刻掉第一半导体材料的上部以形成第一鳍和第二鳍，第一鳍与第二鳍间隔第一半导体材料的宽度。
虽然本公开内容提供了示例性实施例，但是该说明书不旨在解释为限制意义。当参考说明书时，示例性实施例以及其他实施例的多种修改和结合对于本领技术人员来说是显而易见的。因此，目的是所附权利要求包含任何这种修改或实施例。

Claims (10)

1.一种用于鳍式场效应晶体管(FinFET)器件的鳍结构，包括：
衬底；
第一半导体材料，设置在所述衬底上；
浅沟槽隔离(STI)区，设置在所述衬底上方并形成在所述第一半导体材料的相对侧上；以及
第二半导体材料，形成在所述STI区上设置的第一鳍和第二鳍，所述第一鳍与所述第二鳍间隔所述第一半导体材料的宽度。
2.根据权利要求1所述的鳍结构，其中，能够相对于所述第二半导体材料选择性地蚀刻所述第一半导体材料。
3.根据权利要求1所述的鳍结构，其中，所述第一半导体材料的顶面通常与所述第一鳍和所述第二鳍的底面共面。
4.根据权利要求1所述的鳍结构，其中，所述第一鳍和所述第二鳍在所述第一半导体材料的顶面上方竖直凸出。
5.根据权利要求1所述的鳍结构，其中，所述第一半导体材料是IV族、III-V族以及II-VI族半导体材料中的一种。
6.根据权利要求1所述的鳍结构，其中，所述第二半导体材料是IV族、III-V族以及II-VI族半导体材料中的一种。
7.根据权利要求1所述的鳍结构，其中，所述第一半导体材料是第一硅锗(SiGe)合金，以及所述第二半导体材料是第二SiGe合金。
8.根据权利要求1所述的鳍结构，其中，所述第一半导体材料是锗，以及所述第二半导体材料是硅。
9.一种场效应晶体管(FinFET)器件，包括：
衬底；
第一半导体材料，设置在所述衬底上；
浅沟槽隔离(STI)区，设置在所述衬底上方并形成在所述第一半导体材料的相对侧上；
第二半导体材料，形成在所述STI区上设置的第一鳍和第二鳍，所述第一鳍与所述第二鳍间隔所述第一半导体材料的宽度；以及
栅极层，形成在所述第一鳍、在所述第一鳍和所述第二鳍之间设置的所述第一半导体材料的顶面以及所述第二鳍的上方。
10.一种形成鳍式场效应晶体管(FinFET)器件的方法，包括：
在衬底上形成第一半导体材料；
在所述衬底和所述第一半导体材料的下部上方形成浅沟槽隔离(STI)区；
沿着所述第一半导体材料的上部的侧壁外延生长第二半导体材料；以及
选择性地蚀刻掉所述第一半导体材料的所述上部以形成第一鳍和第二鳍，所述第一鳍与所述第二鳍间隔所述第一半导体材料的宽度。
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