CN103367397A - 半导体基板、具有其的半导体芯片和堆叠半导体封装体 - Google Patents
半导体基板、具有其的半导体芯片和堆叠半导体封装体 Download PDFInfo
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Abstract
一种半导体基板、具有其的半导体芯片和堆叠半导体封装体。该半导体基板包括:基板本体,分成器件区域和在器件区域之外的外围区域,并且基板本体具有一个表面、实质上背对一个表面的另一个表面、限定在器件区域中一个表面下方的沟槽以及由于限定沟槽而形成的内表面;有源区域,形成在沟槽中;以及吸除层,形成在基板本体的内表面与有源区域之间。
Description
技术领域
本发明总体上涉及适合于改善吸除特性的半导体基板、具有该半导体基板的半导体芯片以及具有该半导体芯片的堆叠半导体封装体。
背景技术
在半导体工业中,用于集成电路的封装技术被不断地开发以满足小型化和安装可靠性的要求。近来,随着在电气和电子应用中对于小型化和高性能的要求,开发了各种堆叠技术。
在半导体工业中,术语“堆叠”是指垂直堆积至少两个半导体芯片或半导体封装体。在存储装置的情况下,通过采用堆叠技术,能够实现的产品的存储容量为通过半导体集成工艺获得的至少两倍大。因为堆叠半导体封装体不仅具有存储容量上的优点,而且具有安装面积利用率上的优点,所以已经加速对于堆叠半导体封装体的研究与开发。
作为堆叠半导体封装体的示例,提出了这样的结构,其中贯通电极形成在半导体芯片中,使得上半导体芯片与下半导体芯片由贯通电极彼此物理和电性连接。
然而,用作贯通电极的物质,例如铜,很可能扩散到半导体芯片从而导致晶体缺陷。结果,半导体芯片中可能引发漏电流,并且晶体管的阈值电压很可能偏移,由此刷新特性可能劣化。
为了应对此问题,公开了这样的方法,其中使形成在贯通电极和半导体芯片之间的介电层(SiO2)的厚度增加,从而使得朝向半导体芯片扩散的铜可被介电层吸除。然而,介电层不足以吸除从贯通电极扩散的铜。
发明内容
实施例涉及适合于改善吸除特性的半导体基板。
而且,实施例涉及具有半导体基板的半导体芯片。
此外,实施例涉及具有半导体芯片的堆叠半导体封装体。
在实施例中,半导体基板包括:基板本体,分成器件区域和在器件区域外面的外围区域,并且具有一个表面,实质上背对一个表面的另一个表面、限定在器件区域中一个表面下方的沟槽和由于限定沟槽而形成的内表面;有源区域,形成在沟槽中;以及吸除层,形成在基板本体的内表面与有源区域之间。
有源区域可包括单晶硅,并且吸除层可包括多晶硅。
在另一个实施例中,半导体芯片包括:半导体基板、半导体器件以及贯通电极,半导体基板包括基板本体、有源区域和吸除层,基板本体分成器件区域和在器件区域外面的外围区域,并且基板本体具有一个表面、实质上背对一个表面的另一个表面、限定在器件区域中一个表面下方的沟槽和由于限定沟槽而形成的内表面,有源区域形成在沟槽中,吸除层形成在基板本体的内表面与有源区域之间,半导体器件形成在有源区域上,贯通电极穿过基板本体的外围区域。
有源区域可包括单晶硅,并且吸除层可包括多晶硅。
半导体器件可包括选自图像传感器、存储器半导体、系统半导体、无源元件、有源元件和传感器半导体中的至少一种。
半导体芯片还可包括电路图案,其形成在基板本体的一个表面和有源区域之上,并且电路图案可包括:接合垫,形成在电路图案的第一表面上且与贯通电极电连接,电路图案的第一表面实质上背对电路图案的第二表面,电路图案的第二表面实质上面对基板本体的一个表面和有源区域;配线,电连接半导体器件与接合垫;以及介电层,使半导体器件与配线彼此隔离,使配线彼此隔离,并且使配线与接合垫彼此隔离。
贯通电极可穿过电路图案并且可与接合垫直接连接。与此不同,贯通电极可不穿过电路图案并且电路图案还可包括附加配线,附加配线使贯通电极与接合垫彼此电连接。
在另一个实施例中,堆叠半导体封装体包括多个半导体芯片以及导电连接构件,每一个半导体芯片都包括半导体基板、半导体器件和贯通电极,半导体基板包括基板本体、有源区域和吸除层,基板本体分成器件区域和在器件区域之外的外围区域,并且基板本体具有一个表面、实质上背对一个表面的另一个表面、限定在器件区域中一个表面下方的沟槽以及由于限定沟槽而形成的内表面,有源区域形成在沟槽中,吸除层形成在基板本体的内表面和有源区域之间,半导体器件形成在有源区域上,贯通电极穿过基板本体的外围区域,多个半导体芯片堆叠为使得贯通电极彼此电连接,导电连接构件使堆叠的半导体芯片的贯通电极电连接。
每个半导体芯片的有源区域可包括单晶硅,并且每个半导体芯片的吸除层可包括多晶硅。
每个半导体芯片的半导体器件可包括选自图像传感器、存储器半导体、系统半导体、无源元件、有源元件和传感器半导体中的至少一种。
每个半导体芯片还可包括电路图案,电路图案形成在基板本体的一个表面和有源区域之上,并且电路图案可包括:接合垫,形成在电路图案的第一表面上且与贯通电极电连接,电路图案的第一表面实质上背对电路图案的第二表面,电路图案的第二表面实质上面对基板本体的一个表面和有源区域;配线,电连接半导体器件与接合垫;以及介电层,使半导体器件与配线彼此隔离,使配线彼此隔离,并且使配线与接合垫彼此隔离。
贯通电极可通过电路图案并且可与接合垫直接连接。与此不同,贯通电极可不通过电路图案,并且电路图案还可包括附加配线,附加配线使贯通电极与接合垫彼此电连接。
堆叠半导体封装体还可包括:第一介电层,形成在堆叠的半导体芯片当中最下方的半导体芯片的下表面下方并且构造为暴露最下方的半导体芯片的贯通电极;重分配线,形成在第一介电层下方并且与通过第一介电层暴露的贯通电极电连接;以及第二介电层,形成在包括重分配线的第一介电层下方并且构造为暴露重分配线的一部分。
堆叠半导体封装体还可包括结构体,其支撑半导体芯片且包括连接电极,连接电极与堆叠的半导体芯片当中最下方的半导体芯片的贯通电极电连接。结构体可包括印刷电路板、内插器和半导体封装体中的任何一种。
附图说明
图1是示出根据实施例的半导体芯片的截面图。
图2是示出图1所示半导体基板的截面图。
图3是示出根据实施例的堆叠半导体封装体的截面图。
图4是示出根据实施例的堆叠半导体封装体的截面图。
图5是示出具有根据实施例的半导体芯片的电子设备的立体图。
图6是示出具有根据实施例的半导体芯片的电子设备的示例的模块图。
具体实施方式
在下文,将参考附图描述各种实施例。
这里应理解的是,附图不必按比例,并且在某些情况下比例可被夸大以更加清楚地描述本发明的某些特征。附图中,相同的标号通篇表示相同的元件。
图1是示出根据实施例的半导体芯片的截面图,而图2是示出图1所示半导体基板的截面图。
参见图1,根据第一实施例的半导体芯片10可包括半导体基板100、贯通电极200和半导体器件300。此外,半导体芯片10还可包括电路图案400。
参见图2,半导体基板100可包括基板本体110、有源区域120和吸除层(gettering layer)130。
基板本体110可分成器件区域DR和外围区域PR。基板本体110可具有一个表面111、另一个表面112、沟槽113以及内表面,另一个表面112实质上背对该一个表面111、沟槽113可限定在器件区域DR中的该一个表面111下方,内表面由于限定沟槽113而形成。
有源区域120可形成在沟槽113中,并且可包括单晶硅。
吸除层130可形成在基板本体的内表面和有源区域120之间。吸除层130可包括多晶硅。
半导体基板100可制作在晶片上,或者可在制造在晶片上之后被单个化。
参见图1,贯通电极200通过基板本体110的外围区域PR。用作贯通电极200的物质可包括选自铜、铝、铝合金、SnAg和Au中的至少一种。
尽管没有示出,但是介电层可形成在贯通电极200和基板本体110之间。介电层可包括选自氧化物层、氮化物层和有机层中的至少任何一种。
半导体器件300可形成在有源区域120上。半导体器件300例如可包括选自图像传感器、存储器半导体、系统半导体、无源元件、有源元件和传感器半导体中的至少一种。
电路图案400可形成在基板本体110的一个表面111上以及有源区域120上。电路图案400可包括第一表面410、第二表面420、接合垫430、配线440和介电层450。
第一表面410可实质上背对第二表面420。第二表面420可实质上面对基板本体110的一个表面111和有源区域120,并且接合垫430可设置在第一表面410且可与贯通电极200电连接。
配线440可电连接半导体器件300与接合垫430,并且介电层450可使半导体器件300和配线440彼此隔离,使得配线440彼此隔离,且使得配线440和接合垫430彼此隔离。
在实施例中,贯通电极200可穿过电路图案400,并且可与接合垫430直接连接。然而,尽管附图中没有示出,但是贯通电极200可不穿过电路图案400,并且在此情况下,电路图案400还可包括附加配线(未示出),其使贯通电极200和接合垫430彼此电连接。
在下文,将描述具有上述半导体芯片的堆叠半导体封装体。
图3是示出根据实施例的堆叠半导体封装体的截面图。
参见图3,在制备多个半导体芯片10i-10iii后,半导体芯片10i-10iii的每一个都包括半导体基板100、贯通电极200和半导体器件300,半导体基板100可限定有形成在吸除层130中的有源区域120。第二半导体芯片10ii可堆叠在第一半导体芯片10i上,使得第二半导体芯片10ii的贯通电极200可连接到第一半导体芯片10i的贯通电极200。这样,多个半导体芯片,例如三个半导体芯片10i-10iii,可一个堆叠在另一个上。
导电连接构件20可形成在堆叠的半导体芯片10i-10iii的贯通电极200之间以电连接上和下半导体芯片10i-10iii的贯通电极200,并且粘合剂构件30可形成在堆叠的半导体芯片10i-10iii之间以彼此粘合上和下半导体芯片10i-10iii。
导电连接构件20可由金属形成,该金属包括铜(Cu)、锡(Sn)和银(Ag)中的至少一种,并且粘合剂构件30可包括非导电膜(NCF)、非导电膏(NCP)、各向异性导电膜(ACF)、各向异性导电膏(ACP)和聚合物当中的至少一种。
第一介电层40可形成在第一半导体芯片10i(第一半导体芯片10i是堆叠的半导体芯片10i-10iii当中的最下方的半导体芯片)的下表面下方,使得第一半导体芯片10i的贯通电极200被暴露。重分配线50可形成在第一介电层40下方,可与第一半导体芯片10i的贯通电极200电连接。第二介电层60可形成在包括重分配线50的第一介电层40下方,以使得部分的重分配线50被暴露。外部连接端子70可安装到重分配线50的通过第二介电层60暴露的部分。
图4是示出根据实施例的堆叠半导体封装体的截面图。
参见图4,在制备了多个半导体芯片10i-10iii之后(半导体芯片10i-10iii的每一个都包括半导体基板100、贯通电极200和半导体器件300,半导体基板100可限定有形成在吸除层130中的有源区域120),第二半导体芯片10ii可堆叠在第一半导体芯片10i上,使得第二半导体芯片10ii的贯通电极200可连接到第一半导体芯片10i的贯通电极200。这样,多个半导体芯片,例如三个半导体芯片10i-10iii,可一个堆叠在另一个上。
导电连接构件20可形成在堆叠的半导体芯片10i-10iii的贯通电极200之间以电连接上和下半导体芯片10i-10iii的贯通电极200。粘合剂构件30可形成在堆叠的半导体芯片10i-10iii之间以彼此粘合上和下半导体芯片10i-10iii。
导电连接构件20可由金属形成,该金属包括铜(Cu)、锡(Sn)和银(Ag)中的至少一种。粘合剂构件30可包括非导电膜(NCF)、非导电膏(NCP)、各向异性导电膜(ACF)、各向异性导电膏(ACP)和聚合物当中的至少一种。
堆叠的半导体芯片10i-10iii可安装到结构体80,使得作为堆叠的半导体芯片10i-10iii当中的最下方的半导体芯片的第一半导体芯片10i的贯通电极200可与结构体80的连接电极82电连接。在实施例中,结构体80例如可包括印刷电路板(PCB)。
第一半导体芯片10i的贯通电极200和结构体80的连接电极82可由导电连接构件90彼此电连接。粘合剂构件92可形成在第一半导体芯片10i和结构体80之间以使第一半导体芯片10i和结构体80彼此粘合。
导电连接构件90可由金属形成,该金属包括铜(Cu)、锡(Sn)和银(Ag)中的至少一种。粘合剂构件92可包括非导电膜(NCF)、非导电膏(NCP)、各向异性导电膜(ACF)、各向异性导电膏(ACP)和聚合物当中的至少一中。
包括堆叠的半导体芯片10i-10iii的结构体80的上表面可通过模塑部件94密封。参考标号84表示球焊盘,并且86表示焊料球,其可用作外部连接端子。
尽管在图4所示的实施例中描述了结构体80可包括印刷电路板,但是应注意结构体80也可包括半导体封装体或内插器。
前述半导体芯片可应用于各种电子设备。
图5是示出具有根据实施例的半导体芯片的电子设备的立体图。
参见图5,根据本发明实施例的半导体芯片例如可应用于电子设备1000,诸如便携式电话。因为根据实施例的半导体芯片具有良好的吸除特性,所以对改善电子设备1000的性能和可靠性的提供了优点。电子设备1000不限于图5所示的便携式电话,而是可包括各种电子应用,例如,诸如移动电子应用、膝上电脑、笔记本电脑、便携式多媒体播放器(PMP)、MP3播放器、便携式摄像机、网络写字板、无线电话、汽车导航仪、个人数字助理(PDA),等等。
图6是示出具有根据实施例的半导体芯片的电子设备的示例的模块图。
参见图6,电子系统1300可包括控制器1310、输入/输出单元1320和存储器1330。控制器1310、输入/输出单元1320和存储器1330可通过汇流线1350彼此连接。汇流线1350用作数据通过其可移动的通道。例如,控制器1310可包括至少一个微处理器、至少一个数字信号处理器、至少一个微控制器以及能够与这些部件执行相同功能的逻辑器件中的至少任何一种。控制器1310和存储器1330可包括根据实施例的半导体芯片。输入/输出单元1320可包括选自键区、键盘、显示装置等当中的至少一种。存储器1330可以是存储数据的装置。存储器1330可存储控制器1310要执行的数据和/或指令等。存储器1330可包括易失性存储装置和/或非易失性存储装置。另外,存储器1330可由闪存构成。例如,应用实施例技术的闪存可安装到诸如移动终端或台式电脑的信息处理系统。闪存可由固态驱动器(SSD)构成。在此情况下,电子系统1300可在闪存系统中稳定地存储大量的数据。电子系统1300还可包括接口1340,构造为传输数据到通讯网络或从通讯网络接收数据。接口1340可为有线型或无线型的。例如,接口1340可包括天线或有线或无线收发器。此外,尽管没有示出,但是本领域的技术人员可易于理解的是,电子系统1300可附加提供有应用芯片集、照相机图像处理器(CIS)、输入/输出单元等。
由上面的描述可见,根据实施例,因为从贯通电极向有源区域扩散的金属被形成在有源区域下方由多晶硅构成的吸除层有效吸除,所以可改善吸除特性。结果,能够防止在半导体器件中产生漏电流以及防止阈值电压偏移,并且改善刷新特性,从而可改善产品的可靠性和性能。
尽管出于示例的目的已经描述的具体的实施例,但是本领域的技术人员应理解的是,在不偏离如所附权利要求公开的实施例的范围和精神的情况下,可进行各种变型、添加和替代。
本申请要求2012年4月5日提交韩国知识产权局的韩国专利第10-2012-0035278号的优先权,其全部内容通过引用结合于此。
Claims (20)
1.一种半导体基板,包括:
基板本体,分成器件区域和在该器件区域之外的外围区域,并且该基板本体具有一个表面、实质上背对该一个表面的另一个表面、限定在该器件区域中该一个表面下方的沟槽以及由于限定该沟槽而形成的内表面;
有源区域,形成在该沟槽中;以及
吸除层,形成在该基板本体的该内表面与该有源区域之间。
2.根据权利要求1所述的半导体基板,其中该有源区域包括单晶硅。
3.根据权利要求1所述的半导体基板,其中该吸除层包括多晶硅。
4.一种半导体芯片,包括:
半导体基板,包括基板本体、有源区域和吸除层,该基板本体分成器件区域和在该器件区域之外的外围区域,且该基板本体具有一个表面、实质上背对该一个表面的另一个表面、限定在该器件区域中该一个表面下方的沟槽以及由于限定该沟槽而形成的内表面,该有源区域形成在该沟槽中,该吸除层形成在该基板本体的该内表面与该有源区域之间;
半导体器件,形成在该有源区域上;以及
贯通电极,穿过该基板本体的该外围区域。
5.根据权利要求4所述的半导体芯片,其中该有源区域包括单晶硅。
6.根据权利要求4所述的半导体芯片,其中该吸除层包括多晶硅。
7.根据权利要求4所述的半导体芯片,其中该半导体器件包括选自图像传感器、存储器半导体、系统半导体、无源元件、有源元件和传感器半导体中的至少一种。
8.根据权利要求4所述的半导体芯片,还包括:
电路图案,形成在该基板本体的该一个表面以及该有源区域上,
其中该电路图案包括:
接合垫,形成在该电路图案的第一表面上且与该贯通电极电连接,该电路图案的该第一表面实质上背对该电路图案的第二表面,该电路图案的该第二表面实质上面对该基板本体的该一个表面以及该有源区域;
配线,电连接该半导体器件与该接合垫;以及
介电层,使该半导体器件与配线彼此隔离,使该配线彼此隔离,并且使该配线与该接合垫彼此隔离。
9.根据权利要求8所述的半导体芯片,其中该贯通电极穿过该电路图案,并且与该接合垫直接连接。
10.根据权利要求8所述的半导体芯片,其中该贯通电极不穿过该电路图案,并且该电路图案还包括附加配线,该附加配线使该贯通电极和该接合垫彼此电连接。
11.一种堆叠半导体封装体,包括:
多个半导体芯片,每一个半导体芯片都包括半导体基板、半导体器件和贯通电极,该半导体基板包括基板本体、有源区域和吸除层,该基板本体分成器件区域和在该器件区域之外的外围区域,并且具有一个表面、实质上背对该一个表面的另一个表面、限定在该器件区域中该一个表面下方的沟槽以及由于限定该沟槽而形成的内表面,该有源区域形成在该沟槽中,该吸除层形成在该基板本体的该内表面与该有源区域之间,该半导体器件形成在该有源区域上,该贯通电极穿过该基板本体的该外围区域,该多个半导体芯片堆叠为使该贯通电极彼此电连接;以及
导电连接构件,电连接堆叠的半导体芯片的该贯通电极。
12.根据权利要求11所述的堆叠半导体封装体,其中每个半导体芯片的有源区域包括单晶硅。
13.根据权利要求11所述的堆叠半导体封装体,其中每个半导体芯片的吸除层包括多晶硅。
14.根据权利要求11所述的堆叠半导体封装体,其中每个半导体芯片的半导体器件包括选自图像传感器、存储器半导体、系统半导体、无源元件、有源元件和传感器半导体中的至少一种。
15.根据权利要求11所述的堆叠半导体封装体,
其中每个半导体芯片还包括电路图案,该电路图案形成在该基板本体的该一个表面和该有源区域上,并且
其中该电路图案包括:
形成在该电路图案的第一表面上且与该贯通电极电连接的接合垫,该电路图案的第一表面实质上背对该电路图案的第二表面,该电路图案的该第二表面实质上面对该基板本体的该一个表面和该有源区域;
配线,电连接该半导体器件与该接合垫;以及
介电层,使该半导体器件与该配线彼此隔离,使该配线彼此隔离,并且使该配线和该接合垫彼此隔离。
16.根据权利要求15所述的堆叠半导体封装体,其中该贯通电极穿过该电路图案,并且与该接合垫直接连接。
17.根据权利要求15所述的堆叠半导体封装体,其中该贯通电极不穿过该电路图案,并且该电路图案还包括附加配线,该附加配线使该贯通电极与该接合垫彼此电连接。
18.根据权利要求11所述的堆叠半导体封装体,还包括:
第一介电层,形成在堆叠的半导体芯片当中最下方的半导体芯片的下表面下方,并且构造为暴露该最下方的半导体芯片的该贯通电极;
重分配线,形成在该第一介电层下方并且与通过该第一介电层暴露的该贯通电极电连接;以及
第二介电层,形成在包括该重分配线的该第一介电层下方并且构造为暴露该重分配线的一部分。
19.根据权利要求11所述的堆叠半导体封装体,还包括:
结构体,支撑该半导体芯片并且包括连接电极,该连接电极与堆叠的半导体芯片当中最下方的半导体芯片的贯通电极电连接。
20.根据权利要求19所述的堆叠半导体封装体,其中该结构体包括印刷电路板、内插器和半导体封装体中的任何一种。
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KR1020120035278A KR20130113032A (ko) | 2012-04-05 | 2012-04-05 | 반도체 기판, 이를 갖는 반도체 칩 및 적층 반도체 패키지 |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108701683A (zh) * | 2016-02-18 | 2018-10-23 | 科锐 | 其中集成阻抗匹配网络元件的基于pcb的半导体封装件 |
CN110021521A (zh) * | 2017-11-30 | 2019-07-16 | 台湾积体电路制造股份有限公司 | 半导体器件及其制造方法 |
US11791299B2 (en) | 2017-11-30 | 2023-10-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Redistribution layer (RDL) layouts for integrated circuits |
US12021054B2 (en) | 2023-07-31 | 2024-06-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Redistribution layer (RDL) layouts for integrated circuits |
Families Citing this family (1)
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WO2015186625A1 (ja) * | 2014-06-03 | 2015-12-10 | 株式会社日本製鋼所 | ゲッタリング層を持つ半導体の製造方法、半導体装置の製造方法および半導体装置 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030011068A1 (en) * | 2001-07-10 | 2003-01-16 | Samsung Electronics Co., Ltd. | Semiconductor chip having bond pads and multi-chip package |
CN1812089A (zh) * | 2004-12-21 | 2006-08-02 | 精工爱普生株式会社 | 半导体装置及其制造方法、电路基板、以及电子仪器 |
JP2007227601A (ja) * | 2006-02-23 | 2007-09-06 | Seiko Epson Corp | 半導体装置および半導体装置の製造方法 |
JP2007250561A (ja) * | 2004-04-12 | 2007-09-27 | Japan Science & Technology Agency | 半導体素子および半導体システム |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5834350A (en) * | 1997-06-11 | 1998-11-10 | Advanced Micro Devices, Inc. | Elevated transistor fabrication technique |
US9608119B2 (en) * | 2010-03-02 | 2017-03-28 | Micron Technology, Inc. | Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices including such structures |
US8426946B2 (en) * | 2010-06-28 | 2013-04-23 | Headway Technologies, Inc. | Laminated semiconductor substrate, laminated chip package and method of manufacturing the same |
JP2012222161A (ja) * | 2011-04-08 | 2012-11-12 | Elpida Memory Inc | 半導体装置 |
-
2012
- 2012-04-05 KR KR1020120035278A patent/KR20130113032A/ko not_active Application Discontinuation
- 2012-09-13 JP JP2012201078A patent/JP2013219317A/ja active Pending
- 2012-09-13 US US13/614,924 patent/US8829657B2/en active Active
- 2012-10-31 CN CN2012104277531A patent/CN103367397A/zh active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030011068A1 (en) * | 2001-07-10 | 2003-01-16 | Samsung Electronics Co., Ltd. | Semiconductor chip having bond pads and multi-chip package |
JP2007250561A (ja) * | 2004-04-12 | 2007-09-27 | Japan Science & Technology Agency | 半導体素子および半導体システム |
CN1812089A (zh) * | 2004-12-21 | 2006-08-02 | 精工爱普生株式会社 | 半导体装置及其制造方法、电路基板、以及电子仪器 |
JP2007227601A (ja) * | 2006-02-23 | 2007-09-06 | Seiko Epson Corp | 半導体装置および半導体装置の製造方法 |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108701683A (zh) * | 2016-02-18 | 2018-10-23 | 科锐 | 其中集成阻抗匹配网络元件的基于pcb的半导体封装件 |
CN108701683B (zh) * | 2016-02-18 | 2021-08-13 | 科锐 | 其中集成阻抗匹配网络元件的基于pcb的半导体封装件 |
CN110021521A (zh) * | 2017-11-30 | 2019-07-16 | 台湾积体电路制造股份有限公司 | 半导体器件及其制造方法 |
CN110021521B (zh) * | 2017-11-30 | 2021-08-03 | 台湾积体电路制造股份有限公司 | 半导体器件及其制造方法 |
US11791299B2 (en) | 2017-11-30 | 2023-10-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Redistribution layer (RDL) layouts for integrated circuits |
US12021054B2 (en) | 2023-07-31 | 2024-06-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Redistribution layer (RDL) layouts for integrated circuits |
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JP2013219317A (ja) | 2013-10-24 |
US20130264689A1 (en) | 2013-10-10 |
US8829657B2 (en) | 2014-09-09 |
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