CN103329274A - Selective germanium P-contact metalization through trench - Google Patents

Selective germanium P-contact metalization through trench Download PDF

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CN103329274A
CN103329274A CN2011800614402A CN201180061440A CN103329274A CN 103329274 A CN103329274 A CN 103329274A CN 2011800614402 A CN2011800614402 A CN 2011800614402A CN 201180061440 A CN201180061440 A CN 201180061440A CN 103329274 A CN103329274 A CN 103329274A
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CN103329274B (en
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G·A·格拉斯
A·S·莫西
T·甘尼
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Intel Corp
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Intel Corp
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    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate

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Abstract

Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in Sight of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type de vices, but can be used for n-type de vices if so desired.

Description

Pass the selectivity germanium P contact metallization of groove
Related application
The application is the U. S. application No.12/975 that submitted on December 21st, 2010,278 part continuation application.
Background technology
Comprise the circuit devcie of transistor, diode, resistor, capacitor and other passive and the raising of active electronic performance of devices is normally considered in design, manufacturing and the operating period of those devices principal element that forms in Semiconductor substrate.For example, during the Design and manufacture or formation of metal-oxide semiconductor (MOS) (MOS) transistor semiconductor device (such as the semiconductor device that is used for complementary metal oxide semiconductors (CMOS) (CMOS)), usually it is minimum that expectation makes the dead resistance that is associated with contact point, and this dead resistance is called non-essential resistance R in addition ExtThe R that reduces ExtCan from identical transistor design, realize higher electric current.
Description of drawings
Figure 1A illustrates the MOS device of the boron doped germanium layer that disposes according to an embodiment of the invention between source/drop ply and contacting metal.
Figure 1B illustrates the MOS device that disposes the boron doped germanium layer between source/drop ply and contacting metal according to another embodiment of the present invention.
Fig. 1 C illustrates the MOS device that disposes the boron doped germanium layer between source/drop ply and contacting metal according to another embodiment of the present invention.
Fig. 2 is the method that is used to form according to an embodiment of the invention the transistor arrangement with low contact resistance.
Fig. 3 A to 3I illustrates the structure that forms when the method for execution graph 2 according to each embodiment of the present invention.
Fig. 4 is the method that is used to form the transistor arrangement with low contact resistance according to another embodiment of the present invention.
Fig. 5 A to 5F illustrates the structure that forms when the method for execution graph 4 according to each embodiment of the present invention.
Fig. 6 illustrates the stereogram of the FinFET transistor body architecture that configures according to one embodiment of present invention.
Fig. 7 illustrates the drawing of cutting apart in batches, illustrates according to the transistor arrangement of embodiments of the invention configuration and does not configure the contact resistance of the standard crystal tubular construction of cap rock.
Fig. 8 illustrates the computing system of realizing according to the one or more transistor arrangements of utilizing of example embodiment of the present invention.
As it will be appreciated that ground, these figure not necessarily draw in proportion, or concrete configuration shown in being intended to invention required for protection is limited to.For example, although some figure roughly indicate straight line, right angle and smooth surface, but consider the physical constraints of employed treatment facility and technology, the actual implementation of transistor arrangement may have faulty straight line, right angle, and some features may have surface placement or unsmooth.In brief, providing accompanying drawing only is for example structure is shown.
Specifically describe
The technology that has the transistor device of the parasitic contact resistance that reduces with respect to conventional device that is used to form is disclosed.These technology for example usable criterion contact lamination (such as a series of metals on silicon or SiGe (SiGe) source/drain region) realize.According to the example of such embodiment, the boron undoped sige layer is significantly to reduce contact resistance in the middle of arranging between source/leakage and contacting metal.According to the disclosure, many transistor arrangement and suitable manufacturing process will be apparent, comprise the channel structure of plane and nonplanar transistor arrangement (for example FinFET) and strain and non-strain.These technology are particularly useful for realizing the p-type device, but also can be used for the N-shaped device when needed.
General view
As illustrated before, can realize the increase of drive current in the transistor by reducing device resistance.Contact resistance is the one-component of the overall electrical resistance of device.For example, the transistor contacts lamination of standard comprises: silicon or SiGe source/drop ply, nickel silicide layer, titanium nitride adhesive layer and tungsten contact pad.In such structure, by aiming at of the pinning energy level in silicon or SiGe valence band and the metal, contact resistance is effectively limited.Typically, utilize industrial standard silicide such as nickel (or other suitable silicide, such as titanium, cobalt or platinum), this causes, and about 0.5eV's can be with misalignment.Therefore, according to example embodiment of the present invention, the boron undoped sige layer in the middle of being provided with between source/leakage and contacting metal is significantly to reduce being with misalignment and contact resistance.
In a specific example embodiment, in the middle of disposing the contact of boron doped germanium layer present the band misalignment be decreased to 0.2eV and corresponding contact resistance reduce approximately 3 times (with respect to similar configuration with routine contact lamination, but do not have the middle boron undoped sige layer between source/drain region and contacting metal).Transmission electron microscopy (TEM) cross section or assisting ion mass spectrum are learned (SIMS) distribute germanium concentration in the vertical stack that can be used to show whole membrane structures, because can be easily distribution and the Germanium concentration profile of the extension alloy of silicon and SiGe be distinguished.
Therefore, according to the transistor arrangement of embodiments of the invention configurations provide surmount conventional structure with respect to the more improvement of low contact resistance.Some such embodiment make the good contact property of germanium be combined with the defect semiconductor transistor properties of Si and SiGe, so that follow-on low resistance contact to be provided.Can realize selectivity by variety of way.For example, in one embodiment, by in the territory crested of p-type MOS device (PMOS) depositional stage chien shih nmos area, can provide the selectivity to N-shaped MOS (NMOS) source/leakage position.In another embodiment, NMOS and PMOS zone can be opened simultaneously, but deposition only occurs in the PMOS zone by groove.Advantage herein is, do not have low-melting germanium during the common relatively high heat budget step of MOS flow process front end.After groove processing and germanium deposition, and according to specific such example embodiment, this structure can not experience and surpass 500 ℃ temperature, so the germanium cover layer can not be among the danger of melting and/or other mode deteriorate performance.As will further understanding ground according to the disclosure, selectivity can comprise natural selection.For example, although boron doped germanium is grown on p-type SiGe (or silicon) source/drain region, it can not be grown on the dielectric surface such as silicon dioxide (SiO2) or silicon nitride (SiN); It also can not be grown on the silicon of the heavy phosphorus doping that exposes in the N-shaped district.
According to the disclosure, many transistor arrangement and suitable manufacturing process will be apparent, comprise the channel structure of plane and nonplanar transistor arrangement (for example double grid and tri-gate transistor structure) and strain and non-strain.As describing herein, any amount of such architectural feature and material system can use together in conjunction with the germanium cover layer.Transistor arrangement can comprise p-type source/drain region, N-shaped source/drain region or N-shaped and p-type source/drain region.In some example embodiment, transistor arrangement is included in source/drain region or the pure germanium film (for example having those germanium films that are less than 10% silicon) of extension (polycrystalline) replacement source/drain region, SiGe alloy or nominal of the dopant injection of the silicon in the MOS structure.According to embodiments of the invention, in arbitrary such realization, can on source/drain region, directly form cover layer or the cap rock of boron doped germanium.Then contacting metal (or a series of metal) can be deposited, and subsequently reaction (annealing) can be carried out to form germanium metal compound source and drain contact.As understanding, this contact can be implemented as the one or more lamination that comprises in silicide layer, adhesive layer and/or the metal bed course.If necessary, also can on the other parts (such as polysilicon gate and/or ground joint zone) of transistor arrangement, directly form boron doped germanium cover layer.
Known, MOS transistor can comprise source and leakage tip region, and these zones are designed to reduce transistorized overall electrical resistance and strengthen simultaneously short-channel effect (SCE).Routinely, these tip region are a plurality of parts of substrate, and utilization injection and diffusion technique have been injected the dopant such as boron or carbon in these a plurality of parts.The source tip region forms in the zone between source region and channel region.Similarly, form in the zone of leakage tip region between drain region and channel region.Some embodiments of the present invention dispose the tip region that such routine forms.In other example embodiment, adopt manufacturing technology to expand most advanced and sophisticated (SET) transistor of self aligned extension, to realize very the theoretical limit near uniaxial strain.For example, this can pass through in source and drain region and the deposition of the selective epitaxial in their corresponding tip region, realizes to form the double-layer structural that is coated with by the boron doped silicon of the cap rock of boron doped germanium layer or SiGe (being used for source/drain region) in source/leakage and corresponding tip region.But in some example embodiment, germanium can be different with boron concentration, and in the scope of 100 atomic percents, and boron concentration is at 1E20cm at 20 atomic percents for germanium concentration -3To 2E21cm -3Scope in (for example germanium concentration surpasses 50 atomic percents and boron concentration surpasses 2E21cm -3).Note, boron doped germanium layer can be arranged in the tip region, but only is arranged in other embodiments (not in tip region) on source/drain region.
In other other example embodiment, the optional thin resilient coating that can use germanium concentration with gradual change and/or boron concentration as back lining at the bottom of and the boundary layer between source/drop ply (for example silicon or SiGe).Similarly, can use the thin resilient coating of germanium concentration with gradual change and/or boron concentration as the boundary layer between source/drop ply and the boron doped germanium cap rock.In other other embodiment, boron doped germanium cover layer or source/drop ply self can have with germanium and/or the boron concentration of the gradual change of optional resilient coating similar manner.In the situation that arbitrary such because boron is diffused in suppressed in the germanium (concentration is higher, relatively suppresses stronger), can be in germanium the boron of doped with high concentration, this then cause lower dead resistance and can not make most advanced and sophisticated steepness deteriorated.In addition, owing to having reduced schottky barrier height, contact resistance is reduced.
Architecture and method
Figure 1A illustrates the MOS device 100A that is formed on according to an embodiment of the invention on the substrate 102 and disposes the boron doped germanium layer between source/drop ply and contacting metal.Particularly, boron doped germanium layer 117 is arranged between source layer 110 and the contacting metal 125, and boron doped germanium layer 119 is arranged between drop ply 112 and the contacting metal 127.Can utilize any amount of routine techniques to form source region 110 and drain region 112.For example, in this example embodiment, by etch substrate then extension ground depositing silicon or silicon germanium material (for example germanium concentration is in the scope of for example 10 to 70 atomic percents), and form source region 110 and drain region 112.
Gate stack 122 forms on the channel region 120 of transistor 100A.As can further finding out, gate stack 122 comprises gate dielectric layer 106 and gate electrode 104, and interval body 108 forms near gate stack 122.Under some sample situations and depend on arrangement nodes, interval body 108 produces the approximately distance of 10 to 20 nanometers (nm) between the edge of gate dielectric layer 106 and each the edge in source and the drain region 110/112.In this space, can form source cusp field 110A and leak cusp field 112A.In this example embodiment, cusp field 110A/112A by typically based on inject-technique of diffusion forms and overlapping with interval body 108, and can be with gate dielectric layer 106 overlapping or thereunder diffusion for example less than the distance of 10nm.Forming based on injecting-during tip region 110A, the 112A of diffusion, the dopant such as boron or carbon can being injected in source region 110 and the drain region 112.Then transistor 100A is annealed so that dopant spreads to channel region 120.Also can come further dopant to be injected in those zones between gate dielectric layer 106 and the source/drain region 110/112 with angled ion implantation technique.The tip based on injecting-spreading like this forms technique and does not generally introduce strain at channel region.
In either case, and it will be appreciated that according to the disclosure, whether transistor arrangement has strain or unstrained raceway groove or whether have source-leakage tip region or do not have source-leakage tip region is not relevant especially with each embodiment of the present invention, and such embodiment is not intended to be subject to any specific such architectural feature.On the contrary, any amount of transistor arrangement and type can be benefited from as described herein boron doped germanium cover layer of employing.The technology that this paper provides can with for example conventional dopant Implanted Silicon, the source of rising/leakages, strain SiGe (or other suitable material) and below the gate electrode dielectric, extend or any deposition extension tip (being sometimes referred to as source-leakage extension) of separating with the vertical line that is limited by the gate electrode dielectric compatible.
Generally after formation source/drain region 110/112 and before forming contact 125/127, germanium cover layer 117/119 is set.The thickness of this cover layer 117/119 can be different to another embodiment from an embodiment, but in an example embodiment, this thickness is at 50 to 250 dusts
Figure BDA0000349060010000061
Scope in.The boron concentration of cover layer 117/119 also can be different, but in an example embodiment, this boron concentration is at 1E20cm -3To 2E21cm -3Scope in (for example surpass 2E20cm -3).Can be in the source/leakage 110/112 zone (and/or other zone as required, such as polysilicon gate or ground joint zone) on sedimentary cover 117/119 optionally.Can provide cover layer 117/119 (for example chemical vapour deposition (CVD), molecular beam epitaxy etc.) with any amount of suitable deposition technique.According to an example embodiment, contacting metal 125 and 127 each include the lamination of nickel silicide layer, titanium nitride adhesive layer and tungsten contact pad, but can understand according to the disclosure, also can use any amount of contacting metal configuration.But the Application standard deposition technique arranges contacting metal 125/127.
Figure 1B illustrates being formed on the substrate 102 and disposing the example MOS device 100B of the boron doped germanium layer 117/119 between source/drop ply 110/112 and contacting metal 125/127 according to another embodiment of the present invention.This example arrangement comprises the source and leaks extension most advanced and sophisticated (being referred to as in this article the extension tip).More specifically, MOS transistor 100B uses undercutting to be etched with permission source region 110 and extend below interval body 108 in drain region 112, and extends below gate dielectric layer 106 in some cases.A plurality of parts of extending (also may below gate dielectric layer 106) below the interval body 108 in source/drain region 110/112 are collectively referred to as respectively the most advanced and sophisticated 110B of source extension and leak the most advanced and sophisticated 112B of extension.Source and the most advanced and sophisticated 110B/112B of leakage extension substitute the described tip region 110A/112A based on injection/diffusion about Figure 1A.According to an embodiment, can for example come formation source/drain region 110/112 and the most advanced and sophisticated 110B/112B of source/leakage extension by etch substrate 102, etch substrate 102 can comprise incision interval body 108 (and possible gate dielectric layer 106), then deposit to provide for example in-situ doped silicon, germanium or SiGe with filling source/drain region 110/112 and the most advanced and sophisticated 110B/112B of source/leakage extension, as shown in Figure 1B with selective epitaxial.Note, shown in further among Figure 1B, extension is filled and can be raise with respect to the surface of substrate 102, but also can use uninflated configuration.Germanium cover layer 117/119 and contacting metal 125/127 can be realized as described with respect to Figure 1A before.
Fig. 1 C illustrates being formed on the substrate 102 and disposing the MOS device 100C of the boron doped germanium layer 117/119 between corresponding source/drop ply 110/112 and contacting metal 125/127 according to another embodiment of the present invention.By the dopant such as boron is injected source region 110 and the drain region 112 that substrate forms this example embodiment.Gate stack 122 forms at the channel region 120 of transistor 100C, and does not comprise in this example sidewall 108.The transistor arrangement of this example does not comprise undercutting or the tip region such with embodiment shown in Figure 1A and the 1B yet.Germanium cover layer 117/119 and contacting metal 125/127 can be realized as described with respect to Figure 1A before.
Can realize multiple other modification and feature according to the transistor arrangement of embodiments of the invention configuration.For example, in one or more positions of this structure, can use the resilient coating of gradual change.For example, substrate 102 can be the silicon fiml of silicon substrate or silicon-on-insulator (SOI) substrate or the MULTILAYER SUBSTRATE that comprises silicon, SiGe, germanium and/or III-V compound semiconductor.Therefore, as example, having silicon or silicon-Germanium substrate 102 and be arranged in source/drain region 110/112 and the embodiment of the boron doped SiGe filling of the original position of the most advanced and sophisticated 110B/112B of source/leakages extension, can at the bottom of the back lining 102 and source/leakage material between resilient coating is set.In such embodiment, this resilient coating can be boron doping (or intrinsic) germanium-silicon layer of gradual change, wherein germanium concentration is from being gradient to 100 atomic percents (or near 100 atomic percents, such as surpassing 90 atomic percents or 95 atomic percents or 98 atomic percents) with basic horizontal compatible at the bottom of the back lining.Boron concentration in this resilient coating can be fixed (for example being in high level), or for example from being in or (for example surpassing 2E20cm with basic concentration gradual change compatible at the bottom of the back lining to the high concentration of expectation -3).Note, " compatible " not necessarily requires overlapping (for example the germanium concentration at the bottom of the back lining can be 0 to 20 atomic percent, and the initial germanium concentration of resilient coating can be 30 to 40 atomic percents) on the concentration level as used herein.In addition, as used herein, " fix " with respect to the term of concentration level and to be intended to represent relatively constant concentration level (for example the least concentration level in this layer and the maximum concentration level in this layer differ in 10%).According to implication more generally, the fixed concentration level is intended to represent not exist the graded concentration level of having a mind to cause.The thickness of this resilient coating can be depending on many factors (such as the concentration range that is cushioned) and difference, but in certain embodiments, the thickness of this resilient coating arrives 30
Figure BDA0000349060010000071
Scope in, arrive such as 50
Figure BDA0000349060010000072
(for example Or
Figure BDA0000349060010000074
).As will be further understood that according to the disclosure, such graded buffer layer has reduced schottky barrier height valuably.
Alternatively, replace using the thin resilient coating between the most advanced and sophisticated 110B/112B of substrate 102 and source/drain region 110/122 and source/leakage extension, source/leakage material itself can be according to similar mode gradual change.For example and according to an example embodiment, the most advanced and sophisticated 110B/112B of boron doped SiGe source/drain region 110/112 and source/leakage extension may be configured with from being gradient to the germanium concentration of 100 atomic percents with basic horizontal concentration (for example in the scope of 30 to 70 atomic percents) compatible at the bottom of the back lining.In some such embodiment, the scope of the boron concentration in this boron doped germanium layer can be for example from being in or (for example surpassing 2E20cm with basic concentration compatible at the bottom of the back lining to the high concentration of expectation -3).
In other embodiments, resilient coating can be arranged between source/leakage material and the boron doped germanium cover layer 117/119.In such embodiment, source/leakage material is to have the fixedly boron doped SiGe layer of germanium concentration (for example in 30 to 70 atomic percent scopes), and this resilient coating can be that thin SiGe layer (for example 30 arrives
Figure BDA0000349060010000081
Arrive such as 50 ), this thin SiGe layer has from the basic horizontal concentration gradient compatible with the boron doped SiGe layer of bottom to 100 atomic percents the germanium concentration of (or near 100 atomic percents, such as surpassing 90 atomic percents or surpassing 95 atomic percents or surpass 98 atomic percents).In the situation that some are such, the boron concentration in this resilient coating can be fixed in the high level of expectation, or for example can (for example surpass 1E20cm from the high concentration that is in or the basic concentration gradual change compatible with bottom SiGe layer extremely expected -3, surpass 2E20cm -3Or above 3E20cm -3).Alternatively, not the resilient coating that utilizes between source/leakage material and the boron doped germanium cover layer 117/119, can make in a similar manner gradual change of cover layer 117/119 itself.For example and according to an example embodiment, boron doped cover layer 117/119 may be configured with the germanium concentration that is gradient to 100 atomic percents (or near 100 atomic percents) from the basic horizontal concentration compatible with at the bottom of the back lining and/or source/drain region (for example in the scope of 30 to 70 atomic percents).Boron concentration in 117/119 layer of this cover layer can be fixed in the high level of expectation, or can be for example from being in or the basic concentration compatible with at the bottom of the back lining and/or source/drain region (for example surpasses 2E20cm to the expectation high level -3) scope in.
Therefore, provide the low contact resistance architecture that is used for multiple transistor device.These devices can partly utilize isotropism undercutting in any amount of common process (such as by gate oxide, polysilicon gate electrode, thin interval body) and the source/drain region (or ammoniacal etchant has facet fin recess to form in the single crystalline substrate, or other suitable being etched with forms the fin recess) to form.According to some embodiment, can provide in-situ doped silicon or the complete germanium-silicon layer of strain with epitaxial deposition optionally, have or the cuspidated source/drain region of tool not with formation.As illustrated before, can use optional resilient coating.Also can use any suitable high k to replace metal gate (RMG) technological process, wherein high-k dielectric is replaced conventional gate oxide.For example utilizing, the silicidation technique of nickel, nickel-platinum or titanium and so on (being accompanied by or not following the pre-amorphous injection of germanium) can be used to form the low resistance germanide.For example; can use the technology that provides herein benefiting any technology node (for example 90nm, 65nm, 45nm, 32nm, 22nm, 14nm and 10nm transistor and lower), and claimed the present invention is not intended to be subject to any specific such node or the scope of device geometries.According to the disclosure, other advantage will be apparent.
Fig. 2 is the method that is used to form according to an embodiment of the invention the transistor arrangement with low contact resistance.Fig. 3 A to 3I is illustrated in and forms when carrying out this method and according to the example structure of some embodiment.
As finding out, the method starts from forming gate stack (202) in Semiconductor substrate, can form the MOS device such as the PMOS transistor on this Semiconductor substrate.For example, can utilize body silicon or this Semiconductor substrate of silicon-on-insulator Configuration.In other implementation, this Semiconductor substrate can utilize substitution material to form, this substitution material can with or can be and the silicon combination, such as germanium, SiGe, indium antimonide, lead telluride, indium arsenide, indium phosphide, GaAs or gallium antimonide.On meaning more generally, according to embodiments of the invention, can use any material that can serve as the basis that makes up semiconductor device, gate stack can be as conventional like that or utilize any suitable custom technology to form.In some embodiments of the invention, can patterned gate dielectric layer and gate electrode layer form this gate stack by depositing then.For example, under a kind of sample situation, can utilize such as chemical vapour deposition (CVD) (CVD), ald (ALD), spin-on deposition (SOD) or physical vapour deposition (PVD) (PVD) conventional depositing operation with the gate dielectric layer code-pattern be deposited on the Semiconductor substrate.Also can use alternative deposition technique, for example can heat growth gate dielectric layer.For example, can form grid dielectric material from the material such as silicon dioxide or high-k dielectric material.The example of high k grid dielectric material for example comprises: hafnium oxide, hafnium silicon oxide, lanthana, lanthana aluminium, zirconia, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, yittrium oxide, aluminium oxide, lead oxide scandium tantalum and lead niobate zinc.In some specific example embodiment, the thickness of high k gate dielectric layer can be approximately
Figure BDA0000349060010000091
Arrive approximately
Figure BDA0000349060010000092
Between (for example Extremely
Figure BDA0000349060010000094
).Generally speaking, the thickness of gate dielectric layer should be enough to make gate electrode and adjacent source and drain contact electrical isolation.In other embodiments, can carry out additional processing to high k gate dielectric layer, such as annealing in process, to improve the quality of high k material.Next, can utilize the similar deposition technique such as ALD, CVD or PVD to deposit gate material at gate dielectric layer.In some such specific embodiments, gate material is polysilicon or metal level, but also can use other suitable gate material.This gate material can be to be removed after a while to be used for replacing the expendable material of metal gate (RMG) technique, and in some example embodiment, the thickness of this gate material exists
Figure BDA0000349060010000101
Extremely
Figure BDA0000349060010000102
Scope between (for example
Figure BDA0000349060010000103
).Then can carry out conventional Patternized technique and remove a plurality of parts of gate electrode layer and gate dielectric layer with etching to form gate stack, as shown in Figure 3A.As seen, Fig. 3 A illustrates substrate 300, can form gate stack on substrate 300.In this example embodiment, gate stack comprises gate dielectric layer 302 (can be high k grid dielectric material) and altered sacrificial gate electrode 304.In a kind of specific example situation, this gate stack comprises silicon dioxide gate dielectric layer 302 and polygate electrodes 304.This gate stack also can be included in the grid hard mask layer 306 that some benefit or purposes are provided during the processing, not affected by follow-up ion implantation technology such as grill-protected electrode 304.This hard mask layer 306 can utilize typical hard mask material to form, such as silicon dioxide, silicon nitride and/or other conventional dielectric substance.Fig. 3 A further is illustrated in the interval body 310 that forms on this lamination either side.For example, interval body 310 can utilize conventional material or other suitable spacer material such as silica, silicon nitride to form.Generally can select based on formed transistorized designing requirement the width of interval body 310.Yet, as describing herein, according to some embodiment, the width of sufficiently high boron doped germanium content (boron will can not be diffused in the raceway groove) interval body 310 in given source/leakage tip region, the width of interval body 310 can not be limited by the source to be limited with the design that the formation of leaking the extension tip applies.
Further with reference to figure 2, after gate stack formed, the method continued to define the source/drain region (204) of transistor arrangement.As illustrated before, can utilize any amount of suitable technique and configuration to come realization source/drain region.For example, source/drain region can be that inject, etched and extension is filled, raise, can be silicon or SiGe alloy, p-type and/or N-shaped, and the diffusion zone with plane or fin-shaped.In the example embodiment shown in Fig. 3 A, substrate 300 is etched so that chamber 312/314 and corresponding tip region 312A/314A, this etching process undercutting gate dielectric 302 to be provided.Fig. 3 B is illustrated in chamber 312/314 and tip region 312A/314A has been filled to provide source/drain region 318/320 and tip region 318A/320A substrate 300 afterwards.According to some example embodiment, the silicon that source and chamber, drain region 312/314 and their corresponding tip region 312A/314A are in-situ doped or SiGe fill, and form thus source region 318 (and the most advanced and sophisticated 318A of extension) and drain region 320 (and leaking the most advanced and sophisticated 320A of extension).(for example surpass 2E21cm with respect to material (for example silicon, SiGe, III-V material), dopant -3Boron or other suitable concentration of dopant) and size (for example the thickness of source/drop ply can be for example 50 in the scope of 500nm, so that source/drain region concordant or that raise to be provided), can use any amount of source/drop ply configuration at this.
As illustrated before, some such embodiment can be included between source/drop ply and the substrate or source/leakage and boron doped germanium cover layer between thin resilient coating.For example, in the example embodiment as shown in Fig. 3 B further as seen, sedimentary origin resilient coating 313 and leakage resilient coating 315 before sedimentary origin/leakages material.In certain embodiments, resilient coating 313 and 315 can be the boron doped germanium-silicon layer of gradual change, wherein the germanium component can be from basic horizontal concentration gradient to 100 atomic percent compatible with 300 materials at the bottom of the back lining (or near 100 atomic percents, as described earlier).Boron concentration is suitably gradual change also.According to the disclosure, multiple resilient coating scheme will be apparent.
Further with reference to figure 2, after having defined source/drain region, the method continue with in the source of transistor arrangement/drain region deposition boron doped germanium (206).Fig. 3 C illustrates boron doped germanium layer 317/319.In some example embodiment, boron doped germanium layer 317/319 can be in epitaxial deposition in the one or more layer, boron doped germanium layer 317/319 has the germanium concentration that surpasses 90 atomic percents, but will understand according to the disclosure, can use other suitable concentration level (for example above 91 atomic percents or above 92 atomic percents or above 98 atomic percents or above 99 atomic percents or real pure germanium).Such as before explanation, this germanium concentration can be fixed or gradual change, to be increased to high level (for example surpassing 90 atomic percents) from basic horizontal (near substrate 300).In some such embodiment, boron concentration can surpass 1E20cm -3, such as being higher than 2E20cm -3Or be higher than 2E21cm -3Also but gradual change (for example surpasses 1E20cm to increase to high level from the basic horizontal near substrate 300 -3Or above 2E20cm -3Or above 3E20cm -3, surpass 2E21cm -3).The germanium concentration of bottom source/drain region 318/320 fix or relatively low embodiment in, can come with the resilient coating of gradual change better as the interface between source/drain region 318/320 and the boron doped germanium layer 317/319, as illustrated before.According to some specific example embodiment, the thickness of boron doped germanium cap rock 317/319 can have and for example 50 arrives
Figure BDA0000349060010000111
Thickness in the scope, but alternate embodiment can have as according to the disclosure with apparent other layer thickness.
In certain embodiments, CVD technique or other suitable deposition technique can be used to deposit 206 or otherwise form boron doped germanium layer 317/319.For example, can in CVD or quick hot CVD (RT-CVD) or low pressure chemical vapor deposition (LP-CVD) or ultra high vacuum CVD (UHV-CVD) or gas source molecular beam epitaxy (GS-MBE) equipment, utilize the predecessor of germanic and boron (such as germane (GeH 4) or two germane (Ge 2H 6) and diborane (B2H5) or boron difluoride (BF 2)) carry out the deposition 206.In some such embodiment, may there be the carrier gas (for example, predecessor is diluted with the 1-5% concentration of carrier gas) such as for example hydrogen, nitrogen or rare gas.Also may there be etching gas, such as for example: based on the gas of halogen, such as hydrogen chloride (HCl), chlorine (Cl) or hydrogen bromide (HBr).The basic deposition of germanium and boron doped germanium may realize on the condition of wide region, utilize in 300 ℃ to 800 ℃ scope for example depositing temperature (for example 300-500 ℃) and under the reactor pressure in the scope of 760Torr of 1Torr for example.Germanium is optionally natural, because it is deposited on silicon or the sige alloy, and is not deposited on other material such as silicon dioxide and silicon nitride.Because this natural selectivity is not complete perfection, as described above, can improve with the etchant of low discharge the selectivity of deposition.In carrier and the etchant each can have the flow velocity (typically, need to be no more than the flow velocity of 100SCCM, but some embodiment may need more high flow rate) in 10 to 300SCCM scope.In a specific example embodiment, can utilize the GeH that in hydrogen, dilutes with 1% concentration 4And 100 and 1000SCCM between scope in flow velocity under carry out deposition 206.In-situ doped for boron can be used diluted B 2H 6(B for example 2H 6Can be in hydrogen with 3% concentration be diluted and its flow velocity 100 and 600SCCM between scope in).In some such specific example situations, with for example 10 and 100SCCM between scope in flow velocity add HCl or Cl 2Etchant, to improve the selectivity of deposition.
As understanding according to the disclosure, the selectivity that deposits boron doped germanium layer 317/319 can be different according to expectation.For example, in some cases, boron doped germanium layer 317/319 is 318/320 deposition or only a part of 318/320 (rather than total) deposits in source/drain region in source/drain region only.Can come optionally sedimentary deposit 317/319 with any amount of mask/patterning techniques.In addition, other embodiment can benefit from floor 317/319 and cover for example polycrystalline grid region or ground joint district.As understanding according to the disclosure, according to some example embodiment, can use high germanium concentration (for example surpassing 90 atomic percents to pure germanium) and high boron concentration (for example to surpass 2E20em -3) combination come in source and drain region to realize significantly lower contact resistance in (and other zone of expectation low contact resistance, such as the ground joint zone).In addition, and as before illustrated, fully suppressed by pure germanium because boron spreads, no matter how high near the boron concentration of raceway groove, under thermal annealing subsequently, all can realize there is not disadvantageous SCE deteriorated.The higher concentration of the germanium by the contact surface place can realize that also barrier height reduces.In some example embodiment, can use above 95 atomic percents and height to the germanium concentration of pure germanium (100 atomic percent) and realize such benefit.
Further with reference to figure 2, after boron doped germanium layer 317/319 was set, the method continued to deposit (208) dielectric capping layers 317/319.Fig. 3 D illustrates the dielectric 322 concordant with the hard mask 306 of gate stack, but not necessarily concordant.This dielectric can configure according to various ways.In certain embodiments, utilize SiO 2Or other low K dielectrics material is realized dielectric 322.In other embodiments, utilize SiN lining and one or more layers SiO subsequently 2Or any combination of nitride, oxide, oxynitride, carbide, oxycarbide or other suitable dielectric substance realizes dielectric 322.The dielectric 322 that is called interlayer dielectric (ILD) can complanation as usually.For example, other example dielectric substance for example comprises: oxide (CDO), the organic polymer such as octafluorocyclobutane or polytetrafluoroethylene, fluorine silex glass (FSG) and the organosilicate such as silsesquioxane, siloxanes or organic silicate glass that carbon mixes.In some example arrangement, the ILD layer can comprise that hole or other space are with its dielectric constant of further reduction.
Then, used therein replacement metal gate (RMG) technique and best in Fig. 3 E shown in some embodiments of the present invention in, the method can further comprise utilizes the conventional etch process of realizing to remove gate stack (comprising high k gate dielectric layer 302, altered sacrificial gate electrode 304 and hard mask layer 306).In substituting implementation, only remove sacrificial gate 304 and hard mask layer 306.Fig. 3 E illustrates the groove opening that forms according to such embodiment when etching away gate stack.If removed gate dielectric layer, then the method can continue new gate dielectric to be deposited in the groove opening (being labeled as 324 in Fig. 3 F).Can use such as any suitable high-k dielectric material of describing before those, such as hafnium oxide at this.Also can use identical depositing operation.The replacement of gate dielectric layer can be used, for example solving any damage that original gate dielectric layer occurs during applying dry ecthing and wet etching process, and/or the grid dielectric material that k or sacrificial dielectric material replace with high k or other expectation will be hanged down.As further illustrating among Fig. 3 F, the method can further continue to deposit to metal gate electrode layer 326 in the groove and deposit on the gate dielectric layer 324.The metal deposition process of useful routine forms metal gate electrode layer, such as CVD, ALD, PVD, chemical plating or plating.Metal gate electrode layer can comprise for example p-type workfunction metal (such as ruthenium, palladium, platinum, cobalt, nickel) and conducting metal oxide (for example ruthenium-oxide).In some example arrangement, can deposit two or more metal gate electrode layers.For example, can in gate groove, deposit workfunction metal and then deposit suitable metal gate electrode filling metal (such as aluminium or silver).
Further with reference to figure 2, dielectric layer 322 (and RMG technique of any expectation) is set afterwards on layer 317/319, the method continues with etching (210) with formation source/drain contact groove.Can use any suitable dry ecthing and/or wet etching process.Fig. 3 G illustrates the source after etching is finished according to an example embodiment/drain contact groove.Then the method continues to deposit (212) contact resistance and reduces metal and annealing, to form silicide/germanide, then deposits (214) source/drain contact plug.Fig. 3 H illustrates contacting metal 325/327, and contacting metal 325/327 comprises silicide/germanide in certain embodiments, but other embodiment can comprise other layer (for example adhesive layer).Fig. 3 I illustrates contact plug metal 329/331, contact plug metal 329/331 comprises aluminium in certain embodiments, but can utilize conventional depositing operation that any suitable conductive contact metal or alloy is used for contact plug 329/331, such as other alloy or the titanium of silver, nickel-platinum or nickel-aluminium or nickel and aluminium.For example, the silication of other alloy by utilizing nickel, aluminium, nickel-platinum or nickel-aluminium or nickel and aluminium or titanium (following or do not follow the pre-amorphous injection of germanium to form the low resistance germanide) can realize the germanium of source and drain contact/metallization 212.Boron doped germanium layer 317/319 allows metal-germanide to form (for example nickel-germanium).Germanide allows significantly lower schottky barrier height and the contact resistance that is better than the improvement of common metal silicide system (to comprise R Ext).For example, conventional transistor typically uses source/leakage SiGe epitaxy technique, and wherein germanium concentration is in the scope of 30-40 atomic percent.Such conventional system presents the approximately R of 140Ohm*um ExtValue is subject to epitaxial silicon compound interface resistance, and this interface resistance is high and may hinder following pitch expansion.Some embodiments of the present invention allow the R in the PMOS device Ext(for example approximately 2 times or better improve the R of all according to appointment 70Ohm*um of remarkable improvement Ext), can support better the expansion of PMOS device.Therefore, have according to an embodiment of the invention the source that disposes boron doped germanium cap rock 317/319/leakage, wherein boron concentration surpasses 1E20cm-3, germanium concentration and surpasses 90 atomic percents and high at the interface between source/drain region 318/320 and contacting metal 325/327 to pure germanium (100 atomic percent) or otherwise can present the R that is lower than 100Ohm*um near the transistor of pure germanium (100 atomic percent) ExtBe worth, and be lower than in certain embodiments the R of 90Ohm*um ExtValue, and the R that is lower than in some cases 80Ohm*um ExtValue, and be lower than in some cases 75Ohm*um or lower R ExtValue.
Fig. 4 is the method that is used to form the transistor arrangement with low contact resistance according to another embodiment of the present invention.Fig. 5 A to 5F is illustrated in and forms when carrying out this method and according to the example structure of some embodiment.As finding out, this example transistor structure comprises p-type and N-shaped source and drain region (being labeled as respectively p-S/D and n-S/D), and boron doped germanium only optionally is deposited in the p-type district.Substantially, the method is similar to the method with reference to figure 2 and 3A-H description, and difference is, at deposition dielectric 322 and after being etched with the formation contact trench, carries out the deposition of boron doped germanium layer 317/319 on source/drain region.
The method comprises utilizes standard to process to form (402) gate stack and a plurality of p-S/D of definition (404) and n-S/D zone, such as best illustrating among Fig. 5 A.In certain embodiments, can mix p-S/D and n-S/D zone so that the selectivity with respect to the expected degree of boron doped germanium to be provided.The method also is included in Direct precipitation (406) dielectric 322 on p-S/D and the n-S/D zone, as shown in Fig. 5 B.The method continues with etching (408) to form p-S/D and n-S/D zone contact trench, then with boron doped germanium layer 317/319 selectivity deposition (410) in groove and be deposited on (the application scenario of depending on desired function and transistor arrangement, p-S/D zone, may have one or more p-S/D zone) on, as illustrating best among Fig. 5 C and the 5D.Can utilize any suitable depositing operation (such as selective epitaxial) to carry out deposition 410.In case be provided with layer 317/319, the method continues then to deposit (414) source/drain contact plug 329/331, shown in Fig. 5 E and 5F with depositing (412) contacting metal 325/327 on the layer 317/319 and on the n-S/D zone of any exposure.This alternative method provides the same benefits of the contact resistance of improvement, but has more selectivity in the occasion of the boron doped germanium of deposition.According to the disclosure, utilize mask/patterning and the optionally any suitable combination of deposition technique, other such selectivity depositing operation will be apparent.As understanding, the relevant discussion with respect to the similar part of the method can be suitable for equally at this before.
The FinFET configuration
As everyone knows, FinFET is the transistor that the faciola (being commonly referred to as fin) at semi-conducting material is set up on every side.This transistor comprises pattern field effect transistor (FET) node, comprises grid, gate dielectric, source region and drain region.The conducting channel of this device is positioned on the outside of fin, the gate dielectric below.Particularly, electric current flows along the sidewall (perpendicular to the sidewall of substrate surface) of fin and along the top (being parallel to substrate surface) of fin.Because the conducting channel of such configuration is positioned at three different outer surface level zones of fin substantially, so such FinFET design is sometimes referred to as three gate FinFETs.The FinFET of other type configuration also is available, and such as so-called double grid FinFET, wherein conducting channel mainly only is positioned at two sidewalls along the fin top of fin (not along).
Fig. 6 illustrates the according to one embodiment of present invention stereogram of the example three grid architectures of configuration.As can be seen, this tri-gate devices comprises substrate 600, and this substrate 600 has semiconductor bodies or the fin 660 (by a dotted line expression) that passes insulation layer 610,620 extensions from substrate 600.Gate electrode 640 forms to form 3 grid on 3 surfaces of fin 660.Hard mask 690 forms on gate electrode 640.Gate isolation body 670,680 forms at the opposing sidewalls place of gate electrode 640.
The source region is included in the epitaxial region 631 that forms on the interface, source 650 of depression and fin 660 sidewall, and the epitaxial region 631 that forms on the interface, source 650 that the drain region is included in depression and the relative fin 660 sidewall (not shown).Cap rock 641 is deposited on the epitaxial region 631.Note, boron cap rock 641 can be arranged in (tip) zone of depression, but only is arranged in other embodiments (not in sunk area) on source/drain region.In one embodiment, isolated area 610, the 620th utilizes shallow trench isolation that routine techniques forms from (STI) district, and for example etch substrate 600 to be to form groove, then on groove the deposition oxide material to form sti region.Isolated area 610,620 can be made by any suitable dielectric/insulating material, such as SiO 2The before discussion about substrate 102 is suitable for (for example substrate 600 can be silicon substrate, SOI substrate or MULTILAYER SUBSTRATE) equally at this.
As understanding according to the disclosure, the technique of applicable routine and formation technology are made the FinFET transistor arrangement.Yet, according to one example embodiment, for example, the double-decker of epitaxial region 631 and cap rock 641 can utilize the in-situ doped silicon that covered by boron doped germanium (641) or SiGe (631) (having optional germanium between two bilayers and/or the resilient coating of boron gradual change) to realize.Can be used to be converted to boron doped germanium cap rock 641 from the basic horizontal germanium compatible with epitaxial region 631/boron concentration such as illustrated before, such resilient coating.Alternatively, can directly in epitaxial region 631 and/or cap rock 641, realize germanium and/or boron concentration gradient, rather than in the graded buffer layer of centre is arranged, realize.As will be further understood that, notice that the replacement scheme of three grid configuration is the double grid architecture, it is included in the dielectric isolation layer on the fin 660.
Fig. 7 illustrates the drawing of cutting apart in batches, illustrates according to the transistor arrangement of embodiments of the invention configuration and does not configure the contact resistance of the standard crystal tubular construction of cap rock.The transistor arrangement that is associated with the high resistance number that surpasses 0.18 all is that realize in the PMOS source/drain region that utilizes the standard SiGe alloy of Direct precipitation contacting metal on it to raise.The transistor arrangement that is associated with 0.107 and lower resistance number all is similar realization, but according to a plurality of embodiment of the present invention, has added the boron doped germanium cap rock between source/drain region and contacting metal.Table 1 illustrates from having and do not have the as described herein resulting initial data quantile of test of the example structure of boron doped germanium cap rock.
Figure BDA0000349060010000171
Table 1
As can be seen, this example actual improve (reducing) that shows than the contact resistance of approximately three to six times (3X is to 6X) of conventional transistor arrangement in bulk.Unit is ohm/arbitrary area.
Will be apparent according to the disclosure by other improvement that applicable boron doped according to an embodiment of the invention germanium cap rock is realized.Particularly, according to some example embodiments of the present invention, the germanide material of gained and schottky barrier height improve 2 times of R that realize leaking with respect to conventional SiGe source the PMOS device ExtImprove.As everyone knows, schottky barrier height is the potential barrier conduct semiconductor-metal being used for of tying.The size of schottky barrier height has reflected the mismatch in the energy position of Fermi level on the semiconductor-metal interface and semi-conductive majority carrier belt edge.For the p-type semiconductor-metal interface, schottky barrier height is poor between Fermi level and the semi-conductive valence band maximum.
Example system
Fig. 8 illustrates the according to one embodiment of present invention calculation element 1000 of configuration.As seen, calculation element 1000 comprises motherboard 1002.Motherboard 1002 can comprise a plurality of assemblies, includes but not limited to processor 1004 and at least one communication chip 1006, but each entity ground wherein and electrically be coupled to motherboard 1002 or be integrated in the motherboard 1002.As understanding, for example, motherboard 1002 can be any printed circuit board (PCB), also is mounted in the daughter board on the mainboard or installs unique plate of 1000 no matter it is mainboard.Depend on its application, calculation element 1000 can comprise one or more other assemblies, but this one or more other assembly entity ground and electrically be coupled to motherboard 1002.These other assemblies can include but not limited to volatile memory (for example DRAM), nonvolatile memory (for example ROM), graphic process unit, digital signal processor, encryption processor, chipset, antenna, display, touch-screen display, touch screen controller, battery, audio coder-decoder, video coder-decoder, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, loud speaker, camera and mass storage device are (such as hard disk drive, compact disk (CD), digital versatile disc (DVD) etc.).The arbitrary assembly that comprises in the calculation element 1000 can comprise as described in this article one or more transistor arrangements.In certain embodiments, several functions can be integrated into (for example, attention communication chip 1006 can be the part of processor 1004 or be integrated in the processor 1004) in one or more chips.
Communication chip 1006 realizes that radio communications are to be used for going to calculation element 1000 and from the transfer of data of calculation element 1000.Term " wireless " and derivatives thereof can be used for describing by circuit, equipment, system, method, technology, communication channel that transmits data with modulated electromagnetic radiation via non-solid state medium etc.This term does not mean that the device that is associated does not comprise any wire, but they may not comprise any wire in certain embodiments.Communication chip 1006 can be realized any in multiple wireless standard or the agreement, includes but not limited to Wi-Fi (IEEE802.11 series), WiMAX (IEEE802.16 series), IEEE802.20, Long Term Evolution (LTE), EV-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, bluetooth and derivative thereof and is called 3G, 4G, 5G and higher any other wireless protocols.Calculation element 1000 can comprise a plurality of communication chips 1006.For example, the first communication chip 1006 can be exclusively used in the more radio communication of short distance (such as Wi-Fi and bluetooth), and second communication chip 1006 can be exclusively used in more the radio communication of long-range (such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO and other).
The processor 1004 of calculation element 1000 comprises the integrated circuit that is encapsulated in the processor 1004.In some embodiments of the invention, the integrated circuit lead of this processor comprises that plate carries nonvolatile memory or high-speed cache, and/or otherwise is communicatively coupled to the chip external memory that utilizes one or more transistor arrangements as described herein to realize.Term " processor " for example can represent to process from the electronic data of register and/or memory with any device of this electronic data being converted to other electronic data that can be stored in register and/or the memory or the part of device.
Communication chip 1006 also can comprise the integrated circuit lead that is encapsulated in communication chip 1006 inside.According to some such example embodiment, the integrated circuit lead of this communication chip comprises the one or more devices that utilize one or more transistor arrangements as described herein to realize.As understanding according to the disclosure, attention can directly be integrated into a plurality of standard radio abilities (for example the function of arbitrary chip 1006 is integrated in the processor 1004, rather than has independent communication chip) in the processor 1004.In addition, notice that processor 1004 can be the chipset with such wireless capability.In brief, can use any amount of processor 1004 and/or communication chip 1006.Equally, any one chip or chipset can have the several functions that is integrated in wherein.
In a plurality of implementations, calculation element 1000 can be laptop computer, net book, notebook, smart mobile phone, flat board, personal digital assistant (PDA), super mobile OC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, amusement control unit, digital camera, portable music player or digital video recorder.In other implementation, this device 1000 can be deal with data or adopt transistorized any other electronic installation.
A plurality of embodiment will be apparent according to the disclosure, and the feature of describing in this article can make up in any amount of configuration.An exemplary embodiment of the present invention provides transistor device.This device comprises the substrate with channel region and is positioned at the gate electrode of this channel region top.Gate dielectric layer is arranged between gate electrode and the channel region, and p-type and N-shaped source/drain region are arranged in the substrate and contiguous channel region.This device also is included in the boron doped germanium layer at least a portion in p-type source/drain region.This boron doped germanium layer comprises the germanium concentration that surpasses 90 atomic percents and surpasses 1E20cm -3Boron concentration.This device also is included in metal on the boron doped germanium layer-germanide source/drain contact.In such example, this boron doped germanium layer is only on the p-type source/drain region of this device.In another sample situation, this device further comprises interlayer dielectric.In another sample situation, this device further is included in the resilient coating of the gradual change between the resilient coating of the gradual change between in this substrate and p-type and the N-shaped source/drain region at least one and/or at least one and the boron doped germanium layer in p-type and N-shaped source/drain region.In the situation that one such, the resilient coating of the gradual change between at least one in p-type and N-shaped source and the drain region and the boron doped germanium layer have from p-type and N-shaped source/drain region at least one compatible basic horizontal concentration gradient to the germanium concentration of the high concentration that surpasses 95 atomic percents.In such specific example situation, high concentration has reflected pure germanium.Under another sample situation, the resilient coating of the gradual change between at least one in p-type and the N-shaped source/drain region and the boron doped germanium layer have from p-type and N-shaped source/drain region at least one compatible basic horizontal concentration gradient to surpassing 1E20cm -3The boron concentration of high concentration.Under another sample situation, boron doped germanium layer has at least one the graded concentration in germanium and the boron.Under another sample situation, p-type and N-shaped source/drain region comprise the SiGe with the germanium concentration from the basic horizontal concentration gradient compatible with substrate to the high concentration that surpasses 50 atomic percents, and boron doped germanium layer has the germanium concentration that surpasses 95 atomic percents.Under another sample situation, p-type and N-shaped source/drain region comprise having from the basic horizontal concentration gradient compatible with substrate to surpassing 1E20cm -3The boron doped SiGe of boron concentration of high concentration.Under another sample situation, p-type and N-shaped source/drain region comprise silicon or SiGe, and this device also is included in the resilient coating between at least one and the boron doped germanium layer in p-type and the N-shaped source/drain region, this resilient coating have from p-type and N-shaped source/drain region at least one compatible basic horizontal concentration gradient to the germanium concentration of the high concentration that surpasses 50 atomic percents and from p-type and N-shaped source/drain region at least one compatible basic horizontal concentration gradient to surpassing 1E20cm -3The boron concentration of high concentration.Under another sample situation, this boron doped germanium layer comprises the germanium concentration that surpasses 98 atomic percents and surpasses 2E20cm -3Boron concentration.Another embodiment provides a kind of electronic installation, and it comprises the printed circuit board (PCB) with one or more integrated circuits, and at least one in wherein one or more integrated circuits comprises such as many-sided defined one or more transistor devices in this paragraph.In the situation that a kind of such, the one or more integrated circuit comprises at least one in communication chip and/or the processor, and in communication chip and/or the processor at least one comprises one or more transistor devices.In the situation that another is such, this device is calculation element (for example mobile phone or smart phone, laptop computer, flat computer etc.).
Another embodiment of the present invention provides transistor device.Under this sample situation, this device comprises the substrate with channel region, the gate electrode that is positioned at this channel region top, and wherein gate electrode layer is arranged between gate electrode and the channel region, and interval body is arranged on the side of gate electrode.This device also is included in the substrate and p-type and the N-shaped source/drain region of contiguous channel region, and each in p-type and the N-shaped source/drain region is included in the tip region that extend the corresponding interval body below in gate dielectric layer and/or the interval body.This device also is included in the boron doped germanium layer at least a portion in p-type source/drain region, and this boron doped germanium layer comprises the germanium concentration that surpasses 95 atomic percents and surpasses 2E20cm -3Boron concentration.This device also is included in metal on the boron doped germanium layer-germanide source/drain contact.This device is a kind of in plane or the FinFET transistor.Under such sample situation, this device also is included in the resilient coating between at least one and the boron doped germanium layer in p-type and the N-shaped source/drain region, wherein this resilient coating have from p-type and N-shaped source/drain region at least one compatible basic horizontal concentration gradient to the germanium concentration of the high concentration that surpasses 95 atomic percents and from p-type and N-shaped source/drain region at least one compatible basic horizontal concentration gradient to surpassing 1E20cm -3The boron concentration of high concentration.Under another sample situation, boron doped germanium layer has at least one the graded concentration in germanium and the boron.Under another sample situation, p-type and N-shaped source/drain region comprise the SiGe with the germanium concentration from the basic horizontal concentration gradient compatible with substrate to the high concentration that surpasses 50 atomic percents, and boron doped germanium layer has the germanium concentration that surpasses 98 atomic percents.Under another sample situation, p-type and N-shaped source/drain region have from the basic horizontal concentration gradient compatible with substrate to surpassing 2E20cm -3The boron concentration of high concentration.Under another sample situation, p-type and N-shaped source/drain region comprise having the fixedly SiGe of germanium concentration, and this device also is included in the resilient coating between p-type and N-shaped source/drain region and the boron doped germanium layer, this resilient coating have from the basic horizontal concentration gradient compatible with N-shaped source/drain region with p-type to the high concentration that surpasses 50 atomic percents germanium concentration and from the basic horizontal concentration gradient compatible with N-shaped source/drain region with p-type to surpassing 2E20cm -3The boron concentration of high concentration, this resilient coating has the thickness less than 100 dusts.Another embodiment provides a kind of calculation element (for example desktop computer or portable computer etc.), it comprises the printed circuit board (PCB) with communication chip and/or processor, and wherein at least one in communication chip and/or the processor comprises the one or more transistor devices such as many-sided definition in this paragraph.
Another embodiment of the present invention is provided for forming the method for transistor device.The method comprises provides the substrate with channel region, and is provided at the gate electrode on this channel region, and wherein gate dielectric layer is arranged between gate electrode and the channel region.The method continues to be provided in the substrate and p-type and the N-shaped source/drain region of contiguous channel region, and is provided at the boron doped germanium layer at least a portion in p-type source/drain region.This boron doped germanium layer comprises the germanium concentration that surpasses 90 atomic percents and surpasses 1E20cm -3Boron concentration.The method continues to be provided at metal on the boron doped germanium layer-germanide source/drain contact.Under some such sample situations, the method further comprise the resilient coating of the gradual change between at least one that is provided in this substrate and p-type and the N-shaped source/drain region and/or be provided at p-type and N-shaped source/drain region at least one and boron doped germanium layer between the resilient coating of gradual change.Under another sample situation, boron doped germanium layer has at least one the graded concentration (can with or can not use with graded buffer layer) in germanium and the boron.For example, can when any electronic installation of making such as calculation element, adopt the method.
For the purpose of illustration and description, provided the foregoing description of example embodiment of the present invention.It is not intended to limit or limits the present invention to disclosed accurately form.According to above-mentioned open, many modifications and variations are possible.Scope of the present invention is not by this detail specifications restriction but is defined by the following claims.

Claims (23)

1. transistor device comprises:
Substrate has channel region;
Gate electrode, described gate electrode are positioned at described channel region top, and wherein gate dielectric layer is arranged between described gate electrode and the described channel region;
P-type and N-shaped source/drain region, described p-type and N-shaped source/drain region are in described substrate and contiguous described channel region;
Boron doped germanium layer, described boron doped germanium layer and comprise the germanium concentration that surpasses 90 atomic percents and surpass 1E20cm at least a portion in p-type source/drain region -3Boron concentration; And
Metal-germanide source/drain contact, described metal-germanide source/drain contact is on described boron doped germanium layer.
2. device as claimed in claim 1 is characterized in that, described device is a kind of in plane or the FinFET transistor.
3. device as claimed in claim 1 or 2 is characterized in that, described boron doped germanium layer is only on the p-type source/drain region of described device.
4. such as each the described device in the above claim, it is characterized in that, also comprise interlayer dielectric.
5. such as each the described device in the above claim, it is characterized in that, also comprise at least one in the following:
The resilient coating of the gradual change between at least one in described substrate and described p-type and N-shaped source/drain region; And
The resilient coating of the gradual change between at least one in described p-type and N-shaped source/drain region and the described boron doped germanium layer.
6. device as claimed in claim 5, it is characterized in that, the resilient coating of the gradual change between at least one in p-type and N-shaped source/drain region and the boron doped germanium layer have from p-type and N-shaped source/drain region at least one compatible basic horizontal concentration gradient to the germanium concentration of the high concentration that surpasses 95 atomic percents.
7. device as claimed in claim 6 is characterized in that, described high concentration reflection pure germanium.
8. such as each the described device in the claim 5,6 or 7, it is characterized in that, the resilient coating of the gradual change between at least one in p-type and N-shaped source/drain region and the boron doped germanium layer have from p-type and N-shaped source/drain region at least one compatible basic horizontal concentration gradient to surpassing 1E20cm -3The boron concentration of high concentration.
9. as each the described device in the above claim, it is characterized in that, described boron doped germanium layer has at least one the graded concentration in germanium and the boron.
10. such as each the described device in the above claim, it is characterized in that, p-type and N-shaped source/drain region comprise the SiGe with the germanium concentration from the basic horizontal concentration gradient compatible with substrate to the high concentration that surpasses 50 atomic percents, and boron doped germanium layer has the germanium concentration that surpasses 95 atomic percents.
11. each the described device as in the above claim is characterized in that, described p-type and N-shaped source/drain region comprise having from the basic horizontal concentration gradient compatible with substrate to surpassing 1E20cm -3The boron doped SiGe of boron concentration of high concentration.
12. such as each the described device among the claim 1-4, it is characterized in that, p-type and N-shaped source/drain region comprise silicon or SiGe, and described device also is included in the resilient coating between at least one and the boron doped germanium layer in p-type and the N-shaped source/drain region, described resilient coating have from p-type and N-shaped source/drain region at least one compatible basic horizontal concentration gradient to the germanium concentration of the high concentration that surpasses 50 atomic percents and from p-type and N-shaped source/drain region at least one compatible basic horizontal concentration gradient to surpassing 1E20cm -3The boron concentration of high concentration.
13. each the described device as in the above claim is characterized in that, described boron doped germanium layer comprises the germanium concentration that surpasses 98 atomic percents and surpasses 2E20cm -3Boron concentration.
14. an electronic installation comprises:
Printed circuit board (PCB) has one or more integrated circuits, and at least one in wherein said one or more integrated circuits comprises such as each the one or more transistor devices that limit in the above claim.
15. electronic installation as claimed in claim 14, it is characterized in that, described one or more integrated circuit comprises at least one in communication chip and/or the processor, and in described communication chip and/or the processor at least one comprises described one or more transistor device.
16. such as the described electronic installation of claims 14 or 15, it is characterized in that, described device is calculation element.
17. a transistor device comprises:
Substrate has channel region;
Gate electrode, described gate electrode are positioned at described channel region top, and wherein gate dielectric layer is arranged between described gate electrode and the described channel region, and interval body is arranged on the side of described gate electrode;
P-type and N-shaped source/drain region, described p-type and N-shaped source/drain region are in described substrate and be close to described channel region, and each in described p-type and the N-shaped source/drain region is included in the tip region that extend the corresponding interval body below in gate dielectric layer and/or the interval body;
Boron doped germanium layer, described boron doped germanium layer and comprise the germanium concentration that surpasses 95 atomic percents and surpass 2E20cm at least a portion in p-type source/drain region -3Boron concentration; And
Metal-germanide source/drain contact, described metal-germanide source/drain contact is on described boron doped germanium layer;
Wherein said device is a kind of in plane or the FinFET transistor.
18. device as claimed in claim 17 is characterized in that, described device also comprises:
Resilient coating between in p-type and N-shaped source/drain region at least one and the boron doped germanium layer, wherein said resilient coating have from p-type and N-shaped source/drain region at least one compatible basic horizontal concentration gradient to the germanium concentration of the high concentration that surpasses 95 atomic percents and from p-type and N-shaped source/drain region at least one compatible basic horizontal concentration gradient to surpassing 2E20cm -3The boron concentration of high concentration.
19. device as claimed in claim 17 is characterized in that, described boron doped germanium layer has at least one the graded concentration in germanium and the boron.
20. device as claimed in claim 17, it is characterized in that, described p-type and N-shaped source/drain region comprise the SiGe with the germanium concentration from the basic horizontal concentration gradient compatible with substrate to the high concentration that surpasses 50 atomic percents, and boron doped germanium layer has the germanium concentration that surpasses 98 atomic percents.
21. device as claimed in claim 20 is characterized in that, described p-type and N-shaped source/drain region have from the basic horizontal concentration gradient compatible with substrate to surpassing 2E20cm -3The boron concentration of high concentration.
22. device as claimed in claim 17, it is characterized in that, described p-type and N-shaped source/drain region comprise having the fixedly SiGe of germanium concentration, and described device also is included in the resilient coating between p-type and N-shaped source/drain region and the boron doped germanium layer, described resilient coating have from the basic horizontal concentration gradient compatible with N-shaped source/drain region with p-type to the high concentration that surpasses 50 atomic percents germanium concentration and from the basic horizontal concentration gradient compatible with N-shaped source/drain region with p-type to surpassing 2E20cm -3The boron concentration of high concentration, described resilient coating has the thickness less than 100 dusts.
23. a method that forms transistor device comprises:
Substrate is provided, and described substrate has channel region;
Gate electrode is provided, and described gate electrode is positioned at described channel region top, and wherein gate dielectric layer is arranged between described gate electrode and the described channel region; And
P-type and N-shaped source/drain region are provided, and described p-type and N-shaped source/drain region are in described substrate and contiguous described channel region;
Boron doped germanium layer is provided, and described boron doped germanium layer is at least a portion in p-type source/drain region, and described boron doped germanium layer comprises the germanium concentration that surpasses 90 atomic percents and surpasses 1E20cm -3Boron concentration; And
Metal-germanide source/drain contact is provided, and described metal-germanide source/drain contact is on described boron doped germanium layer.
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