TWI696290B - Semiconductor device, electronic device and electronic device terminal structure - Google Patents

Abstract

Provided are a semiconductor device, an electronic device, and an electronic device terminal structure, wherein the semiconductor device can include a channel region with a first semiconductor material for a majority carrier in the channel region during operation (on state) of the device and a metal contact. A source/drain region can include a semiconductor material alloy including a second semiconductor material and at least one heterojunction located between the metal contact and the channel region, wherein the heterojunction forms a band-edge offset for the majority carrier that is less than or equal to about 0.2 eV.

Description

Semiconductor component, electronic component and electronic component terminal structure [Cross-reference to related applications]

This application is related to and advocates the application on November 26, 2014 at the United States Patent and Trademark Office (USPTO) with the title "Structure and method to achieve low contact." resistance using heterojunctions)" priority of US Provisional Patent Application No. 62/085,092, and was filed at the USPTO on March 26, 2014, with the heading "Containing High Mobility Channel Materials and Indented Source/ Fin-type field effect transistor element with step-wise composition in the drain region and method of forming the element (FINFET DEVICES INCLUDING HIGH MOBILITY CHANNEL MATERIALS WITH MATERIALS OF GRADED COMPOSITION IN RECESSED SOURCE/DRAIN REGIONS AND METHODS OF FORMING THE SAME) ”Partial continuation of US Patent Application No. 14/226,518, which claims to have an indentation and a step change titled “Low Total Parasitic Resistance” filed at the USPTO on July 30, 2013 FINFET WITH RECESSED AND GRADED SOURCE AND DRAIN MATERIAL FOR LOW TOTAL PARASITIC RESISTANCE of the source and drain materials The priority of Provisional Patent Application No. 61/859,932, the full disclosure content of the above patent application is incorporated in this case for reference.

The present invention relates generally to the field of integrated circuit elements, and more specifically relates to the use of integrated circuit elements configured to operate as semiconductor materials.

As the size of metal oxide semiconductor (MOS) devices continues to shrink, parasitic resistance may become an increasingly prominent problem, which can make the total resistance at each new node compared to the previous node The percentage is higher and can be a factor that affects the performance of these devices. Furthermore, the specific materials selected for channels such as MOS elements may not always be sufficient or compatible for low-resistivity contacts.

For example, the parasitic resistance is further discussed in US Patent Publication Nos. 2006/0202266 and 2009/0166742, the entire disclosure content of which is incorporated by reference in this case.

According to the embodiments of the present invention, in order to lower the contact resistance, an element contact structure including a heterojunction can be provided. According to these embodiments, a semiconductor device may include: a channel region having a first semiconductor material for transferring a majority carrier in the channel region during operation of the semiconductor device; and a metal contact point. The source/drain regions may include an alloy of semiconductor materials Gold includes a second semiconductor material, and at least one heterojunction is located in the source/drain region between the metal contact and the channel region, wherein the heterojunction is for the majority carrier This results in a band edge shift of less than or equal to about 0.2 eV.

In some embodiments according to the present invention, the semiconductor material alloy may include a stepped composition of the second semiconductor material and a third semiconductor material, wherein the third semiconductor material is not completely incompatible with the first semiconductor material Miscibility, that is, it is impossible to obtain the third semiconductor material by continuously changing the semiconductor material alloy from the first semiconductor material.

In some embodiments according to the present invention, the band edge offset of the heterojunction may be about 0.0 electron volts.

In some embodiments according to the present invention, the energy band edge offset of the heterojunction may be less than 0.2 electron volts, and the heterojunction may be doped with conduction with the majority carrier The type of dopant corresponding to the sex.

In some embodiments according to the invention, the stepped composition of the semiconductor material alloy includes the second semiconductor at a concentration that can be enriched at the interface with the first semiconductor material of the channel region Materials and a depleted concentration of the third semiconductor material, and progress to a depleted concentration of the second semiconductor material and an enriched concentration of the third semiconductor material at the interface with the metal contact.

In some embodiments according to the present invention, the stepped composition of the semiconductor material alloy may be provided by S2 _x S3 _1-x , where S3 is the third semiconductor material and S2 is the second semiconductor material . In some embodiments, x=0 at the interface with the metal contact and x=1 at the interface with the first semiconductor material.

In some embodiments according to the present invention, the increase in the stepped composition of the semiconductor material alloy may be configured to prevent an energy band shift between adjacent steps in the stepped composition greater than about 0.2 electrons volt.

In some embodiments according to the present invention, an electronic component may include: a channel region having a first semiconductor material, the first semiconductor material is used to transmit a majority load in the channel region during operation of the electronic component Sub; and metal contacts. The source/drain region may include a material alloy that includes at least one material component and may be free of any component of the first semiconductor material, so that the material alloy is in the channel region and The compositional step change between the interfaces of the metal contacts avoids sudden changes in band edge shifts between the increase of the compositional step change and at any of the heterojunctions therein.

In some embodiments according to the present invention, the first semiconductor material has a first lattice structure, and the material alloy may have a second lattice structure different from the first lattice structure to form a For most carriers, the heterojunction has a band edge shift of less than or equal to about 0.2 eV.

In some embodiments, the semiconductor device may include: a channel region having a first semiconductor material for transferring a majority carrier in the channel region during operation of the semiconductor device; and a metal contact point. The source/drain region may include a first portion adjacent to the channel region containing a semiconductor material alloy, the semiconductor material alloy including a second semiconductor material and the second semiconductor material With the third semiconductor material step change composition. The source/drain region may include another portion adjacent to the metal contact containing the fourth semiconductor material, wherein for the majority carrier, one of the two portions of the source/drain The interface between them is a heterojunction with a band edge shift of less than or equal to about 0.2 electron volts, and is doped with a dopant type corresponding to the majority carrier. In some of these embodiments, the material may be selected such that no heterojunction is formed between the portion of the channel adjacent to the source/drain and the channel material. For example, in certain embodiments, the semiconductor material alloy is selected so that the semiconductor material alloy can be stepped into a substantially first semiconductor material at the interface with the channel. In other embodiments, the interface between the semiconductor alloy and the first semiconductor material may exhibit an energy band edge shift of less than or equal to about 0.2 eV for the majority carrier and be doped with the The second heterojunction of the dopant type corresponding to the majority carrier.

In some embodiments according to the present invention, an electronic component terminal structure may include: a metal contact; and a stepped composition layer including the steps within the stepped composition layer represented by S2 _x S3 _1-x A second material (S2) and a third material (S3) that are combined with each other in a variable composition, wherein the stepped composition of the stepped composition layer is approximately S2 near the metal contact, that is, x=0, And it is almost completely S1 away from the metal contact, that is, x=1, and the stepwise composition of the stepwise composition layer between x=0 and x=1 is sufficient to avoid the terminal structure of the electronic component For the selected carrier of, the band edge shift in the stepped composition layer is greater than 0.2 eV. The third material S3 may contact the stepped composition layer at a position away from the metal contact at x=1, S3 is selected to form a heterojunction with S1 equal to or less than about 0.2 electron volts, and wherein S2 may be It is selected to provide a Schottky barrier height equal to or less than about 0.2 eV to the metal contacts.

In some embodiments according to the present invention, an electronic component terminal structure may include: a metal contact; and a stepped composition layer including the steps within the stepped composition layer represented by S2 _x S3 _1-x A second material (S2) and a third material (S3) that are combined with each other in a variable composition, wherein the stepped composition of the stepped composition layer is approximately completely S2 near the metal contact, that is, x= 0, and the step-wise composition of the step-wise composition layer at the distance from the metal contact is approximately completely S1, that is, x=1, and the step-wise composition between x=0 and x=1 The stepped composition of the layer is sufficient to avoid shifting the band edge within the stepped composition layer by more than 0.2 electron volts for the selected carrier of the electronic component terminal structure. The third material S3 may be positioned to separate the metal contact from the stepped composition layer, and may be adjacent to the stepped composition layer at the position of x=0, and S3 is selected to form with S2 A heterojunction equal to or less than about 0.2 electron volts and provides the metal contact with a Schottky barrier height equal to or less than about 0.2 electron volts.

100: channel area

101: metal contacts

102: Interface

105: Metal contact interface part

106: Semiconductor material alloy

107: source/drain region

CBE: conduction band edge

S1: First material/first semiconductor material

S2: second material/second semiconductor material

S2 _x S3 _1-x : semiconductor material alloy

S3: third material/third semiconductor material

S4: Fourth semiconductor material

S5: Fifth semiconductor material

VBE: price band edge

1 is a cross-sectional view of a channel region with an adjacent source/drain region in some embodiments according to the present invention, the source/drain region including a semiconductor material alloy, the semiconductor material alloy having The channel region and the metal contact located at the upper surface of the source/drain region are smoothly stepped.

2 and 3 are alternative channel areas in some embodiments according to the present invention to And a cross-sectional view of the associated source/drain region geometry, each of which includes a metal contact at the channel region and at the upper surface of the source/drain region A semiconductor material alloy in which steps change smoothly between points.

4 is a schematic diagram of a linear composition step curve of a semiconductor material alloy between a material of a channel region and a metal contact in some embodiments according to the present invention.

5 is a schematic diagram of a nonlinear composition step curve of a semiconductor material alloy between a material of a channel region and a metal contact in some embodiments according to the present invention.

FIG. 6 is a schematic diagram of a stepwise composition step curve of a semiconductor material alloy between a material of a channel region and a metal contact in some embodiments according to the present invention.

7 is a schematic diagram of a compositional step curve of a semiconductor material alloy between a material of a channel region and an interface material adjacent to a metal contact in some embodiments according to the present invention.

FIG. 8 is a schematic diagram of a composition step curve of the first and second semiconductor material alloys between the channel region material and the metal contact in some embodiments according to the present invention.

Exemplary embodiments are explained below with reference to the drawings. Many different forms and embodiments can be made without departing from the spirit and teaching content of this disclosure, so the present invention should not be considered limited to the exemplary embodiments described herein. Rather, the exemplary embodiments are provided to make the disclosure content thorough and complete, and to convey the scope of the present invention to those skilled in the art. In the drawings, the size and relative size of each layer and area can be exaggerated for clarity. The same reference numbers refer to the same elements throughout.

Herein, exemplary embodiments of the inventive concept are explained with reference to cross-sectional views, which are schematic diagrams of idealized embodiments and intermediate structures of exemplary embodiments. Therefore, it can be expected to deviate from the illustrated shape due to, for example, manufacturing technology and/or tolerance. Therefore, the exemplary embodiments of the inventive concept should not be considered limited to the specific shapes described herein, but include shape deviations caused by, for example, manufacturing.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary knowledge in the technical field to which the present invention belongs. It should be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the relevant technical background, and unless clearly defined herein, they should not be interpreted as having ideals The meaning is too formal or too formal.

The terminology used herein is only for explaining specific embodiments, and is not intended to limit the embodiments. Unless the context clearly indicates otherwise, the singular forms "a" and "said" used herein are intended to include the plural forms as well. It should be further understood that when the terms "including" and/or "including" are used in this specification, they are used to indicate the existence of the described features, integers, steps, operations, elements, and/or components, but do not exclude one or The presence or addition of multiple other features, integers, steps, operations, elements, components, and/or groups thereof.

It should be understood that when an element is referred to as being "coupled" to, "connected to", "responsive" to another element, or "on" another element, it can be directly coupled to, connected to, and corresponding to. The other element may be directly on the other element, or an intermediate element may also be present. On the contrary, when a component is "directly coupled" to, "directly When connecting to, directly responding to, or being "directly on" another component, there is no intermediate component. The term "and/or" as used herein includes any and all combinations of one or more of the listed items.

It should be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited to these terms. These terms are only used to distinguish each element. Therefore, the first element may be referred to as the second element without departing from the teaching content of the embodiments of the present invention.

In this article, for ease of explanation, the terms of spatial relative relationship can be used, such as "below", "below", "below", "above", "above", etc. The relationship between one element or feature described and another (other) element or feature. It should be understood that the terms of the spatial relative relationship are intended to include different orientations of the elements in use or operation in addition to the orientations depicted in the figures. For example, if the element in the figure is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The elements may have other orientations (rotation by 90 degrees or other orientations), and therefore the term spatial relative relationship used herein may be interpreted accordingly.

It should be understood that although many of the embodiments described herein relate to semiconductor materials in transistors, the invention can be utilized with other types of materials that can be configured in electronic components as semiconductor materials ( For example, semi-metal materials, degenerate semiconductor materials, and combinations thereof operate.

In addition, it should be understood that although many embodiments described herein illustrate a fin field-effect transistor (finFET) structure as the channel region, other types of transistor structures (eg, planar transistors, Nanowire transistors, metal-oxide-semiconductor field-effect transistors (MOSFETs, etc.) utilize the present invention.

It should be understood that the term "band edge" used herein in connection with a specific material depends on the conductivity type of charge carriers used during operation (on state) of the device (ie, pMOS device to nMOS device) , And refers to the edge of the conduction band or valence band of the mentioned material. Therefore, when the type of the component is not specified, the term "band edge" may be used by referring to "relevant carrier". For pMOS devices, the relevant carriers are holes, and the band edge refers to the valence band edge. For nMOS devices, the relevant carriers are electrons, and the band edge refers to the conduction band edge.

It should be understood that the term "low contact resistivity" or similar terms used herein refers to an interface of about 1×10 ^-8 ohm-cm ² or less than 1×10 ^-8 ohm-cm ² Contact resistivity value. In certain embodiments, it may refer to about 1 × 10 ^-7 ohm - cm or less than 1 × 10 ^-7 ohm - cm contact resistance value. It should be understood that the terms "low Schottky barrier height (SBH)" or "low barrier" used herein for metals in contact with semiconductor materials include values of about 0.2 eV or less. It should be understood that the term "small" (or similar terms) used in this text is used to refer to the shift of the energy band between the edges of the energy carriers at the heterojunction between two different materials, Include values of about 0.2 eV or less. It should be understood that the term "small" (or similar terms) as used herein, when used to refer to an energy band shift formed by an increase or step in the compositional step of the material, includes about 0.2 eV or less 0.2 eV, preferably about 0.1 eV or less.

It should be understood that the formal expressions used in this document (for example, S2 _x S3 _1-x ) refer to two materials (S2 and S3) formed into alloys with a relative composition so that S2 per x unit corresponds to every 1-x unit. S3, where the index x can vary between 0 and 1. The alloy S2 _x S3 _1-x may be included in the region (eg, source/drain region), and the composition of the alloy (represented by the parameter x) may vary with the position in the region. The terms "poor" or "enriched" can be used to refer to the proportion of specific materials. For example, S2 _x S3 _1-x alloy enriched S2 is close to x S2 _x S3 _1-x alloy 1. For example, S2 poor S2 _x S3 _1-x alloy close to x S2 _x S3 _1-x alloy 0.

The term "semiconductor material" as used herein may refer to a semiconductor material containing only a single element, or to a semiconductor material compound containing more than one element. The term "semiconductor material alloy" as used herein refers to a semiconductor material containing at least two different elements.

As understood by the inventor of the present invention, in some embodiments according to the present invention, for the device, a semiconductor material alloy (hereinafter referred to as abbreviated as a A low-resistivity contact is provided to the first semiconductor material S1 (hereinafter simply referred to as semiconductor material S1) in the channel region for a semiconductor alloy or alloy (S2 and S3). For example, the compositional step change in the semiconductor alloy may be such that the contributions of S2 and S3 in the alloy gradually change with the position in the source/drain regions. For example, the alloy composition step can be changed by It is arranged such that the semiconductor alloy is substantially S2 near the channel region, and the semiconductor alloy is substantially S3 at the metal contact away from the channel region.

In addition, the semiconductor materials contained in the alloys (S2 and S3) can each be selected to have a specific relationship with respect to the semiconductor material (S1) in the channel. For example, compared to the band edge of the third semiconductor material S3 (hereinafter referred to as semiconductor material S3), the second semiconductor material S2 (hereinafter referred to as semiconductor material S2) can be selected to have a relatively close to the semiconductor material S1 Band edge band edge (ie, low band edge offset). However, the semiconductor material S3 may be selected to have a relatively large band edge offset relative to the semiconductor material S1. In addition, for the relevant carriers, the compositional steps of the semiconductor alloys (S2 and S3) in the source/drain regions should be smooth to avoid any of the band edge in the source/drain regions Suddenly changed.

Therefore, as understood by the inventor of the present invention, the semiconductor material S1 and the semiconductor material S3 in the channel region are selected so that one of them (for example, S3) cannot be changed from the other by using a continuous composition step ( For example, S1) obtained. In other words, the semiconductor material S2 can be used as an intermediate material that is closer to the energy band edge of S1 but can also be present in the alloy together with S3.

Therefore, the semiconductor material S1 can be selected to be significantly different from the semiconductor material S2 but still have a relatively low band edge shift, and in addition, the compositional step change of the semiconductor alloy can be used to move the metal away from the channel region as the step changes The contact progresses and gradually increases the contribution of S3 and decreases the contribution of S2. It should further be understood that the semiconductor material S3 present at the metal contacts can be selected to provide a relatively low Schottky barrier height to the relevant carriers.

As understood by the inventor of the present invention, references (Jenny Hu, H.-S. Philip Wong) and Krishna Saraswater ( Krishna Saraswat (2011) published in Materials Research Society Bulletin (MRS Bulletin) No. 36, pages 112-120, ``Novel contact structures for high mobility channel (Novel contact structures for high mobility channel) materials)" (available online at doi: 10.1557/mrs.2011.5 and incorporated into this article for reference)) and Figure 3 and references (Hideki Hasgawa and Masamichi Akazawa) in the Korean Journal of Physical Society (Journal of the Korean Physical Society) "Transient Behavior of Current Transmission, Fermi Level Pinning, and Group III Nitride Schottky Barriers" published on September 3, 2009, Volume 55, pages 1167-1179 (Journal of the Korean Physical Society) Current transport, Fermi Level Pinning, and Transient Behavior of Group-III Nitride Schottky Barriers)'' (incorporated herein by reference)) illustrates each of the different semiconductor materials/compounds/alloys that can be used in the element according to the invention Don't take band alignment. According to the above materials, some semiconductor materials exhibit Fermi level pinning when in contact with metal (and in some cases exhibit strong Fermi level pinning); in this case, they form at the metal-semiconductor interface The Schottky barrier is moderately dependent or not dependent on the work function of the metal. The Fermi level pinning position is usually close to the charge neutral level.

Still referring to Figure 3 of Hu and Figure 4 of Hasegawa, the charge-neutral levels of several semiconductor materials are shown. In some embodiments, the semiconductor material selected to form the metal contact has a Fermi level pinning or near the edge of the relevant carrier band Strong Fermi level pinning to provide a low Schottky barrier height to the relevant carrier when in contact with metal.

It should be further understood that the pinning of the indium gallium antimony (InGaSb) alloy can be close to the edge of the valence band. It should be further understood that for indium gallium arsenide (InGaAs), indium gallium nitrogen (InGaN), and aluminum gallium nitrogen (AlGaN) alloys, the absolute position of the charge neutral level may vary slightly with the composition. In some embodiments, indium arsenide (InAs), indium (In) enriched indium-gallium-arsenic (In-Ga-As) alloy, indium nitride (InN), and indium (In) enriched Indium-gallium-nitrogen (In-Ga-N) alloys can be applied to semiconductor materials used for alloy interfaces to metal contacts in nMOS devices. Due to its small gap, indium antimonide (InSb) can be applied to nMOS devices and pMOS devices. For pMOS devices, germanium (Ge), indium antimonide (InSb), gallium antimonide (GaSb), and indium-gallium-antimony (In-Ga-Sb) alloys can be applied to the alloy interface to the metal contacts semiconductors.

As understood by the inventor of the present invention, Sandipu. Sandip Tiwari and David. J. David J. Frank published in Appl. Phys. Lett. 60,630 (1992) "Empirical fitting of band discontinuities and barrier heights in III-V alloy systems (Empirical fit to band discontinuities and barrier heights in III-V alloy systems)'' (available online at dx.doi.org/10.1063/1.06575 and incorporated herein for reference) is shown in FIG. 1 to illustrate certain embodiments according to the present invention. In the graph of lattice constants and band edge positions of different semiconductor materials. Therefore, Tivari's Figure 1 can be used to select the appropriate material combination for the channel and source drain regions of the device. As more understood by the inventor of the present invention, by Jesus A. Dell. Alamo (Jesús A. del Alamo) "Nanometre-scale electronics with III-V compound semiconductors" (Nanometre-scale electronics with III-V compound semiconductors) published by Nature 479,317-323 (November 17, 2011) (available at doi: 10.1038 /nature10677 is available online and incorporated herein for reference). Figure 1 is a graph illustrating the mobility of several semiconductor materials and can be used to select the appropriate channel material.

The compositional step change of the semiconductor material alloy in the source/drain region may be set based on the semiconductor material selected for the interface with the metal contact and the semiconductor material to be used in the channel region. For example, in some embodiments according to the present invention, high germanium silicon germanium alloy (high Ge SiGe alloy) or germanium (Ge) for nMOS or pMOS, silicon (Si) for nMOS or pMOS, Silicon-germanium (SiGe) for pMOS, In-Ga-As alloy for nMOS, In-As alloy for nMOS, or Indium for nMOS or pMOS -Gallium-antimony (In-Ga-Sb) alloys and the like can be used as semiconductor materials in the channel region. It should be understood that each of the above parameters (ie, the semiconductor material used as the interface to the metal contact, and the semiconductor material used in the channel region) can be selected to satisfy the following two conditions: (1) in the channel The semiconductor material used in the region cannot be smoothly changed in composition to achieve the semiconductor material used at the interface to the metal contact; and (2) The semiconductor material used in the channel region is selected to be located at the metal contact The band edge shift between semiconductor materials at the interface of (for related carriers) is significant (ie, greater than about 0.2 eV).

In view of the above, between the channel region and the metal contact, a smooth composition step change of the semiconductor alloy in the source/drain region can be used to provide a low resistivity contact. in In either case, the semiconductor material contained in the alloy is selected to effectively reduce the barrier to carrier transport in the source/drain region, regardless of, for example, the heterojunction formed near the metal contact or near the channel region Existence or not. In either case, the band edge offset provided at the heterojunction should be less than 0.2 eV for the relevant carriers.

It should be understood that using epitaxial growth of the selected material in the source/drain regions (epitaxial-growth), the desired composition expression (eg S2 _x S3 _1-x ) can be used during the epitaxial growth process to perform smooth steps The formation of variable semiconductor material alloys. In addition, the method described in the following application can be used to form a smooth step-change semiconductor material alloy: the application filed at the USPTO on March 26, 2014, entitled "Containing High Mobility Channel Materials and Indented Source/ Fin-type field effect transistor element with step-wise composition in the drain region and method of forming the element (FINFET DEVICES INCLUDING HIGH MOBILITY CHANNEL MATERIALS WITH MATERIALS OF GRADED COMPOSITION IN RECESSED SOURCE/DRAIN REGIONS AND METHODS OF FORMING THE SAME) ”U.S. Patent Application No. 14/226,518, and the fin field effect of the recessed and stepped source and drain materials with low total parasitic resistance and filed at the USPTO on July 30, 2013 Transistor (FINFET WITH RECESSED AND GRADED SOURCE AND DRAIN MATERIAL FOR LOW TOTAL PARASITIC RESISTANCE)" US Provisional Patent Application No. 61/859,932.

FIG. 1 is a semiconductor element having a channel area 100 (hereinafter referred to as area 100) In a cross-sectional view of the device, the channel region 100 includes a channel and contains a first semiconductor material adjacent to the semiconductor material alloy 106 in the source/drain region 107 (S1). In some embodiments according to the invention, the semiconductor material alloy 106 also includes a metal contact interface portion 105 to the metal contact 101. Although FIG. 1 and the associated description refer to the use of semiconductor materials, other types of materials can be used in accordance with the present invention. For example, any material configured to operate as a semiconductor can be used, such as a semi-metal or degenerated semiconductor. Further, FIGS. 2 and 3 illustrate alternative geometries of the region 100 and the source/drain region 107 in some embodiments according to the present invention. Therefore, the geometry of the element shown in FIG. 1 is exemplary, and the present invention is not limited to this.

Still referring to FIG. 1, the semiconductor material alloy 106 is stepwise in composition in the source/drain region 107, for example, from the interface 102 with the channel-containing region 100 to the metal contact interface portion 105. In other words, the composition of the semiconductor material alloy 106 changes with the position in the source/drain region 107. In some embodiments, the composition of the semiconductor material alloy 106 varies with the position in the source/drain region 107 to provide a heterojunction with the semiconductor material S1 and the metal contact interface portion 105 with the metal contacts Between points 101 provides a relatively low Schottky barrier height. Specifically, the semiconductor material alloy 106 may be grown epitaxially so that the semiconductor material S2 is substantially provided at the interface 102 and gradually decreases as it moves toward the metal contact interface portion 105, while the semiconductor material S3 decreases with the semiconductor material S2 And gradually increase, so that when the step change of the semiconductor material alloy 106 reaches the metal contact interface portion 105, the semiconductor material alloy 106 is basically the semiconductor material S3.

It should be understood that in some embodiments, the semiconductor material S1 in the region 100 is The interface 102 forms a heterojunction with the second semiconductor material S2. Therefore, the semiconductor material S1 may be substantially different from the semiconductor material S2, and the band edge shift from S2 to S1 may be relatively small (eg, less than or equal to about 0.2 electron volts). It should also be understood that in embodiments where there is a small band shift, at the heterojunction (between the semiconductor material S1 in the channel-containing region 100 and the semiconductor material S2 in the semiconductor material alloy 106) Doping can be used so that during operation of the device, no significant barrier to carrier flow occurs at the heterojunction interface.

It should be understood that the energy band alignment diagrams shown in FIGS. 4 to 8 represent the material properties of the semiconductor materials (such as S1, S2, S3, etc.) described herein, rather than the specific energy band diagram of the device in a specific operating mode . In FIGS. 4 and 6, for example, CBE refers to the conduction band edge, and the figures correspond to possible embodiments illustrated for nMOS devices. It should be understood that similar mechanisms can be applied to pMOS devices (in this case, the illustrated band edge will correspond to the valence band edge). In Figures 5, 7 and 8, VBE refers to cost band edges, and the figures correspond to possible embodiments illustrated for pMOS elements. It should be understood that a similar mechanism can be applied to nMOS devices (in this case, the illustrated band edge will correspond to the conduction band edge). There can be many other figures within the scope of the invention.

FIG. 4 is a schematic diagram of the linear composition step curve of the semiconductor material alloy 106 in the source/drain region 107. It should be understood that the schematic diagram shown in FIG. 4 can be applied to the embodiment in which the element shown in FIG. 1 is an nMOS element. Referring to FIGS. 1 and 4, the position of x=1 refers to the interface 102 between the channel region 100 and the source/drain region 107, where the semiconductor material alloy 106 includes the semiconductor material S2 but does not include the semiconductor material S3. In some embodiments, at the interface 102, the semiconductor material alloy 106 contains the semiconductor material S2 and a small amount of S3 (ie, S2 is rich and S3 is poor).

As shown in FIG. 4, the composition of the semiconductor material S2 and the semiconductor material S3 in the semiconductor material alloy 106 may change linearly with the position in the source/drain region 107. It should be understood that all semiconductor materials S1 to S3 and all intermediate materials expressed by the relationship shown above are stable or metastable within the thermal budget used in the processing and application of the device . Further, the semiconductor material alloy 106 may be simultaneously doped during the epitaxial growth of the semiconductor material alloy 106.

Further, the semiconductor material S3 present at the metal contact interface portion 105 to the metal contact 101 is selected to provide a relatively small Schottky barrier height (eg, equal to Or less than about 0.2 eV). It should be understood that the compositional step change of the semiconductor material within the semiconductor material alloy 106 provides a relatively small change in composition throughout the source/drain region 107. In addition, in some embodiments according to the present invention, sufficient doping is applied to the entire structure so that screening can effectively reduce any barriers to the transmission of related carriers, otherwise the The barrier can be raised due to the change of the band edge position caused by the compositional step change.

It should be understood that the above mentioned use of smooth composition steps to shield the barrier to carrier transmission can be achieved by maintaining the changes in the band edge to a certain level within a certain distance in the source/drain regions While being offered. In some embodiments according to the present invention, for a doping of about 1×10 ¹⁸ cm ^-3 , the smooth composition step is such that for the relevant carrier, the position of the band edge is about 6 nm Or greater than 6 nanometers with a variation of about 0.1 eV. In some embodiments, for a doping of about 1×10 ¹⁹ cm ^-3 , the smooth composition step is such that for the relevant carriers, the position of the band edge is about 2 nm or greater than 2 nm The change within meters is about 0.1 eV. In some embodiments, for a doping of about 1×10 ²⁰ cm ^-3 , the smooth composition step is such that for the relevant carrier, the position of the band edge is about 0.6 nm or greater than 0.6 nm The change within meters is about 0.1 eV.

It should further be understood that when doping is provided so that the barrier to carrier transmission is effectively shielded via compositional steps, certain ones can be used in source/drain regions with specific band edge changes within a specific distance Doping level.

Referring to FIG. 1, in some embodiments according to the present invention, it should be understood that the doping of the metal contact interface portion 105 can be used to provide the low metal contact interface resistance required herein. For example, for metal contacts with a very low Schottky barrier height and for materials with a small tunneling effective mass in the metal contact interface portion 105, 1×10 ¹⁹ cm ⁻ A doping concentration of several times of ³ may be sufficient. In some embodiments, a doping concentration of 1×10 ²⁰ cm ⁻³ or higher than 1×10 ²⁰ cm ⁻³ may be used in the metal contact interface portion 105. In most cases, even for small Schottky barrier heights, a higher doping concentration in the metal contact interface portion 105 may result in lower contact resistivity, for example, in contact with indium arsenide (InAs ) In the case of contact.

Therefore, in some embodiments, the highest achievable doping concentration may be used in the metal contact interface portion 105.

Similarly, in the case of heterojunctions with small band edge shifts, high doping can be used, where higher doping can provide lower heterojunction interface resistance. In some embodiments, doping levels greater than 1×10 ¹⁹ cm ^-3 may be used. In certain embodiments, may be used from about 1 × 10 ²⁰ cm ^-3 or higher than the doping level of 1 × 10 ²⁰ cm ^-3 in.

In some embodiments where the nMOS device is arranged as shown in FIG. 4 for example: S1 may be silicon (Si), silicon germanium (SiGe) alloy or germanium (Ge); S2 may be gallium arsenide (GaAs) or indium -Gallium-nitrogen (In-Ga-N) or indium-gallium-arsenic-nitrogen (In-Ga-As-N) alloy or indium-aluminum-gallium-arsenic (In-Al-Ga-As) alloy or aluminum- Gallium-arsenic (Al-Ga-As) alloy, in which indium-gallium-nitrogen (In-Ga-N) alloy or indium-gallium-arsenic-nitrogen (In-Ga-As-N) alloy or indium-aluminum-gallium -The composition of the arsenic (In-Al-Ga-As) alloy or the aluminum-gallium-arsenic (Al-Ga-As) alloy is selected so that the conduction band edge is located at about 0.2 electron volts or less than 0.2 of the conduction band edge of S1 Within electronic volts; and S3 can be indium arsenide (InAs), indium nitride (InN) or indium-arsenic-nitrogen (In-As-N) alloy or indium-aluminum-arsenic (In-Al-As) alloy or Indium-gallium-arsenic (In-Ga-As) alloy (in the case of indium-aluminum-arsenic (In-Al-As) alloy or indium-gallium-arsenic (In-Ga-As) alloy, it is preferable to have Indium (In) enriched composition). In some embodiments, if S2 is gallium arsenide (GaAs), then S3 is substantially indium arsenide (InAs). In some embodiments, S3 is doped to be greater than 1×10 ¹⁹ cm ^-3 . In some embodiments, S3 is doped up to about 1×10 ²⁰ cm ^-3 or higher than 1×10 ²⁰ cm ^-3 . In some embodiments, the metal contact 101 is formed of a refractory metal or a transition metal, so the metal contact 101 is a reacted transition metal-S3 alloy. The compositional step change of the alloy may be linear as shown in FIG. 4, or non-linear as shown in FIG. 5, or stepped as shown in FIG.

Selected to contact semiconductor material at metal contact interface portion 105 The metal of alloy 106 (ie, semiconductor material S3) is selected to provide a low Schottky barrier height for most carriers (eg, equal to or less than about 0.2 electron volts). In some embodiments according to the present invention, the metal contact 101 may be a reacted metal contact. In some embodiments according to the present invention, the metal contact interface portion 105 including the semiconductor material S3 is implemented to provide low interface contact resistivity.

It should be understood that FIGS. 5 and 6 show alternative curves of the compositional step change of the semiconductor material alloy 106. Specifically, FIG. 5 shows a nonlinear composition step curve of the semiconductor material alloy 106, and FIG. 6 shows a step composition curve of the semiconductor material alloy 106. It should be understood that the schematic diagrams shown in FIGS. 4 and 6 mean nMOS devices. It should also be understood that the schematic diagrams shown in FIGS. 5, 7 and 8 refer to pMOS devices. However, it should be further understood that the same principles explained above with reference to nMOS can be applied to pMOS devices and vice versa.

In some embodiments in which the device is configured as an nM0s device as shown in FIG. 1 for example: S1 may be silicon (Si), silicon germanium (SiGe) alloy or germanium (Ge); S2 may be gallium arsenide (GaAs) or indium -Gallium-nitrogen (In-Ga-N) or indium-gallium-arsenic-nitrogen (In-Ga-As-N) alloy or indium-aluminum-gallium-arsenic (In-Al-Ga-As) alloy or aluminum- Gallium-arsenic (Al-Ga-As) alloy, in which indium-gallium-nitrogen (In-Ga-N) alloy or indium-gallium-arsenic-nitrogen (In-Ga-As-N) alloy or indium-aluminum-gallium -The composition of arsenic (In-Al-Ga-As) alloy or aluminum-gallium-arsenic (Al-Ga-As) alloy is selected so that the CBE at the edge of the conduction band of S1 is about 0.2 electron volts or less than 0.2 electrons Volts; and S3 can be indium arsenide (InAs), indium nitride (InN) or indium-arsenic-nitrogen (In-As-N) alloy or indium-aluminum-arsenic (In-Al-As) alloy or indium -Gallium-arsenic (In-Ga-As) alloy (in the case of indium-aluminum-arsenic (In-Al-As) alloy or indium-gallium-arsenic (In-Ga-As) alloy, preferably having indium (In) Enriched composition). In some embodiments, if S2 is gallium arsenide (GaAs), then S3 is substantially indium arsenide (InAs). In some embodiments, S3 is doped to be greater than 1×10 ¹⁹ cm ^-3 . In some embodiments, S3 is doped up to about 1×10 ²⁰ cm ^-3 or higher than 1×10 ²⁰ cm ^-3 . In some embodiments, the metal contact 101 is formed of a refractory metal or a transition metal, such that the metal contact 101 is a reacted refractory metal-S3 alloy or a reacted transition metal-S3 alloy, respectively.

Referring to FIGS. 1 and 4 to 6, the semiconductor material alloy 106 has sufficient doping at the surface so that a low contact resistivity interface to the metal contact 101 can be provided. In some embodiments, the semiconductor material alloy 106 has sufficient doping so that carriers effectively find that there are no barriers in the on-state of the element. The curve of the stepped composition of the semiconductor material alloy 106 can also be adjusted to optimize device function, such as reducing diffusion into the channel. In some embodiments, lightly doped extensions can also be formed. In some embodiments, once the extension of light doping (from the source/drain toward the channel) is reached, the position of the band edge of the material used does not change significantly. In other words, the composition step can be sufficiently included in the highly doped region, and the interface to the semiconductor material S1 should also be included in the highly doped region of the source/drain region.

7 is a schematic diagram of the compositional step curve of the semiconductor material alloy 106 from the channel region 100 to the intermediate semiconductor material as the interface to the metal contact 101 in some embodiments according to the present invention. According to FIG. 7, the semiconductor material S2 is selected for the channel region 100 and is also selected for inclusion in the semiconductor material alloy 106 together with the semiconductor material S3. In addition, according to the relationship S2 _x S3 _1-x , the composition step curve of the alloy including S2 and S3 is provided, wherein in the source/drain region 107, the interface 102 between the channel region 100 and the semiconductor material alloy 106 is at x =1, and x=0 at an intermediate position where an interface is provided in the source/drain region 107 to the illustrated fourth semiconductor material S4 (hereinafter simply referred to as semiconductor material S4).

It should be understood that all semiconductor materials (S2 and S3) are stable or meta-stable within the thermal budget used in the processing and application of the device. In addition, during the epitaxial growth of the semiconductor material alloy 106, the semiconductor material may be correspondingly doped for the pMOS or nMOS element. It should be understood that although the composition step shown in FIG. 7 appears as a nonlinear function, other types of step changes (eg, continuous step changes or stepped step changes and other types) may be used.

It should be understood that the compositional steps in the semiconductor material alloy 106 should be provided smoothly (ie, in the source/drain region 107, provide a small change in the value of x in the composition) and provide a doping level to allow shielding Any barriers to carrier transmission are effectively reduced, otherwise the barriers to carrier transmission may rise due to changes in the band edge position of the entire semiconductor material alloy 106 due to the step change.

For most carriers of the device, between the band edges, the semiconductor material S4 is substantially different from the semiconductor material S3 so that a relatively small offset (ie, equal to or less than about 0.2 eV is formed between the two ) Heterojunction. It should be further understood that in cases where there is a small band shift at the heterojunction, sufficient doping may be applied to the heterojunction to shield any barriers to carrier flow at the heterojunction.

It should be further understood that the semiconductor material S4 is also selected to provide a relatively small Schottky barrier height (eg, equal to or less than about 0.2 eV) to the metal contact 101. In some embodiments according to the present invention, the metal contact 101 may be a reacted metal contact (for example, a metal or a metal-containing material generated by the reaction between the metal material and the semiconductor material S4). In some embodiments according to the present invention, doping may be applied at the interface between the semiconductor material S4 and the metal contact 101 to provide low interface contact resistivity.

In the example of the pMOS device using the stepped composition illustrated in FIG. 7, the semiconductor material S4 may be germanium (Ge) or high-Ge SiGe alloy (high-Ge SiGe alloy), and has antimony as S3 A heterojunction of gallium (GaSb) or indium gallium antimonide (InGaSb) alloy, which then steps toward another III-V material (S2) in the channel. In some embodiments of the pMOS device, S4 may be a high-Ge SiGe alloy with a heterojunction to the indium arsenide (InAs) alloy as S3, which then faces the channel region 100 InGaAs (S2) step change.

8 is a schematic diagram of two step composition curves of two semiconductor material alloys in the source/drain region 107 in some embodiments according to the present invention. According to FIG. 8, the first-order variable composition alloy (referred to as alloy 1 in FIG. 8) may include semiconductor material S2 and semiconductor material S3 and have a compositional step change, which makes the first-order variable composition alloy free and At the interface of the channel region 100, S2 is changed to semiconductor material S3 at the interface with the second-order variable composition alloy (referred to as alloy 2 in FIG. 8). A second order variable composition alloy is located in the source/drain region between the channel region and the first order variable composition alloy. As shown in FIG. 8, the second-order variable composition alloy includes a fourth semiconductor material S4 (hereinafter referred to as semiconductor material S4) and a fifth semiconductor material S5 (hereinafter referred to as semiconductor material S5), and is at the interface with the semiconductor material S3 Semiconducting The bulk material S4 transitions to the semiconductor material S5 to provide the metal contact interface portion 105 to the metal contact 101. The fifth semiconductor material is not completely miscible with the first semiconductor material. It should be understood that no matter where the heterojunction exists in the diagram shown in FIG. 8, the energy band offset at the heterojunction is small, preferably less than about 0.2 eV, and can be used across the heterojunction Doping. In some embodiments of nMOS devices where S1 is high Ge SiGe (for example, 90% or more is germanium (Ge)) or germanium (Ge), S2=S1, S3 may be Is a silicon germanium (SiGe) alloy with a lower germanium (Ge) content (for example, silicon germanium (SiGe) with 60% germanium (Ge)), S4 may be gallium arsenide (GaAs), and S5 may be arsenide Indium (InAs). In some embodiments of nMOS devices where S1 is high Ge SiGe (for example, 90% or more is germanium (Ge)) or germanium (Ge), S2=S1, S3 may be Is a silicon germanium (SiGe) alloy with a lower germanium (Ge) content (for example, silicon germanium (SiGe) with 60% germanium (Ge)), S4 may be gallium arsenide (GaAs), and S5 may be arsenide Indium (InAs). S1 and S2 in the channel may be indium-gallium-antimony (In-Ga-Sb) alloy pMOS device in some embodiments, S3 may be indium-gallium-antimony (In-Ga-Sb) alloy, S4 It may be a silicon germanium (SiGe) alloy, and S5 may be a high germanium silicon germanium (high Ge SiGe) alloy or germanium (Ge).

As described herein, in some embodiments according to the present invention, for the device, a semiconductor alloy (composed of components S2 and S3) can be formed between the channel region and the metal contact with a smooth step change Structure), and provide a low resistivity contact to the semiconductor material (S1) in the channel region. For example, the compositional step in the semiconductor alloy may be such that the contribution of S2 and S3 in the alloy gradually changes with the position in the source/drain region. For example, the alloy composition step can be set so that The resulting semiconductor alloy is essentially S2 near the channel region, and the semiconductor alloy is essentially S3 at the metal contact away from the channel region.

In addition, the semiconductor materials contained in the alloy (consisting of components S2 and S3) can each be selected to have a specific relationship with respect to the semiconductor material (S1) in the channel. For example, the semiconductor material S2 may be selected to have an energy band edge that is relatively close to the energy band edge of the semiconductor material S1 (ie, a low energy band edge offset) compared to the energy band edge of the semiconductor material S3. However, the semiconductor material S3 may be selected to have a relatively large band edge offset relative to the channel semiconductor material S1. The semiconductor material S3 can be selected to have a low contact resistivity for metal contacts (preferably 10 ^-8 ohm-square centimeter or less than 10 ^-8 ohm-square centimeter, and in some embodiments 10 ^-7 ohm- Square centimeters or less than 10 ^-7 ohm-square centimeters). In addition, the compositional steps of the semiconductor alloy (composed of component S2 and component S3) in the source/drain region should be smooth to avoid energy bands in the source/drain region for the relevant carriers Any sudden change on the edge.

Therefore, as understood by the inventor of the present invention, the semiconductor material S1 and the semiconductor material S3 in the channel region are selected so that one of them (for example, S3) cannot be changed from the other by using a continuous composition step ( For example, S1) obtained. In other words, the semiconductor material S2 can be used as an intermediate material that is relatively close to the band edge of S1 but can also be present in the alloy together with S3.

The above disclosed subject matter is to be understood as illustrative rather than limiting, and the scope of the accompanying patent application is intended to cover all such retouching, enhancements, and other embodiments that fall within the true spirit and scope of the inventive concept. Therefore, in the To a large extent, the scope of the present invention will be determined by the broadest permissible interpretation of the following patent applications and their equivalents, and should not be limited or limited to the above detailed description.

100: channel area

101: metal contacts

102: Interface

105: Metal contact interface part

106: Semiconductor material alloy

107: source/drain region

Claims (16)

A semiconductor device, including: a channel region, including a first semiconductor material, the first semiconductor material is used to transport majority carriers in the channel region during operation of the semiconductor device; metal contacts; source/drain Region, comprising a semiconductor material alloy, the semiconductor material alloy comprising a second semiconductor material; and at least one heterojunction, located in the source/drain region between the metal contact and the channel region, wherein The heterojunction forms a band edge shift of less than or equal to about 0.2 electron volts for the majority carrier, wherein the semiconductor material alloy includes a stepped composition of the second semiconductor material and the third semiconductor material , Wherein the third semiconductor material is not completely miscible with the first semiconductor material, and wherein the stepped composition of the semiconductor material alloy is contained at the interface with the first semiconductor material of the channel region rich Concentration of the second semiconductor material and a depleted concentration of the third semiconductor material, and progressing to a depleted concentration of the second semiconductor material and an enriched concentration of the first semiconductor material at the interface with the metal contact Three semiconductor materials. The semiconductor device according to item 1 of the patent application range, wherein the heterojunction is doped with a dopant type corresponding to the conductivity of the majority carrier. The semiconductor element as described in item 1 of the patent application range, wherein the stepped composition of the semiconductor material alloy is provided by S2 _x S3 _1-x , where S3 is the third semiconductor material and S2 is the first Two semiconductor materials, and x=0 at the interface with the metal contact, and x=1 at the interface with the first semiconductor material. The semiconductor element according to item 3 of the patent application range, wherein the increase in the stepped composition of the semiconductor material alloy is configured to prevent the band shift between adjacent steps in the stepped composition from being greater than about 0.2 eV. The semiconductor element according to item 1 of the patent application range, wherein the metal contact and the respective materials of the second semiconductor material or the semiconductor material alloy at the interface with the metal contact are selected as A Schottky barrier height equal to about 0.2 eV or less is provided therebetween. The semiconductor device according to item 1 of the scope of the patent application, wherein the stepped composition is a linear stepped composition, a non-linear stepped composition, a stepped stepped composition, or a combination thereof. The semiconductor device according to item 1 of the patent application range, wherein the first semiconductor material includes at least one group IV semiconductor element, and the second semiconductor material includes a group III-V semiconductor compound or a group III-V semiconductor alloy, and The semiconductor material alloy includes the third semiconductor material and the second semiconductor material. The semiconductor element according to item 1 of the patent application range, wherein the semiconductor element includes an NMOS element, and the first semiconductor material includes Si, SiGe alloy, or Ge, and the third semiconductor material includes InAs, InN, In -As-N alloy, In-Al-As alloy, or In-Ga-As alloy, and the second semiconductor material includes GaAs, In-Ga-N, In-Ga-As-N alloy, In-Al- Ga-As alloy or Al-Ga-As alloy. A semiconductor device, including: a channel region, including a first semiconductor material, the first semiconductor material is used to transport majority carriers in the channel region during operation of the semiconductor device; metal contacts; source/drain Region, comprising a semiconductor material alloy, the semiconductor material alloy comprising a second semiconductor material; and at least one heterojunction, located in the source/drain region between the metal contact and the channel region, wherein The heterojunction forms a band edge shift of less than or equal to about 0.2 electron volts for the majority carrier, wherein the semiconductor material alloy includes a stepped composition of the second semiconductor material and the third semiconductor material , And wherein the stepped composition of the semiconductor material alloy includes an enriched concentration of the first semiconductor material and a poor concentration of the second semiconductor material at an interface with the first semiconductor material of the channel region A semiconductor material, and progresses to a lean concentration of the first semiconductor material and an enriched concentration of the second semiconductor material at the interface to form the at least one heterojunction with the third semiconductor material, wherein The third semiconductor material is not completely miscible with the first semiconductor material. A semiconductor device, including: a channel region, including a first semiconductor material, the first semiconductor material is used to transport majority carriers in the channel region during operation of the semiconductor device; metal contacts; source/drain Zone, containing a semiconductor material alloy, the semiconductor material alloy package Containing a second semiconductor material; and at least one heterojunction in the source/drain region between the metal contact and the channel region, wherein the heterojunction is for the majority carrier A band edge shift of less than or equal to about 0.2 electron volts is formed, wherein the semiconductor material alloy includes a stepped composition of the second semiconductor material and a third semiconductor material, wherein the third semiconductor material does not The first semiconductor material is completely miscible, and wherein the semiconductor material alloy includes a first-order variable composition alloy of the second semiconductor material and the third semiconductor material, and the semiconductor element further includes: a second-order variable composition alloy , Located in the source/drain region between the channel region and the first order variable composition alloy, the second order variable composition alloy includes a stepped composition of a fourth semiconductor material and a fifth semiconductor material , Wherein the fifth semiconductor material is not completely miscible with the first semiconductor material. An electronic component, including: a channel region including a first semiconductor material used for transporting a majority carrier in the channel region during operation of the electronic component; metal contacts; and source/drain The pole region contains a material alloy that contains at least one material component and does not contain any component of the first semiconductor material, so that the material alloy is in the channel region and in contact with the metal The compositional step change between the interfaces of the avoids the sudden change of the band edge shift between the increase of the compositional step change and at any of the heterojunctions, Wherein the first semiconductor material and the material alloy at the interface with the first semiconductor material form a heterojunction with an energy band edge shift of less than or equal to about 0.2 eV for the majority carrier surface. The electronic component as described in item 11 of the patent application range, wherein for the majority carrier, the band edge shift is less than or equal to about 0.1 eV. The electronic component as described in item 12 of the patent application range, wherein the material alloy is doped to a range of about 1×10 ¹⁸ cm ⁻³ to about 1×10 ²⁰ cm ⁻³ . The electronic component of claim 13 of the patent application range, wherein the band edge offset between the increments is between about 0.1 eV within about 6 nm and about 0.1 eV within about 0.6 nm between. An electronic component terminal structure, including: a metal contact; a stepped composition layer including second materials (S2) combined with each other according to the stepped composition in the stepped composition layer represented by S2 _x S3 _1-x And a third material (S3), wherein the step-wise composition of the step-wise composition layer is approximately S2 near the metal contact, that is, x=0, and the step-wise composition layer's The stepwise composition is approximately S1, ie x=1, away from the metal contact, and the stepwise composition of the stepwise composition layer between x=0 and x=1 is sufficient to avoid For the selected carrier of the terminal structure of the electronic component, the band edge shift in the stepped composition layer is greater than 0.2 electron volts; the third material S3, which contacts the stepped composition layer at x=1, S3 is It is selected to form a heterojunction equal to or less than about 0.2 eV with S1; and wherein S2 is selected to provide a Schottky barrier height equal to or less than about 0.2 eV to the metal contact. An electronic component terminal structure as described in item 15 of the patent application scope, wherein S1, S2, and S3 are configured to operate as separate semiconductor materials in the electronic component terminal structure.

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