TW201917895A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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TW201917895A
TW201917895A TW106136584A TW106136584A TW201917895A TW 201917895 A TW201917895 A TW 201917895A TW 106136584 A TW106136584 A TW 106136584A TW 106136584 A TW106136584 A TW 106136584A TW 201917895 A TW201917895 A TW 201917895A
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channel structure
gate
source
drain
semiconductor device
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TW106136584A
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Chinese (zh)
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辛裕明
陳鴻儒
尤姿予
林峻緯
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國立中央大學
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Abstract

A semiconductor device is provided. The semiconductor device includes a source, a drain, a composite channel structure and a gate structure. The source has a first conductive type. The drain has a second conductive type. The composite channel structure is located between the source and the drain along a first direction. The composite channel structure includes a first channel structure and a second channel structure. The first channel structure is located between the source and the second channel structure, and has a first bandgap. The second channel structure is located between the first channel structure and the drain, and has a second bandgap. The first bandgap is less than the second bandgap. The gate structure is abutted with the composite channel structure along a second direction. The first direction is intersected with the second direction.

Description

半導體元件Semiconductor component

本發明是有關於一種半導體元件,且特別是有關於一種場效電晶體。This invention relates to a semiconductor component and, more particularly, to a field effect transistor.

隨著積體電路的發展,不斷縮短半導體元件的特徵尺寸。對於場效電晶體而言,縮短特徵尺寸會帶來例如是次臨界擺幅(subthreshold swing)提高的問題。對此,一般以漂移-擴散(drift-diffusion)機制控制開關的場效電晶體難以有效地降低次臨界擺幅。With the development of integrated circuits, the feature size of semiconductor components is continuously shortened. For field effect transistors, shortening the feature size can cause problems such as an increase in subthreshold swing. In this regard, it is difficult to effectively reduce the sub-threshold swing by controlling the field effect transistor of the switch with a drift-diffusion mechanism.

相較而言,以能帶間穿遂(band to band tunneling)機制控制開關的穿遂式場效電晶體(tunneling FET)可進一步降低次臨界擺幅。然而,對於目前的穿遂式場效電晶體而言,難以在不影響導通電流(on current)的情況下降低漏電流。In contrast, a tunneling FET that controls the switch with a band to band tunneling mechanism can further reduce the sub-threshold swing. However, for current through-type field effect transistors, it is difficult to reduce the leakage current without affecting the on current.

本發明提供一種半導體元件,可在實質上不影響導通電流的情況下降低漏電流。The present invention provides a semiconductor element capable of reducing leakage current without substantially affecting an on current.

本發明的半導體元件包括源極、汲極、複合通道結構以及閘極結構。源極具有第一導電型。汲極具有第二導電型。複合通道結構在第一方向上位於源極與汲極之間。複合通道結構包括第一通道結構與第二通道結構。第一通道結構位於源極與第二通道結構之間,且具有第一能隙。第二通道結構位於第一通道結構與汲極之間,且具有第二能隙。第一能隙小於第二能隙。閘極結構在第二方向上鄰接於複合通道結構。第一方向與第二方向交錯。The semiconductor device of the present invention includes a source, a drain, a composite channel structure, and a gate structure. The source has a first conductivity type. The drain has a second conductivity type. The composite channel structure is located between the source and the drain in a first direction. The composite channel structure includes a first channel structure and a second channel structure. The first channel structure is between the source and the second channel structure and has a first energy gap. The second channel structure is located between the first channel structure and the drain and has a second energy gap. The first energy gap is smaller than the second energy gap. The gate structure is adjacent to the composite channel structure in the second direction. The first direction is interleaved with the second direction.

在本發明的一實施例中,第一能隙小於源極的能隙。In an embodiment of the invention, the first energy gap is smaller than the energy gap of the source.

在本發明的一實施例中,第一能隙等於源極的能隙。In an embodiment of the invention, the first energy gap is equal to the energy gap of the source.

在本發明的一實施例中,第一通道結構具有第一傳導帶與第一價帶,第二通道結構具有第二傳導帶與第二價帶。第一傳導帶低於第二傳導帶,且第一價帶低於、高於或齊平於第二價帶;或第一傳導帶齊平於第二傳導帶,且第一價帶低於或高於第二價帶。In an embodiment of the invention, the first channel structure has a first conduction band and a first valence band, and the second channel structure has a second conduction band and a second valence band. The first conduction band is lower than the second conduction band, and the first valence band is lower, higher or flush with the second valence band; or the first conduction band is flush with the second conduction band, and the first valence band is lower than Or higher than the second price band.

在本發明的一實施例中,閘極結構包括第一閘極結構與第二閘極結構。第一閘極結構與第二閘極結構分別在第二方向上鄰接於複合通道結構的相對的兩側上。In an embodiment of the invention, the gate structure includes a first gate structure and a second gate structure. The first gate structure and the second gate structure are respectively adjacent to opposite sides of the composite channel structure in the second direction.

在本發明的一實施例中,第一閘極結構包括第一閘介電層與第一閘極。第一閘介電層位於第一閘極與複合通道結構之間。第二閘極結構包括第二閘介電層與第二閘極。第二閘介電層位於第二閘極與複合通道結構之間。In an embodiment of the invention, the first gate structure includes a first gate dielectric layer and a first gate. The first gate dielectric layer is between the first gate and the composite channel structure. The second gate structure includes a second gate dielectric layer and a second gate. The second gate dielectric layer is between the second gate and the composite channel structure.

在本發明的一實施例中,上述的半導體元件更包括源極接觸層與汲極接觸層。源極接觸層連接於源極,且汲極接觸層連接於汲極。In an embodiment of the invention, the semiconductor device further includes a source contact layer and a drain contact layer. The source contact layer is connected to the source and the drain contact layer is connected to the drain.

在本發明的一實施例中,源極、汲極以及複合通道結構的材料包括IV族半導體、III-V族化合物半導體、II-VI族化合物半導體、或其組合。In an embodiment of the invention, the material of the source, drain and composite channel structures comprises a Group IV semiconductor, a III-V compound semiconductor, a II-VI compound semiconductor, or a combination thereof.

在本發明的一實施例中,第一通道結構的材料的元素種類相異於第二通道結構的材料的元素種類。In an embodiment of the invention, the elemental species of the material of the first channel structure is different from the elemental species of the material of the second channel structure.

在本發明的一實施例中,第一通道結構的材料與第二通道結構的材料包括相同的元素種類,且元素比例彼此相異。In an embodiment of the invention, the material of the first channel structure and the material of the second channel structure comprise the same element type, and the element ratios are different from each other.

基於上述,本發明實施例的半導體元件包括複合通道結構。複合通道結構包括低能隙的第一通道結構與高能隙的第二通道結構。如此一來,在半導體元件的關閉狀態時,高能隙的第二通道結構可形成能障以阻擋由源極穿遂至複合通道結構的漏電流。此外,在半導體的關閉狀態時,源極的價帶中的電子不易跨越第一通道結構所形成的位能井,故難以由源極經複合通道結構而移動至汲極。另一方面,在半導體元件的導通狀態時,高能隙的第二通道結構所形成的能障被降低,而實質上不會影響導通電流。如此一來,可在實質上不影響導通電流的情況下抑制半導體元件的漏電流。Based on the above, the semiconductor element of the embodiment of the present invention includes a composite channel structure. The composite channel structure includes a first channel structure of low energy gap and a second channel structure of high energy gap. As such, in the closed state of the semiconductor component, the high-gap second channel structure can form an energy barrier to block leakage current from the source to the composite channel structure. In addition, in the off state of the semiconductor, electrons in the valence band of the source are less likely to cross the potential well formed by the first channel structure, so that it is difficult to move from the source to the drain via the composite channel structure. On the other hand, in the on state of the semiconductor element, the energy barrier formed by the second channel structure of the high energy gap is reduced without substantially affecting the on current. In this way, the leakage current of the semiconductor element can be suppressed without substantially affecting the on current.

為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.

圖1是依照本發明一些實施例的半導體元件的示意圖。1 is a schematic illustration of a semiconductor component in accordance with some embodiments of the present invention.

請參照圖1,本發明實施例的半導體元件100為一種穿遂式場效電晶體(tunneling FET)。半導體元件100包括源極102、汲極104、複合通道結構(composite channel structure)106以及閘極結構108。在一些實施例中,源極102、汲極104以及複合通道結構106皆可為磊晶層(epitaxial layer),但本發明並不以半導體元件100的製造方法為限。Referring to FIG. 1, a semiconductor device 100 of an embodiment of the present invention is a tunneling field effect transistor (tunneling FET). The semiconductor device 100 includes a source 102, a drain 104, a composite channel structure 106, and a gate structure 108. In some embodiments, the source 102, the drain 104, and the composite channel structure 106 may each be an epitaxial layer, but the present invention is not limited to the method of manufacturing the semiconductor device 100.

源極102與汲極104在第一方向D1上排列。源極102與汲極104的材料可包括IV族半導體、III-V族化合物半導體、II-VI族化合物半導體或其組合。舉例而言,源極102與汲極104的材料可分別包括矽、鍺、碳化矽、矽化鍺、砷化鎵、砷化鋁、砷化銦、砷化銦鎵、砷化鋁鎵、磷化銦、磷化銦鎵、氮化鎵、氮化鋁、氮化銦鎵、氮化鋁鎵、銻化鎵、銻化鋁、銻化銦、銻砷化鎵、氧化鋅、硫化鋅、氧化鎂鋅或其組合。在圖1所示的實施例中,源極102的材料相異於汲極104的材料。舉例而言,源極102的材料可為銻砷化鎵,且汲極104的材料可為砷化銦鎵。在其他實施例中,源極102的材料亦可相同於汲極104的材料,例如是砷化銦鎵。此外,所屬領域中具有通常知識者可依據設計需求而調整化合物半導體中各元素所佔的比例,本發明並不以此為限。The source 102 and the drain 104 are arranged in the first direction D1. The material of the source 102 and the drain 104 may include a Group IV semiconductor, a III-V compound semiconductor, a II-VI compound semiconductor, or a combination thereof. For example, the materials of the source 102 and the drain 104 may include tantalum, niobium, tantalum carbide, tantalum telluride, gallium arsenide, aluminum arsenide, indium arsenide, indium gallium arsenide, aluminum gallium arsenide, phosphating. Indium, indium gallium phosphide, gallium nitride, aluminum nitride, indium gallium nitride, aluminum gallium nitride, gallium antimonide, aluminum telluride, indium antimonide, antimony gallium arsenide, zinc oxide, zinc sulfide, magnesium oxide Zinc or a combination thereof. In the embodiment shown in FIG. 1, the material of the source 102 is different from the material of the drain 104. For example, the material of the source 102 may be gallium germanium arsenide, and the material of the drain 104 may be indium gallium arsenide. In other embodiments, the material of the source 102 may be the same as the material of the drain 104, such as indium gallium arsenide. In addition, those skilled in the art can adjust the proportion of each element in the compound semiconductor according to the design requirements, and the invention is not limited thereto.

源極102可經摻雜以具有第一導電型,而汲極104可經摻雜以具有第二導電型。在一些實施例中,第一導電型為P型,且第二導電型為N型。如此一來,半導體元件100可為N型的穿遂式場效電晶體。在其他實施例中,第一導電型可為N型,且第二導電型可為P型。換言之,半導體元件100亦可為P型的穿遂式場效電晶體。P型的摻質可包括碳或鎂、鈹、鋅或其組合,而N型的摻質可包括矽、錫、銻或其組合。在一些實施例中,源極102的摻雜濃度範圍為1018 至1021 cm-3 。汲極104的摻雜濃度範圍為1018 至1021 cm-3The source 102 can be doped to have a first conductivity type, and the drain 104 can be doped to have a second conductivity type. In some embodiments, the first conductivity type is a P type and the second conductivity type is an N type. As such, the semiconductor component 100 can be an N-type via-type field effect transistor. In other embodiments, the first conductivity type can be N-type and the second conductivity type can be P-type. In other words, the semiconductor device 100 can also be a P-type via-type field effect transistor. The P-type dopant may include carbon or magnesium, cerium, zinc, or a combination thereof, and the N-type dopant may include cerium, tin, antimony, or a combination thereof. In some embodiments, the source 102 has a doping concentration ranging from 10 18 to 10 21 cm -3 . The doping concentration of the drain 104 ranges from 10 18 to 10 21 cm -3 .

複合通道結構106位於源極102與汲極104之間。源極102、複合通道結構106以及汲極104沿著第一方向D1排列。複合通道結構106包括第一通道結構106a與第二通道結構106b。第一通道結構106a位於源極102與第二通道結構106b之間,且第二通道結構106b位於第一通道結構106a與汲極104之間。第一通道結構106a具有第一能隙,且第二通道結構106b具有第二能隙。第一能隙小於第二能隙。The composite channel structure 106 is located between the source 102 and the drain 104. The source 102, the composite channel structure 106, and the drain 104 are arranged along the first direction D1. The composite channel structure 106 includes a first channel structure 106a and a second channel structure 106b. The first channel structure 106a is between the source 102 and the second channel structure 106b, and the second channel structure 106b is located between the first channel structure 106a and the drain 104. The first channel structure 106a has a first energy gap and the second channel structure 106b has a second energy gap. The first energy gap is smaller than the second energy gap.

第一通道結構106a具有第一傳導帶與第一價帶,且第二通道結構106b具有第二傳導帶與第二價帶。在一些實施例中,第一傳導帶低於第二傳導帶,且第一價帶高於第二價帶。在一些實施例中,第一傳導帶低於第二傳導帶,且第一價帶齊平於第二價帶。在一些實施例中,第一傳導帶齊平於第二傳導帶,且第一價帶高於第二價帶。在一些實施例中,第一傳導帶低於第二傳導帶,且第一價帶低於第二價帶。在一些實施例中,第一傳導帶齊平於第二傳導帶,且第一價帶低於第二價帶。The first channel structure 106a has a first conduction band and a first valence band, and the second channel structure 106b has a second conduction band and a second valence band. In some embodiments, the first conduction band is lower than the second conduction band and the first valence band is higher than the second valence band. In some embodiments, the first conduction band is lower than the second conduction band and the first valence band is flush with the second valence band. In some embodiments, the first conduction band is flush with the second conduction band and the first valence band is higher than the second valence band. In some embodiments, the first conduction band is lower than the second conduction band and the first valence band is lower than the second valence band. In some embodiments, the first conductive strip is flush with the second conductive strip and the first valence band is lower than the second valence band.

第一通道結構106a的材料與第二通道結構106b的材料可包括IV族半導體、III-V族化合物半導體、II-VI族化合物半導體或其組合。在一些實施例中,第一通道結構106a的材料相異於第二通道結構106b的材料。舉例而言,第一通道結構106a的材料可為砷化銦鎵或磷化銦。第二通道結構106b的材料可為銻砷化鎵或磷化銦鎵。在其他實施例中,第一通道結構106a與第二通道結構106b的材料相同,但成分比例不同。舉例而言,第一通道結構106a與第二通道結構106b均為砷化銦鎵、銻砷化鎵或氮砷化鎵。藉由調整上述化合物中的元素比例,可使第一通道結構106a的第一能隙小於第二通道結構106b的第二能隙。The material of the first channel structure 106a and the material of the second channel structure 106b may include a Group IV semiconductor, a III-V compound semiconductor, a II-VI compound semiconductor, or a combination thereof. In some embodiments, the material of the first channel structure 106a is different than the material of the second channel structure 106b. For example, the material of the first channel structure 106a may be indium gallium arsenide or indium phosphide. The material of the second channel structure 106b may be gallium arsenide or indium gallium phosphide. In other embodiments, the first channel structure 106a is the same material as the second channel structure 106b, but differs in composition ratio. For example, the first channel structure 106a and the second channel structure 106b are both indium gallium arsenide, gallium arsenide or gallium arsenide. The first energy gap of the first channel structure 106a can be made smaller than the second energy gap of the second channel structure 106b by adjusting the ratio of elements in the above compound.

在一些實施例中,第一通道結構106b的第一能隙小於第二通道結構106b的第二能隙,且第一能隙小於源極102的能隙。舉例而言,在圖1所示的實施例中,第一通道結構106a的材料的元素種類相異於第二通道結構106b的材料的元素種類。舉例而言,第一通道結構106a的材料包括砷化銦鎵,而第二通道結構106b的材料包括銻砷化鎵。如此一來,第一通道結構106a可具有第一能隙且第二通道結構106b可具有第二能隙,且第一能隙小於第二能隙。因此,可在源極102與第一通道結構106b之間形成異質接面(heterojunction),且可降低電子由源極102穿遂至第一通道結構106a的等效穿遂能障(effective tunneling barrier)。因此,可提高半導體元件100的導通電流(on current)。In some embodiments, the first energy gap of the first channel structure 106b is smaller than the second energy gap of the second channel structure 106b, and the first energy gap is smaller than the energy gap of the source 102. For example, in the embodiment illustrated in FIG. 1, the elemental species of material of the first channel structure 106a is different from the elemental species of material of the second channel structure 106b. For example, the material of the first channel structure 106a includes indium gallium arsenide, and the material of the second channel structure 106b includes gallium arsenide. As such, the first channel structure 106a can have a first energy gap and the second channel structure 106b can have a second energy gap, and the first energy gap is smaller than the second energy gap. Therefore, a heterojunction can be formed between the source 102 and the first channel structure 106b, and an effective tunneling barrier for electrons to pass through the source 102 to the first channel structure 106a can be reduced. ). Therefore, the on current of the semiconductor element 100 can be improved.

在一些實施例中,複合通道結構106可未經摻雜,而為本質層(intrinsic layer)。在其他實施例中,複合通道結構106也可經摻雜以具有第一導電型或第二導電型。複合通道結構106的摻雜濃度可低於源極102與汲極104的摻雜濃度。舉例而言,複合通道結構106的摻雜濃度範圍可為1014 至1017 cm-3In some embodiments, the composite channel structure 106 can be undoped, but an intrinsic layer. In other embodiments, the composite channel structure 106 can also be doped to have a first conductivity type or a second conductivity type. The doping concentration of the composite channel structure 106 can be lower than the doping concentration of the source 102 and the drain 104. For example, the doping concentration of the composite channel structure 106 can range from 10 14 to 10 17 cm -3 .

第一通道結構106a在第一方向D1上具有第一長度L1,而第二通道結構106b在第一方向D1上具有第二長度L2。在一些實施例中,第一長度L1與第二長度L2的比值(L1/L2)大於0,且小於或等於14。在一些實施例中,第一長度L1與第二長度L2的比值(L1/L2)可為0.07至6.50。在另一些實施例中,第一長度L1與第二長度L2的比值(L1/L2)亦可為0.07至4。然而,所屬領域中具有通常知識者可依據元件特性分別調整第一長度與第二長度,本發明並不以此為限。The first channel structure 106a has a first length L1 in the first direction D1 and the second channel structure 106b has a second length L2 in the first direction D1. In some embodiments, the ratio (L1/L2) of the first length L1 to the second length L2 is greater than zero and less than or equal to 14. In some embodiments, the ratio (L1/L2) of the first length L1 to the second length L2 may be 0.07 to 6.50. In other embodiments, the ratio of the first length L1 to the second length L2 (L1/L2) may also be 0.07 to 4. However, those skilled in the art can adjust the first length and the second length respectively according to the characteristics of the components, and the invention is not limited thereto.

半導體元件100更包括閘極結構108。閘極結構108在第二方向D2上鄰接於複合通道結構106。第二方向D2交錯於第一方向D1。在一些實施例中,第二方向D2垂直於第一方向D1。在一些實施例中,閘極結構108包括第一閘極結構108a與第二閘極結構108b。第一閘極結構108a與第二閘極結構108b在第二方向D2上鄰接於複合通道結構106的相對的兩側上。相似地,閘介電層110可包括第一閘介電層110a與第二閘介電層110b,且閘極112可包括第一閘極112a與第二閘極112b。第一閘介電層110a位於第一閘極112a與複合通道結構106之間,而第二閘介電層110b位於第二閘極112b與複合通道結構106之間。第一閘介電層110a與第二閘介電層110b的材料可分別包括氧化矽、氮化矽、氧化鋁、氧化鉿或其組合。第一閘極112a與第二閘極112b的材料可分別包括鉑、鈦、鋁、金、鎵、鉛、鉭、鎘、銦或其組合。所屬領域中具有通常知識者可依據元件特性選用適當的閘介電層材料與閘極材料,本發明並不以此為限。在一些實施例中,第一閘介電層110a的材料可與第二閘介電層110b的材料相同或相異。相似地,第一閘極112a的材料可與第二閘極112b的材料相同或相異。在一些實施例中,閘極結構108亦可為單一閘極結構,或包括3個以上的閘極結構,本發明並不以閘極結構的數量為限。The semiconductor component 100 further includes a gate structure 108. Gate structure 108 is adjacent to composite channel structure 106 in a second direction D2. The second direction D2 is staggered in the first direction D1. In some embodiments, the second direction D2 is perpendicular to the first direction D1. In some embodiments, the gate structure 108 includes a first gate structure 108a and a second gate structure 108b. The first gate structure 108a and the second gate structure 108b are adjacent to opposite sides of the composite channel structure 106 in the second direction D2. Similarly, the gate dielectric layer 110 can include a first gate dielectric layer 110a and a second gate dielectric layer 110b, and the gate 112 can include a first gate 112a and a second gate 112b. The first gate dielectric layer 110a is between the first gate 112a and the composite channel structure 106, and the second gate dielectric layer 110b is between the second gate 112b and the composite channel structure 106. The materials of the first gate dielectric layer 110a and the second gate dielectric layer 110b may include tantalum oxide, tantalum nitride, aluminum oxide, tantalum oxide, or a combination thereof, respectively. The materials of the first gate 112a and the second gate 112b may respectively include platinum, titanium, aluminum, gold, gallium, lead, antimony, cadmium, indium or a combination thereof. Those skilled in the art can select appropriate gate dielectric material and gate material according to the characteristics of the device, and the invention is not limited thereto. In some embodiments, the material of the first gate dielectric layer 110a may be the same as or different from the material of the second gate dielectric layer 110b. Similarly, the material of the first gate 112a may be the same as or different from the material of the second gate 112b. In some embodiments, the gate structure 108 can also be a single gate structure, or include more than three gate structures, and the present invention is not limited to the number of gate structures.

在一些實施例中,半導體元件100更可包括源極接觸層114與汲極接觸層116。源極接觸層114連接於源極102,而汲極接觸層116連接於汲極104。在一些實施例中,源極接觸層114設置於源極102的相對於複合通道結構106的一側,而汲極接觸層116設置於汲極104的相對於複合通道結構106的一側。源極接觸層114的材料與汲極接觸層116的材料可分別包括金屬或金屬化合物。舉例而言,源極接觸層114的材料與汲極接觸層116的材料可分別包括鉑、鈦、鋁、金、鎵、鉛、鉭、鎘、銦或其組合,本發明並不以此為限。藉由設置源極接觸層114與汲極接觸層116,可分別降低源極102的接觸電阻(contact resistance)與汲極104的接觸電阻。In some embodiments, the semiconductor device 100 further includes a source contact layer 114 and a gate contact layer 116. The source contact layer 114 is connected to the source 102, and the drain contact layer 116 is connected to the drain 104. In some embodiments, the source contact layer 114 is disposed on a side of the source 102 relative to the composite channel structure 106 and the gate contact layer 116 is disposed on a side of the drain 104 opposite the composite channel structure 106. The material of the source contact layer 114 and the material of the gate contact layer 116 may each comprise a metal or a metal compound. For example, the material of the source contact layer 114 and the material of the gate contact layer 116 may respectively include platinum, titanium, aluminum, gold, gallium, lead, antimony, cadmium, indium or a combination thereof, and the present invention does not limit. By providing the source contact layer 114 and the drain contact layer 116, the contact resistance of the source 102 and the contact resistance of the drain 104 can be reduced, respectively.

圖2A是圖1的半導體元件100在導通狀態的能帶圖(band diagram)。圖2B是圖1的半導體元件100在關閉狀態的能帶圖。在圖2A與圖2B中,半導體元件100為N型穿遂場效電晶體。能帶包括傳導帶CB(conduction band)以及價帶VB(valence band)。區域A為源極102的能帶,區域B1為第一通道結構106a的能帶,區域B2為第二導通結構106b的能帶且區域C為汲極104的能帶。請參照圖2A與圖2B,由於複合通道結構106由低能隙的第一通道結構106a與高能隙的第二通道結構106b構成,故傳導帶CB與價帶VB在區域B1中形成位能井(potential well)且在區域B2中形成能障(potential barrier)。FIG. 2A is a band diagram of the semiconductor device 100 of FIG. 1 in an on state. FIG. 2B is an energy band diagram of the semiconductor device 100 of FIG. 1 in a closed state. In FIGS. 2A and 2B, the semiconductor device 100 is an N-type field-effect transistor. The energy band includes a conduction band CB (conduction band) and a valence band VB (valence band). The region A is the energy band of the source 102, the region B1 is the energy band of the first channel structure 106a, the region B2 is the energy band of the second conduction structure 106b, and the region C is the energy band of the drain 104. Referring to FIG. 2A and FIG. 2B, since the composite channel structure 106 is composed of a low energy gap first channel structure 106a and a high energy gap second channel structure 106b, the conduction band CB and the valence band VB form a potential energy well in the region B1 ( Potential well) and forming a potential barrier in region B2.

請參照圖1與圖2A,當閘極結構108對於源極102具有大於起始電壓(threshold voltage)的正偏壓且汲極104對於源極102具有正偏壓時,半導體元件100為導通狀態(on-state)。如圖2A中的箭號所示,源極102的價帶中的電子能夠以能帶間穿遂(band to band tunneling)的方式穿遂至第一通道結構106a。在導通狀態時,複合通道結構106(區域B1與區域B2)的能帶降低。因此,穿遂至第一通道結構106a的電子可跨過區域B1中傳導帶CB的能障,而移動至汲極104以形成導通電流(on current)。Referring to FIG. 1 and FIG. 2A, when the gate structure 108 has a positive bias voltage greater than a threshold voltage for the source 102 and the gate 104 has a positive bias voltage with respect to the source 102, the semiconductor device 100 is turned on. (on-state). As indicated by the arrows in Figure 2A, electrons in the valence band of source 102 can be tunneled to first channel structure 106a in a band to band tunneling manner. In the on state, the energy band of the composite channel structure 106 (region B1 and region B2) is reduced. Thus, electrons that pass through the first channel structure 106a can cross the energy barrier of the conduction band CB in region B1 and move to the drain 104 to form an on current.

請參照圖1與圖2B,當閘極結構108對於源極102的偏壓小於起始電壓時,半導體元件100為關閉狀態(off state)。在關閉狀態時,源極102的價帶中的電子仍能夠穿遂至第一通道結構106a。然而,在關閉狀態時,複合通道結構106(區域B1與區域B2)的能帶並未被降低。因此,如圖2B的漏電路徑LC1所示,穿遂至第一通道結構106a的電子難以跨越區域B2中傳導帶CB的能障而移動至汲極104,故可降低漏電流。另一方面,如圖2B的漏電路徑LC2所示,源極102的價帶中的電子需跨過區域B1中價帶VB的位能井,方可在閘極結構108對於源極102具有負偏壓時以穿遂的方式移動至汲極104。換言之,可降低半導體元件100的雙極性導通(ambipolar conduction)的情形。Referring to FIGS. 1 and 2B, when the bias voltage of the gate structure 108 with respect to the source 102 is less than the initial voltage, the semiconductor device 100 is in an off state. In the off state, electrons in the valence band of source 102 can still pass through to first channel structure 106a. However, in the off state, the energy band of the composite channel structure 106 (area B1 and region B2) is not reduced. Therefore, as shown by the leakage path LC1 of FIG. 2B, electrons that pass through the first channel structure 106a are difficult to move to the drain 104 across the energy barrier of the conduction band CB in the region B2, so that leakage current can be reduced. On the other hand, as shown by the leakage path LC2 of FIG. 2B, the electrons in the valence band of the source 102 need to cross the potential well of the valence band VB in the region B1, so that the gate structure 108 is negative to the source 102. When biased, it moves to the drain 104 in a twisting manner. In other words, the situation of the ambipolar conduction of the semiconductor element 100 can be reduced.

圖3是依照本發明另一些實施例的半導體元件300的示意圖。3 is a schematic diagram of a semiconductor device 300 in accordance with further embodiments of the present invention.

請參照圖1與圖3,圖3所示的半導體元件300相似於圖1所示的半導體元件100。兩者的差異在於半導體元件300源極302的能隙等於第一通道結構106a的第一能隙。在一些實施例中,源極302的材料可相同於第一通道結構106a與汲極104的材料,例如是砷化銦鎵。如此一來,源極302與第一通道結構106a之間可為同質接面(homojunction)。Referring to FIGS. 1 and 3, the semiconductor device 300 shown in FIG. 3 is similar to the semiconductor device 100 shown in FIG. The difference between the two is that the energy gap of the source 302 of the semiconductor device 300 is equal to the first energy gap of the first channel structure 106a. In some embodiments, the material of the source 302 can be the same as the material of the first channel structure 106a and the drain 104, such as indium gallium arsenide. As such, the source 302 and the first channel structure 106a may be homojunctions.

接下來,以實驗例1至實驗例13以及比較例1、2來驗證本發明實施例的功效。Next, the effects of the examples of the present invention were verified by Experimental Example 1 to Experimental Example 13 and Comparative Examples 1 and 2.

請參照圖1,在實驗例1-13中,半導體元件100為N型穿遂式場效電晶體。源極102與第二通道結構106b的材料為GaAs0.51 Sb0.49 。源極102經摻雜為P型,其中摻質為碳且摻雜濃度為5´1019 cm-3 。第二通道結構106b為未經摻雜的本質層。第一通道結構106a與汲極104的材料為In0.53 Ga0.47 As。汲極104經摻雜為N型,其中摻質為矽且摻雜濃度為1´1019 cm-3 。第一通道結構106a為未經摻雜的本質層。在第一方向D1上,源極102與汲極104的長度分別為300 nm與200 nm。第一閘介電層110a與第二閘介電層110b均為氧化鉿,且其厚度為5 nm。第一閘極112a與第二閘極112b的材料為白金。源極接觸層114與汲極接觸層116的材料為鈦-金合金。Referring to FIG. 1, in Experimental Example 1-13, the semiconductor device 100 is an N-type via-type field effect transistor. The material of the source 102 and the second channel structure 106b is GaAs 0.51 Sb 0.49 . The source 102 is doped to a P type in which the dopant is carbon and the doping concentration is 5 ́10 19 cm -3 . The second channel structure 106b is an undoped intrinsic layer. The material of the first channel structure 106a and the drain 104 is In 0.53 Ga 0.47 As. The drain 104 is doped to be N-type, wherein the dopant is germanium and the doping concentration is 1 ́10 19 cm -3 . The first channel structure 106a is an undoped intrinsic layer. In the first direction D1, the lengths of the source 102 and the drain 104 are 300 nm and 200 nm, respectively. The first gate dielectric layer 110a and the second gate dielectric layer 110b are both hafnium oxide and have a thickness of 5 nm. The material of the first gate 112a and the second gate 112b is platinum. The material of the source contact layer 114 and the gate contact layer 116 is a titanium-gold alloy.

請參照下表1,實驗例1至實驗例13的複合通道結構106在第一方向D1上的總長(亦即第一長度L1與第二長度L2的總和)皆為150 nm。實驗例1至實驗例13的第一長度L1分別為130 nm、120 nm、110 nm、100 nm、90 nm、80 nm、70 nm、60 nm、50 nm、40 nm、30 nm、20 nm以及10 nm。此外,實驗例1至實驗例13的第二長度L2分別為20 nm、30 nm、40 nm、50 nm、60 nm、70 nm、80 nm、90 nm、100 nm、110 nm、120 nm、130 nm以及140 nm。Referring to Table 1 below, the total length of the composite channel structure 106 of Experimental Examples 1 to 13 in the first direction D1 (that is, the sum of the first length L1 and the second length L2) is 150 nm. The first lengths L1 of the experimental examples 1 to 13 are 130 nm, 120 nm, 110 nm, 100 nm, 90 nm, 80 nm, 70 nm, 60 nm, 50 nm, 40 nm, 30 nm, 20 nm, and 10 nm. In addition, the second lengths L2 of the experimental examples 1 to 13 are 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130, respectively. Nm and 140 nm.

另一方面,比較例1、2的半導體元件與實驗例1至實驗例13的半導體元件相似。比較例1與實驗例1-13的差異僅在於比較例1的通道結構並非圖1所示的複合通道結構106。比較例1的通道結構僅包括低能隙的第一通道結構,而並未包括高能隙的第二通道結構。另外,比較例2與比較例1的差異在於比較例2的通道結構僅包括高能隙的第二通道結構,而並未包括低能隙的第一通道結構。On the other hand, the semiconductor elements of Comparative Examples 1 and 2 were similar to the semiconductor elements of Experimental Examples 1 to 13. The difference between Comparative Example 1 and Experimental Example 1-13 is that the channel structure of Comparative Example 1 is not the composite channel structure 106 shown in FIG. The channel structure of Comparative Example 1 includes only the first channel structure of the low energy gap, and does not include the second channel structure of the high energy gap. In addition, the difference between Comparative Example 2 and Comparative Example 1 is that the channel structure of Comparative Example 2 includes only the second channel structure of the high energy gap, and does not include the first channel structure of the low energy gap.

以模擬軟體Silvaco Altas TCAD對實驗例1-13以及比較例1、2的半導體元件進行模擬的結果記載於下表1。下表1的關閉電流、導通電流以及平均次臨界擺幅是在固定汲極對於源極的偏壓為0.5 V且改變閘極結構對源極的偏壓所量測到的數值。The results of simulation of the semiconductor elements of Experimental Example 1-13 and Comparative Examples 1 and 2 by the simulation software Silvaco Altas TCAD are shown in Table 1 below. The turn-off current, on-current, and average sub-threshold swing of Table 1 below are values measured at a fixed drain-to-source bias of 0.5 V and varying the bias of the gate structure to the source.

表1 Table 1

由上表1可看出實驗例1-13的關閉電流均小於比較例1、2的關閉電流。另一方面,實驗例1-13的導通電流與比較例1的導通電流的差異甚小,且實驗例1-13的導通電流大於比較例2的導通電流。由此可知,對於包括複合通道結構的半導體元件(實驗例1-13)而言,皆可有效地抑制漏電流且實質上不影響導通電流。以第一長度L1與第二長度L2的總和為150 nm的情形而言,第一長度L1與第二長度L2的比值(L1/L2)範圍可為0.07至6.5。在此情形下,由平均次臨界擺幅的數據可知,第一長度L1與第二長度L2的比值(L1/L2)範圍在0.07至4的實驗例2-13的半導體元件可具有更佳的開關特性。然而,所屬領域中具有通常知識者可依據設計需求調整第一長度L1與第二長度L2,本發明並不以第一長度L1與第二長度L2的比值範圍為限。It can be seen from the above Table 1 that the shutdown currents of Experimental Examples 1-13 are all smaller than the shutdown currents of Comparative Examples 1 and 2. On the other hand, the difference between the on-current of Experimental Example 1-13 and the on-current of Comparative Example 1 was small, and the on-current of Experimental Example 1-13 was larger than that of Comparative Example 2. From this, it is understood that the semiconductor element including the composite channel structure (Experimental Example 1-13) can effectively suppress the leakage current and does not substantially affect the on-current. In the case where the sum of the first length L1 and the second length L2 is 150 nm, the ratio (L1/L2) of the first length L1 to the second length L2 may range from 0.07 to 6.5. In this case, from the data of the average sub-threshold swing, it can be seen that the semiconductor element of the experimental example 2-13 in which the ratio (L1/L2) of the first length L1 to the second length L2 is in the range of 0.07 to 4 can be better. Switching characteristics. However, those having ordinary skill in the art can adjust the first length L1 and the second length L2 according to design requirements, and the present invention is not limited to the ratio range of the first length L1 and the second length L2.

綜上所述,基於上述,本發明實施例的半導體元件包括複合通道結構。複合通道結構包括低能隙的第一通道結構與高能隙的第二通道結構。如此一來,在半導體元件的關閉狀態時,高能隙的第二通道結構可形成能障以阻擋由源極穿遂至複合通道結構的漏電流。此外,在半導體的關閉狀態時,源極的價帶中的電子不易跨越第一通道結構所形成的位能井,故難以由源極經複合通道結構而移動至汲極。另一方面,在半導體元件的導通狀態時,高能隙的第二通道結構所形成的能障被降低,而實質上不會影響導通電流。如此一來,可在實質上不影響導通電流的情況下抑制半導體元件的漏電流。In summary, based on the above, the semiconductor device of the embodiment of the present invention includes a composite channel structure. The composite channel structure includes a first channel structure of low energy gap and a second channel structure of high energy gap. As such, in the closed state of the semiconductor component, the high-gap second channel structure can form an energy barrier to block leakage current from the source to the composite channel structure. In addition, in the off state of the semiconductor, electrons in the valence band of the source are less likely to cross the potential well formed by the first channel structure, so that it is difficult to move from the source to the drain via the composite channel structure. On the other hand, in the on state of the semiconductor element, the energy barrier formed by the second channel structure of the high energy gap is reduced without substantially affecting the on current. In this way, the leakage current of the semiconductor element can be suppressed without substantially affecting the on current.

雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100、300‧‧‧半導體元件100, 300‧‧‧ semiconductor components

102、302‧‧‧源極102, 302‧‧‧ source

104‧‧‧汲極104‧‧‧汲polar

106‧‧‧複合通道結構106‧‧‧Composite channel structure

106a‧‧‧第一通道結構106a‧‧‧First channel structure

106b‧‧‧第二通道結構106b‧‧‧Second channel structure

108‧‧‧閘極結構108‧‧‧ gate structure

108a‧‧‧第一閘極結構108a‧‧‧First gate structure

108b‧‧‧第二閘極結構108b‧‧‧Second gate structure

110a‧‧‧第一閘介電層110a‧‧‧First gate dielectric layer

110b‧‧‧第二閘介電層110b‧‧‧second gate dielectric layer

112a‧‧‧第一閘極112a‧‧‧first gate

112b‧‧‧第二閘極112b‧‧‧second gate

114‧‧‧源極接觸層114‧‧‧Source contact layer

116‧‧‧汲極接觸層116‧‧‧汲 contact layer

A、B1、B2、C‧‧‧區域A, B1, B2, C‧‧‧ areas

CB‧‧‧傳導帶CB‧‧‧Transmission belt

VB‧‧‧價帶VB‧‧ ‧ price belt

D1‧‧‧第一方向D1‧‧‧ first direction

D2‧‧‧第二方向D2‧‧‧ second direction

L1‧‧‧第一長度L1‧‧‧ first length

L2‧‧‧第二長度L2‧‧‧ second length

LC1、LC2‧‧‧漏電路徑LC1, LC2‧‧‧ leakage path

圖1是依照本發明一些實施例的半導體元件的示意圖。 圖2A是圖1的半導體元件在導通狀態的能帶圖(band diagram)。 圖2B是圖1的半導體元件在關閉狀態的能帶圖。 圖3是依照本發明另一些實施例的半導體元件的示意圖。1 is a schematic illustration of a semiconductor component in accordance with some embodiments of the present invention. 2A is a band diagram of the semiconductor device of FIG. 1 in an on state. 2B is an energy band diagram of the semiconductor device of FIG. 1 in a closed state. 3 is a schematic diagram of a semiconductor device in accordance with further embodiments of the present invention.

Claims (10)

一種半導體元件,包括: 源極,具有第一導電型; 汲極,具有第二導電型; 複合通道結構,在第一方向上位於所述源極與所述汲極之間,其中所述複合通道結構包括: 第一通道結構,位於所述源極與所述汲極之間,且具有第一能隙;以及 第二通道結構,位於所述第一通道結構與所述汲極之間,且具有第二能隙,其中所述第一能隙小於所述第二能隙;以及 閘極結構,在第二方向上鄰接於所述複合通道結構,其中所述第一方向與所述第二方向交錯。A semiconductor device comprising: a source having a first conductivity type; a drain having a second conductivity type; and a composite channel structure between the source and the drain in a first direction, wherein the composite The channel structure includes: a first channel structure between the source and the drain and having a first energy gap; and a second channel structure between the first channel structure and the drain And having a second energy gap, wherein the first energy gap is smaller than the second energy gap; and a gate structure adjacent to the composite channel structure in a second direction, wherein the first direction and the first The two directions are staggered. 如申請專利範圍第1項所述的半導體元件,其中所述第一能隙小於所述源極的能隙。The semiconductor device of claim 1, wherein the first energy gap is smaller than an energy gap of the source. 如申請專利範圍第1項所述的半導體元件,其中所述第一能隙等於所述源極的能隙。The semiconductor device of claim 1, wherein the first energy gap is equal to an energy gap of the source. 如申請專利範圍第1項所述的半導體元件,其中所述第一通道結構具有第一傳導帶與第一價帶,且所述第二通道結構具有第二傳導帶與第二價帶, 其中所述第一傳導帶低於所述第二傳導帶,且所述第一價帶低於、高於或齊平於所述第二價帶;或 其中所述第一傳導帶齊平於所述第二傳導帶,且所述第一價帶高於或低於所述第二價帶。The semiconductor device of claim 1, wherein the first channel structure has a first conduction band and a first valence band, and the second channel structure has a second conduction band and a second valence band, wherein The first conductive strip is lower than the second conductive strip, and the first valence band is lower, higher or flush with the second valence band; or wherein the first conductive strip is flush with The second conduction band is described, and the first valence band is higher or lower than the second valence band. 如申請專利範圍第1項所述的半導體元件,其中所述閘極結構包括第一閘極結構與第二閘極結構,所述第一閘極結構與所述第二閘極結構分別在所述第二方向上鄰接於所述複合通道結構的相對的兩側上。The semiconductor device of claim 1, wherein the gate structure comprises a first gate structure and a second gate structure, and the first gate structure and the second gate structure are respectively The second direction is adjacent to opposite sides of the composite channel structure. 如申請專利範圍第5項所述的半導體元件,其中所述第一閘極結構包括第一閘介電層與第一閘極,所述第一閘介電層位於所述第一閘極與所述複合通道結構之間,所述第二閘極結構包括第二閘介電層與第二閘極,所述第二閘介電層位於所述第二閘極與所述複合通道結構之間。The semiconductor device of claim 5, wherein the first gate structure comprises a first gate dielectric layer and a first gate, and the first gate dielectric layer is located at the first gate Between the composite channel structures, the second gate structure includes a second gate dielectric layer and a second gate, and the second gate dielectric layer is located in the second gate and the composite channel structure between. 如申請專利範圍第1項所述的半導體元件,更包括源極接觸層與汲極接觸層,其中所述源極接觸層連接於所述源極,且所述汲極接觸層連接於所述汲極。The semiconductor device of claim 1, further comprising a source contact layer and a drain contact layer, wherein the source contact layer is connected to the source, and the drain contact layer is connected to the Bungee jumping. 如申請專利範圍第1項所述的半導體元件,其中所述源極、所述汲極以及所述複合通道結構的材料包括IV族半導體、III-V族化合物半導體、II-VI族化合物半導體或其組合。The semiconductor device according to claim 1, wherein the source, the drain, and the material of the composite channel structure comprise a group IV semiconductor, a III-V compound semiconductor, a II-VI compound semiconductor or Its combination. 如申請專利範圍第8項所述的半導體元件,其中所述第一通道結構的材料的元素種類相異於所述第二通道結構的材料的元素種類。The semiconductor element according to claim 8, wherein the element type of the material of the first channel structure is different from the element type of the material of the second channel structure. 如申請專利範圍第8項所述的半導體元件,其中所述第一通道結構的材料與所述第二通道結構的材料包括相同的元素種類,且元素比例彼此相異。The semiconductor device according to claim 8, wherein the material of the first channel structure and the material of the second channel structure comprise the same element type, and the element ratios are different from each other.
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