CN117280475A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN117280475A
CN117280475A CN202280005114.8A CN202280005114A CN117280475A CN 117280475 A CN117280475 A CN 117280475A CN 202280005114 A CN202280005114 A CN 202280005114A CN 117280475 A CN117280475 A CN 117280475A
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contact
source
semi
drain
semiconductor device
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王学雯
吴颖
许俊豪
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor

Abstract

Embodiments of the present disclosure relate to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a source and a drain, each having a first doping type; a gate electrode located between the source electrode and the drain electrode; and a source contact and a drain contact, the source contact in contact with the source and the drain contact in contact with the drain, each of the source contact and the drain contact including a semi-metal layer and a dopant doped in the semi-metal layer, the dopant being of a second doping type opposite the first doping type.

Description

Semiconductor device and method for manufacturing the same Technical Field
Embodiments of the present disclosure relate generally to the field of semiconductor devices, and more particularly, to a semiconductor device and a method of manufacturing the same.
Background
The Dennard Scaling law (Dennard Scaling) states that as transistors become smaller in size, their power density remains unchanged. Therefore, power consumption of the device is one of the key issues that needs to be solved for device miniaturization. For example, the power consumption of a Complementary Metal Oxide Semiconductor (CMOS) device can be obtained by the formula (1.1), where P is the device power, V DD For the device operating voltage, alpha i "switch activator" for the ith circuit block in the device (switching activity factor,0<α i <1)，C i For the total effective capacitance of the ith circuit block (including all interconnections of the ith circuit block and input capacitance of transistors), f is clock frequency, I OFF Is made up of a power supply voltage V DD Off-state currents of all transistors biased. As can be seen from the formula (1.1), reducing the device operating voltage and off-state current can effectively reduce the device power consumption. Reducing the Subthreshold Slope (SS) of the device is a very efficient way to reduce the device operating voltage.
Equation (1.2) is a calculation equation of the subthreshold slope SS of the device at 300K temperature, whereCalled body factor, V G Is the gate voltage, ψ s Is of surface potential (i.e. gate voltage V G A difference from the gate oxide voltage),is a thermal voltage. As can be seen from equation (1.2), conventional MOSFET devices are subject to thermal dissociationThe subthreshold limit, SS, cannot be below 60mV/dec. Thus, in order to maintain a high target current I ON And a larger switching ratio I ON /I OFF Device operating voltage V DD Relatively large, resulting in higher device power consumption. At present, at the technical node of the CMOS integrated circuit with the wavelength of 7nm and 5nm, the working voltage V of the device DD Has been reduced to 0.7V. However, since MOSFET devices are limited by the thermal ion limit, the operating voltage V of the integrated circuit DD The minimum is 0.64V, and the power consumption of the device cannot be effectively reduced at the next technology node (3 nm/2 nm).
In the low-power-consumption logic device, the device with the subthreshold slope SS less than 60mV/dec can effectively reduce the working voltage V of the device DD Thereby reducing the power consumption of the device. However, devices capable of subthreshold slope SS < 60mV/dec, such as Tunneling Field-effect Transistor (TFET), tend to operate at currents more than 2 orders of magnitude less than the target current. Therefore, these low power logic devices also need to maintain a sufficiently high operating current if desired for future low power high performance chips.
One conventional approach exploits the characteristic that the half-metal band gap is zero and the electron state density near the fermi surface is close to zero, suggesting that the pinning effect between metal and semiconductor can be effectively reduced with a half-metal of a particular fermi level, thereby reducing the contact resistance between metal and semiconductor, making its subthreshold slope SS approach 60mV/dec. However, the mere semi-metal contact still cannot break through the thermionic limit, so the subthreshold slope SS rate can only approach 60mV/dec indefinitely, but cannot be less than 60mV/dec.
Disclosure of Invention
Embodiments of the present disclosure provide a semiconductor device and a method of manufacturing the same, which aim to solve the above-mentioned problems and other potential problems of conventional semiconductor devices.
Embodiments of the present disclosure provide a low power transistor device (including NMOS and PMOS transistors) compatible with existing CMOS processes with doped semi-metal materials as source-drain contacts and a process for fabricating the same, which may be integrated in existing planar transistors, fin field effect transistors (finfets), gate-all-around field effect transistors (GAA FETs), and Vertical nanowire field effect transistor (Vertical NWFET) structures, thereby enabling devices such as CMOS inverters and logic circuits based on the same.
According to a first aspect of the present disclosure, there is provided a semiconductor device comprising: a source electrode and a drain electrode respectively having a first doping type; a gate electrode located between the source electrode and the drain electrode; and a source contact and a drain contact, the source contact in contact with the source and the drain contact in contact with the drain, each of the source contact and the drain contact including a semi-metal layer and a dopant doped in the semi-metal layer, the dopant being of a second doping type opposite the first doping type.
In some embodiments, the semi-metallic layer comprises a two-dimensional semi-metallic material.
In some embodiments, the two-dimensional semi-metallic material comprises at least one of: graphene and two-dimensional transition metal chalcogenides.
In some embodiments, the two-dimensional transition metal chalcogenide includes at least one of: WTE (WTE) 2 ；MoTe 2 ；W 2 XY, wherein X and Y are each one of sulfur (S), selenium (Se), and tellurium (Te), and X is different from Y; mo and Mo 2 XY, wherein X and Y are each one of sulfur (S), selenium (Se), and tellurium (Te), and X is different from Y.
In some embodiments, the dopant comprises nitrogen (N) if the first doping type is p-type and the second doping type is N-type, and comprises boron (B) if the first doping type is N-type and the second doping type is p-type.
In some embodiments, the semi-metallic layer comprises a three-dimensional semi-metallic material.
In some embodiments, the three-dimensional semi-metallic material comprises at least one of: tin (Sn), bismuth (Bi), antimony (Sb), tellurium (Te), arsenic (As), and germanium (Ge), and compounds containing the above elements.
In some embodiments, the three-dimensional semi-metallic material comprises at least one of: spinel structure, perovskite structure, rutile structure, and semi-heusler and heusler structures.
In some embodiments, the spinel structure includes Fe 3 O 4 And CuV 2 S 4 At least one of (a) and (b); the perovskite structure comprises La 0.7 Sr 0.3 MnO 3 The method comprises the steps of carrying out a first treatment on the surface of the The rutile structure comprises CrO 2 And CoS 2 At least one of (a) and (b); and the half-heusler and heusler structures include at least one of NiMnSb and PbMnSb.
In some embodiments, the dopant comprises tin (Sn) if the first doping type is n-type and the second doping type is p-type, and tellurium (Te) if the first doping type is p-type and the second doping type is n-type.
In some embodiments, the field effect transistor is a planar field effect transistor, a fin field effect transistor, a gate-all-around field effect transistor, or a vertical structure nanowire field effect transistor.
In some embodiments, a distance between each of the source contact and the drain contact and the gate is below 10 nm.
In some embodiments, each of the source and drain electrodes comprises a semi-metallic material modulated to a semiconductor type.
According to a second aspect of the present disclosure, there is provided a method for manufacturing a semiconductor device, comprising: providing a source and a drain, the source and the drain each having a first doping type; providing a gate electrode, the gate electrode being located between the source electrode and the drain electrode; and providing a source contact and a drain contact, the source contact in contact with the source and the drain contact in contact with the drain, each of the source contact and the drain contact including a semi-metal layer and a dopant doped in the semi-metal layer, the dopant being of a second doping type opposite the first doping type.
According to a third aspect of the present disclosure, there is provided a semiconductor device comprising: a source electrode and a drain electrode respectively having a first doping type; a gate electrode located between the source electrode and the drain electrode; and a source contact and a drain contact, the source contact being in contact with the source and the drain contact being in contact with the drain, each of the source contact and the drain contact comprising a semi-metal layer and a stress layer in contact with the semi-metal layer, the stress layer comprising a metallic material having a different coefficient of thermal expansion or a different lattice parameter than the semi-metal layer.
In some embodiments, the semi-metallic layer comprises a two-dimensional semi-metallic material or a three-dimensional semi-metallic material.
In some embodiments, the stress layer is located over and/or laterally surrounds the semi-metal layer.
In some embodiments, the stress layer comprises a single layer or a stack of layers.
In some embodiments, the semi-metal layer comprises a doped semi-metal material or an undoped semi-metal material.
In some embodiments, a distance between each of the source contact and the drain contact and the gate is below 10 nm.
In some embodiments, each of the source and drain electrodes comprises a semi-metallic material modulated to a semiconductor type.
According to a fourth aspect of the present disclosure, there is provided a method for manufacturing a semiconductor device, comprising: providing a source and a drain, the source and the drain each having a first doping type; providing a gate electrode, the gate electrode being located between the source electrode and the drain electrode; and providing a source contact and a drain contact, the source contact being in contact with the source, the drain contact being in contact with the drain, each of the source contact and the drain contact comprising a semi-metal layer and a stress layer in contact with the semi-metal layer, the stress layer comprising a metallic material having a different coefficient of thermal expansion or a different lattice parameter than the semi-metal layer.
The structure of the semiconductor device of the embodiment of the disclosure is similar to that of a traditional MOSFET device, and the manufacturing process is simpler and compatible with the traditional CMOS process.
The semiconductor device of the embodiment of the disclosure is in an off state Shi Yuan drain due to the existence of a Schottky barrier and a pinning effect and the reduction of carrier concentration caused by the movement of a semi-metal fermi surface, so that the off-state current of the device is smaller than that of a traditional MOSFET device, and meanwhile, the subthreshold slope SS is smaller than 60mV/dec. In addition, when the semiconductor device of the embodiment of the disclosure works, the source-drain Schottky barrier is reduced until disappearing, the pinning effect is gradually weakened until disappearing, and the improvement of carrier concentration caused by the movement of the semi-metal fermi surface enables the device to work at a lower working voltage V DD A larger target current can be obtained while the subthreshold slope SS is less than 60mV/dec. Therefore, the device structure and the technical scheme provided by the embodiment of the disclosure can be applied to the preparation of the semiconductor device with low power consumption and high performance.
The summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the disclosure, nor is it intended to be used to limit the scope of the disclosure.
Drawings
The above, as well as additional purposes, features, and advantages of embodiments of the present disclosure will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown by way of example, and not by way of limitation.
Fig. 1 shows a schematic cross-sectional view of a semiconductor device according to one embodiment of the present disclosure.
Fig. 2 shows the fermi-plane distribution of a p-type doped semi-metallic material.
Fig. 3 shows a schematic diagram of carrier distribution of an n-channel device employing a p-doped semi-metallic material as source-drain contact when the operating voltage is positive.
Fig. 4 shows a schematic carrier distribution diagram of an n-channel device employing a p-doped semi-metallic material as source-drain contact when the operating voltage is negative.
Fig. 5 shows a schematic cross-sectional view of a semiconductor device according to one embodiment of the present disclosure.
Fig. 6 shows the fermi-side distribution of an n-type doped semi-metallic material.
Fig. 7 shows a schematic diagram of carrier distribution of a p-channel device employing an n-doped semi-metallic material as a source-drain contact when the operating voltage is positive.
Fig. 8 shows a schematic diagram of carrier distribution of a p-channel device employing an n-doped semi-metallic material as source-drain contact when the operating voltage is negative.
Fig. 9 shows a schematic cross-sectional view of a semiconductor device according to one embodiment of the present disclosure.
Fig. 10 shows a schematic cross-sectional view of a semiconductor device according to one embodiment of the present disclosure.
Fig. 11 shows a schematic cross-sectional view of a semiconductor device according to one embodiment of the present disclosure.
Fig. 12 shows a schematic cross-sectional view of a semiconductor device according to one embodiment of the present disclosure.
Fig. 13 illustrates a perspective view of a semiconductor device according to one embodiment of the present disclosure.
Fig. 14 shows a perspective view of a semiconductor device according to one embodiment of the present disclosure.
Fig. 15 illustrates a perspective view of a semiconductor device according to one embodiment of the present disclosure.
Like or corresponding reference characters indicate like or corresponding parts throughout the several views.
Detailed Description
Preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present disclosure are illustrated in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The term "comprising" and variations thereof as used herein means open ended, i.e., "including but not limited to. The term "or" means "and/or" unless specifically stated otherwise. The term "based on" means "based at least in part on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment. The term "another embodiment" means "at least one additional embodiment". The terms "upper," "lower," "front," "rear," and the like, as used herein, refer to a place or position relationship based on the orientation or position relationship shown in the drawings, and are merely for convenience in describing the principles of the present disclosure, and do not refer to or imply that the elements referred to must have a particular orientation, be configured or operated in a particular orientation, and thus should not be construed as limiting the present disclosure.
Embodiments of the present disclosure provide a semiconductor device and a method of manufacturing the same to solve the above-mentioned problems and other potential problems of conventional semiconductor devices. The principles of the present disclosure will be described in detail below with reference to the drawings in connection with exemplary embodiments.
Fig. 1 shows a schematic cross-sectional view of a semiconductor device 100 according to one embodiment of the present disclosure. As shown in fig. 1, the semiconductor device 100 includes a substrate 10, a source 20, a drain 30, a source contact 21, a drain contact 31, and a gate 40. The source electrode 20 and the drain electrode 30 are formed at the top surface of the substrate 10. The source contact 21 is in contact with the source 20 for making an electrical connection. The drain contact 31 is in contact with the drain 30 for making an electrical connection. A gate 40 is formed on the top surface of the substrate 10 via a gate dielectric 41. In operation of semiconductor device 100, inA channel 11 connecting the source 20 and the drain 30 may be formed in the substrate 10. Taking the n-channel semiconductor device 100 as an example, the substrate 10 of the semiconductor device 100 has p-type doping, and the source 20 and drain 30 thereof are heavily doped n-type regions. The source contact 21 and the drain contact 31 of the semiconductor device 100 employ a p-type doped semi-metal material (p-SM). The p-doped semi-metallic material means its fermi-plane E F Modulated to the Valence Band (VB) as shown in fig. 2. When a positive voltage is applied to the gate 40, an inversion layer is created in the p-type substrate 10, thereby forming a channel 11, and electrons will be injected into the n-type source and drain electrodes 20, 30 and the corresponding source and drain contacts 21, 31. Thus, fermi plane E of p-SM F Moving upward, gradually from the Valence Band (VB) toward the Conduction Band (CB), at which time the contact resistance between the source and drain contacts 21, 31 and the n-type source and drain electrodes 20, 30 decreases, while the hole concentration of the source electrode 20 decreases, and the electron (carrier) concentration increases, so that the current rapidly increases, as shown in fig. 3. Thus, the semiconductor device 100 can achieve a larger operating current than a conventional nFET, while the subthreshold slope SS is reduced to below 60mV/dec. And when a negative voltage is applied to the gate 40, hole accumulation is generated in the p-type substrate 10, and holes are injected into the n-type source and drain electrodes 20, 30 and the corresponding source and drain contacts 21, 31. Thus, fermi plane E of p-SM F Further downward in the Valence Band (VB), at this time, the contact resistance between the source-drain contacts 21, 31 and the n-type source-drain electrodes 20, 30 increases, while the hole concentration of the source electrode 20 increases, and the electron (carrier) concentration decreases, so that the current rapidly decreases, as shown in fig. 4. Thus, semiconductor device 100 can achieve lower off-state currents than conventional nFETs, while subthreshold slope SS is less than 60mV/dec. In general, since the subthreshold slope SS of the semiconductor device 100 is less than 60mV/dec, the same switching ratio (I ON /I OFF ) Operating voltage V of semiconductor device 100 DD Lower. And the off-state current of the semiconductor device 100 is lower due to the presence of the larger contact resistance. Accordingly, the semiconductor device 100 realizes the low power consumption property in cooperation from the two aspects of lowering the operating voltage and reducing the off-state current.
FIG. 5 illustrates an embodiment in accordance with the present disclosureA schematic cross-sectional view of a semiconductor device 200. The semiconductor device 200 shown in fig. 5 is similar in structure to the semiconductor device 100 shown in fig. 1, except that the semiconductor device 200 shown in fig. 5 is a p-channel device and the semiconductor device 100 shown in fig. 1 is an n-channel device. Specifically, the substrate 10 of the semiconductor device 200 has n-type doping, and the source 20 and drain 30 thereof are heavily doped p-type regions. The source contact 21 and the drain contact 31 of the semiconductor device 200 employ an n-type doped semi-metallic material (n-SM). The n-doped semi-metallic material means its fermi-plane E F Modulated to the Conduction Band (CB) as shown in fig. 6. When a positive voltage is applied to the gate 40, charge accumulation occurs in the n-type substrate 10 and electrons are injected into the p-type source and drain electrodes 20, 30 and the corresponding source and drain contacts 21, 31. Whereby the fermi plane E of n-SM F Further up in the Conduction Band (CB) when the contact resistance between the source and drain contacts 21, 31 and the p-type source and drain 20, 30 increases, while the hole (carrier) concentration of the source 20 decreases, so that the current rapidly decreases, as shown in fig. 7. Thus, the semiconductor device 200 can achieve a lower off-state current than a normal pFET, while the subthreshold slope SS is less than 60mV/dec. And when a negative voltage is applied to the gate 40, an inversion layer is created in the n-type substrate 10 to form a channel 11, holes are injected into the p-type source and drain electrodes 20, 30 and corresponding source and drain contacts 21, 31 to form the fermi-side E of the n-SM F Moving down, the contact resistance between the source-drain contacts 21, 31 and the p-type source-drain electrodes 20, 30 decreases, and the hole (carrier) concentration increases, so that the current increases rapidly, as shown in fig. 8. Thus, the semiconductor device 200 can achieve a larger operating current than a conventional pFET, while the subthreshold slope SS is reduced to below 60mV/dec. In general, since the subthreshold slope SS of the semiconductor device 200 is less than 60mV/dec, the same switching ratio (I ON /I OFF ) Operating voltage V of semiconductor device 200 DD Lower. And the off-state current of the semiconductor device 200 is lower due to the presence of the larger contact resistance. Accordingly, the semiconductor device 200 also realizes the low power consumption property in cooperation from the two aspects of lowering the operating voltage and reducing the off-state current.
The semiconductor device according to the embodiments of the present disclosure may be of various types, such as a planar field effect transistor, a fin field effect transistor, a gate-all-around field effect transistor, or a vertical structure nanowire field effect transistor. An exemplary structure of the semiconductor device will be described hereinafter with reference to fig. 9 to 15.
Fig. 9 shows a schematic cross-sectional view of a semiconductor device 300 according to one embodiment of the present disclosure. The semiconductor device 300 is an n-type planar field effect transistor. As shown in fig. 9, the semiconductor device 300 includes a substrate 10, a source 20, a drain 30, a source contact 21, a drain contact 31, and a gate 40. The source electrode 20 and the drain electrode 30 are formed at the top surface of the substrate 10. The source contact 21 is in contact with the source 20 for making an electrical connection. The drain contact 31 is in contact with the drain 30 for making an electrical connection. A gate 40 is formed on the top surface of the substrate 10 via a gate dielectric 41. The substrate 10 of the semiconductor device 300 has p-type doping and its source 20 and drain 30 are heavily doped n-type regions. By way of example, the heavily doped n-type region may be silicon phosphorus Si P (Silicon Phosphorus), where Si P represents the doping of phosphorus (P) into silicon (Si), achieving n-type doping. The source contact 21 and the drain contact 31 of the semiconductor device 300 employ a p-type doped semi-metallic material (p-SM) including a semi-metallic layer and a dopant doped in the semi-metallic layer. By way of example, the p-doped semi-metallic material may be Bi Sn (Bismuch Stannum), where Bi: sn represents the incorporation of tin (Sn) within bismuth (Bi), i.e., bismuth (Bi) forms a semi-metallic layer, with tin (Sn) being doped as a dopant in bismuth (Bi), thereby achieving p-doping. In some examples, semiconductor device 300 further includes a gate sidewall 42 that covers gate 42. In some examples, semiconductor device 300 further includes an insulating medium 43, insulating medium 43 for isolating source and drain contacts 21, 31 from gate 40.
Fig. 10 shows a schematic cross-sectional view of a semiconductor device 400 according to one embodiment of the present disclosure. The semiconductor device 400 is a p-type planar field effect transistor. As shown in fig. 10, the semiconductor device 400 includes a substrate 10, a source 20, a drain 30, a source contact 21, a drain contact 31, and a gate 40. The source electrode 20 and the drain electrode 30 are formed at the top surface of the substrate 10. The source contact 21 is in contact with the source 20 for making an electrical connection. The drain contact 31 is in contact with the drain 30 for making an electrical connection. A gate 40 is formed on the top surface of the substrate 10 via a gate dielectric 41. The substrate 10 of the semiconductor device 400 has n-type doping and its source 20 and drain 30 are heavily doped p-type regions. By way of example, the heavily doped p-type region may be silicon germanium Si Ge (Silicon Germanium), where Si-Ge represents the incorporation of germanium (Ge) into silicon (Si), to effect p-type doping. The source contact 21 and the drain contact 31 of the semiconductor device 400 employ an n-type doped semi-metallic material (n-SM) including a semi-metallic layer and a dopant doped in the semi-metallic layer. By way of example, the n-doped semi-metallic material may be Bi Te (Bismuch Tellurium), where Bi Te represents the incorporation of tellurium (Te) within bismuth (Bi), i.e., bismuth (Bi) forms a semi-metallic layer, with tellurium (Te) being doped as a dopant in bismuth (Bi), thereby achieving n-doping. In some examples, semiconductor device 400 further includes a gate sidewall 42 that covers gate 42. In some examples, semiconductor device 400 further includes an insulating medium 43, insulating medium 43 for isolating source and drain contacts 21, 31 from gate 40.
For the selection of the semi-metallic material, two-dimensional semi-metallic material and three-dimensional semi-metallic material can be used. It is also possible to develop one-dimensional semi-metallic materials and zero-dimensional semi-metallic materials in the future, which can also be used as semi-metallic layers in the source and drain contacts 21, 31. Two-dimensional semi-metallic materials include, but are not limited to, graphene (graphene), two-dimensional transition metal chalcogenides, and the like. The two-dimensional transition metal chalcogenide may be, for example, WTE 2 ，MoTe 2 ，W 2 XY (X, y=s, se, te, x+.y) and Mo 2 One or more of XY (X, y=s, se, te, x+.y). In some embodiments, the three-dimensional semi-metallic material may be a semi-metallic element of the periodic table of elements, as well As portions of metalloid elements, including, but not limited to, tin (Sn), bismuth (Bi), antimony (Sb), tellurium (Te), arsenic (As), and germanium (Ge), as well As compounds containing these elements. The compounds of the above elements include, but are not limited to, taAs, zrTe 5 ，Na 3 Bi，Cd 3 As 2 And GdPtBi. In some embodimentsThe three-dimensional semi-metallic material may be other compounds having semi-metallic properties including, but not limited to, spinel structures (exemplary, fe 3 O 4 ，CuV 2 S 4 ) Perovskite structure (exemplary, la 0.7 Sr 0.3 MnO 3 ) Rutile structure (exemplary, crO 2 ,CoS 2 ) And Half-Heusler (Half-Heusler) and Heusler (Heusler) structures (exemplary, niMnSb, pbMnSb).
The harvesting of the doped semi-metallic material may be achieved by elemental doping in the semi-metallic layer to adjust the fermi level of the semi-metallic material. For two-dimensional semi-metallic materials, such as graphene, for example, graphene can be made N-type by nitrogen (N) doping and p-type by boron (B) doping. For three-dimensional semi-metallic materials such as bismuth (Bi), for example tin (Sn) doped can be effectively p-doped and tellurium (Te) doped can be effectively n-doped. The fermi surface of the semi-metallic material can be effectively adjusted by element doping.
In some embodiments, the distance between the source and drain contacts 21, 31 and the gate 40 is as narrow as possible to reduce the average of carrier changes due to thermal disturbances. For example, the distance between the source and drain contacts 21, 31 and the gate 40 may be below 10 nm. In addition, in order to reduce the influence caused by thermal disturbance, a semi-metal material with energy band modulated into a semiconductor type can be used as the source and drain electrodes 20 and 30 in contact with the source and drain contacts 21 and 31, and the modulation method can be realized by adopting element doping or stress regulation and control, and can also be realized by controlling the thickness or shape of the semi-metal material. Exemplary, for the semi-metallic material Bi 1-x Sb x The transition from semi-metal to semiconductor can be initiated by varying the Sb content; for the semi-metallic material Bi 8 Te 7 S 5 The semi-metal to semiconductor transition can be initiated by controlling the thickness of the material.
In some embodiments, a method for fabricating semiconductor devices 300 and 400 is also provided. The method comprises the following steps: providing a source 20 and a drain 30, the source 20 and the drain 30 having a first doping type, respectively; providing a gate 40, which is located between the source 20 and the drain 30; and providing a source contact 21 and a drain contact 31, the source contact 21 being in contact with the source 20, the drain contact 31 being in contact with the drain 30, each of the source contact 21 and the drain contact 31 comprising a semi-metal layer and a dopant doped in the semi-metal layer, the dopant being of a second doping type opposite to the first doping type. In the case where the first doping type is n-type, the second doping type is p-type. And in the case where the first doping type is p-type, the second doping type is n-type. The contents described above in connection with fig. 9 and 10 may be incorporated into the method for manufacturing the semiconductor devices 300 and 400, and will not be described again here.
Fig. 11 shows a schematic cross-sectional view of a semiconductor device 500 according to one embodiment of the present disclosure. The semiconductor device 500 is an n-type or p-type planar field effect transistor. As shown in fig. 11, the semiconductor device 500 includes a substrate 10, a source 20, a drain 30, a source contact 21, a drain contact 31, and a gate 40. The source electrode 20 and the drain electrode 30 are formed at the top surface of the substrate 10. The source contact 21 is in contact with the source 20 for making an electrical connection. The drain contact 31 is in contact with the drain 30 for making an electrical connection. A gate 40 is formed on the top surface of the substrate 10 via a gate dielectric 41. In some examples, semiconductor device 500 further includes a gate sidewall 42 that covers gate 42. In some examples, semiconductor device 500 further includes an insulating medium 43, insulating medium 43 for isolating source and drain contacts 21, 31 from gate 40. In the case where semiconductor device 500 is an nFET, substrate 10 of semiconductor device 500 has p-type doping and source 20 and drain 30 thereof are heavily doped n-type regions. By way of example, the heavily doped n-type region may be silicon phosphorus Si P (Silicon Phosphorus), where Si P represents the doping of phosphorus (P) into silicon (Si), achieving n-type doping. In the case where the semiconductor device 500 is a pFET, the substrate 10 of the semiconductor device 500 has n-type doping and the source 20 and drain 30 thereof are heavily doped p-type regions. By way of example, the heavily doped p-type region may be silicon germanium Si Ge (Silicon Germanium), where Si-Ge represents the incorporation of germanium (Ge) into silicon (Si), to effect p-type doping.
Source contact21 includes a semi-metal layer 211 and a stress layer 212. The drain contact 31 includes a semi-metal layer 311 and a stress layer 312. The half metal layers 211 and 311 may be doped half metal layers or undoped half metal layers. The semi-metallic material in the semi-metallic layers 211 and 311 may be a two-dimensional semi-metallic material or a three-dimensional semi-metallic material. Stress layers 212 and 312 may stress-regulate semi-metal layers 211 and 311, respectively. For two-dimensional semi-metallic materials, moTe can be regulated and controlled by stress 2 Electron concentration of (2). For three-dimensional semi-metal materials such as TaAs, stress layers 212 and 312 may be stress tuned to semi-metal layers 211 and 311, respectively, to adjust their band gap to change their Weyl point (Weyl point) and thereby affect their charge transport properties. In addition, the stress regulation can also change the shape of the energy band. The subthreshold slope SS of the device can be reduced more effectively as the band curvature becomes sharper. Therefore, stress control is also a means to effectively adjust the fermi surface of the semi-metallic material. The stress layers 212 and 312 may be a metal material having a different thermal expansion coefficient from the half metal layers 211 and 311 or a metal material having a different lattice parameter. As shown in fig. 11, stress layer 212 is located over semi-metal layer 211 and stress layer 312 is located over semi-metal layer 311. With this arrangement, stress layers 212 and 312 provide primarily out-of-plane (out-of-plane) stress.
In some embodiments, the distance between the source and drain contacts 21, 31 and the gate 40 is as narrow as possible to reduce the average of carrier changes due to thermal disturbances. For example, the distance between the source and drain contacts 21, 31 and the gate 40 may be below 10 nm. In addition, in order to reduce the influence caused by thermal disturbance, a semi-metal material with energy band modulated into a semiconductor type can be used as the source and drain electrodes 20 and 30 in contact with the source and drain contacts 21 and 31, and the modulation method can be realized by adopting element doping or stress regulation and control, and can also be realized by controlling the thickness or shape of the semi-metal material. Exemplary, for the semi-metallic material Bi 1-x Sb x The transition from semi-metal to semiconductor can be initiated by varying the Sb content; for the semi-metallic material Bi 8 Te 7 S 5 Semi-metal to semiconductor can be initiated by controlling the thickness of the materialTransformation of body.
Fig. 12 shows a schematic cross-sectional view of a semiconductor device 600 according to one embodiment of the present disclosure. The semiconductor device 600 is an n-type or p-type planar field effect transistor. As shown in fig. 12, the semiconductor device 600 includes a substrate 10, a source 20, a drain 30, a source contact 21, a drain contact 31, and a gate 40. The source electrode 20 and the drain electrode 30 are formed at the top surface of the substrate 10. The source contact 21 is in contact with the source 20 for making an electrical connection. The drain contact 31 is in contact with the drain 30 for making an electrical connection. A gate 40 is formed on the top surface of the substrate 10 via a gate dielectric 41. In some examples, semiconductor device 500 further includes a gate sidewall 42 that covers gate 42. In some examples, semiconductor device 500 further includes an insulating medium 43, insulating medium 43 for isolating source and drain contacts 21, 31 from gate 40. In the case where the semiconductor device 600 is an nFET, the substrate 10 of the semiconductor device 600 has p-type doping and the source 20 and drain 30 thereof are heavily doped n-type regions. By way of example, the heavily doped n-type region may be silicon phosphorus Si P (Silicon Phosphorus), where Si P represents the doping of phosphorus (P) into silicon (Si), achieving n-type doping. In the case where the semiconductor device 600 is a pFET, the substrate 10 of the semiconductor device 600 has n-type doping and the source 20 and drain 30 thereof are heavily doped p-type regions. By way of example, the heavily doped p-type region may be silicon germanium Si Ge (Silicon Germanium), where Si-Ge represents the incorporation of germanium (Ge) into silicon (Si), to effect p-type doping.
The source contact 21 includes a semi-metal layer 211 and a stress layer 212. The drain contact 31 includes a semi-metal layer 311 and a stress layer 312. The half metal layers 211 and 311 may be doped half metal layers or undoped half metal layers. The semi-metallic material in the semi-metallic layers 211 and 311 may be a two-dimensional semi-metallic material or a three-dimensional semi-metallic material. Stress layers 212 and 312 may stress-regulate semi-metal layers 211 and 311, respectively. For two-dimensional semi-metallic materials, moTe can be regulated and controlled by stress 2 Electron concentration of (2). While for three-dimensional semi-metallic materials such as TaAs, stress layers 212 and 312 may stress-tune semi-metallic layers 211 and 311, respectively, to adjust their band gap to change their Weyl point (Weyl point) to affect their chargeTransport properties. In addition, the stress regulation can also change the shape of the energy band. The subthreshold slope SS of the device can be reduced more effectively as the band curvature becomes sharper. Therefore, stress control is also a means to effectively adjust the fermi surface of the semi-metallic material. The stress layers 212 and 312 may be a metal material having a different thermal expansion coefficient from the half metal layers 211 and 311 or a metal material having a different lattice parameter. As shown in fig. 12, stress layer 212 laterally surrounds semi-metal layer 211 and stress layer 312 laterally surrounds semi-metal layer 311. With this arrangement, stress layers 212 and 312 provide primarily in-plane (in-plane) stress.
In some embodiments, the distance between the source and drain contacts 21, 31 and the gate 40 is as narrow as possible to reduce the average of carrier changes due to thermal disturbances. For example, the distance between the source and drain contacts 21, 31 and the gate 40 may be below 10 nm. In addition, in order to reduce the influence caused by thermal disturbance, a semi-metal material with energy band modulated into a semiconductor type can be used as the source and drain electrodes 20 and 30 in contact with the source and drain contacts 21 and 31, and the modulation method can be realized by adopting element doping or stress regulation and control, and can also be realized by controlling the thickness or shape of the semi-metal material. Exemplary, for the semi-metallic material Bi 1-x Sb x The transition from semi-metal to semiconductor can be initiated by varying the Sb content; for the semi-metallic material Bi 8 Te 7 S 5 The semi-metal to semiconductor transition can be initiated by controlling the thickness of the material.
In some embodiments, the stressing schemes shown in fig. 11 and 12 may be combined if omnidirectional stress is to be provided, or other dual or more stressing layer stack schemes may be employed.
In some embodiments, a method for fabricating semiconductor devices 500 and 600 is also provided. The method comprises the following steps: providing a source 20 and a drain 30, the source 20 and the drain 30 having a first doping type, respectively; providing a gate 40, which is located between the source 20 and the drain 30; and providing a source contact 21 and a drain contact 31, the source contact 21 being in contact with the source 20, the drain contact 31 being in contact with the drain 30, each of the source contact 21 and the drain contact 31 comprising a semi-metal layer 211, 311 and a stress layer 212, 312 in contact with the semi-metal layer 211, 311, the stress layer 212, 312 comprising a metallic material having a different coefficient of thermal expansion or a different lattice parameter than the semi-metal layer. In the case where the first doping type is n-type, the second doping type is p-type. And in the case where the first doping type is p-type, the second doping type is n-type. The contents described above in connection with fig. 11 and 12 may be incorporated into the method for manufacturing the semiconductor devices 500 and 600, and will not be described again here.
In addition, the source electrode 20 and the drain electrode 30 of the planar field effect transistor shown in fig. 9 to 12 can both retain the epitaxial process, and still can provide enough stress for the channel of the device, so that the device can realize larger working current through the stress technology. Epitaxial growth refers to the growth of a single crystal layer with certain requirements and the same crystal orientation as the substrate on a single crystal substrate (substrate) as if the original crystal had been grown by extension.
Fig. 13 illustrates a perspective view of a semiconductor device 700 according to one embodiment of the present disclosure. As shown in fig. 13, the semiconductor device 700 is a fin field effect transistor. The semiconductor device 700 includes a substrate 10; a fin 23 formed on the substrate 10, one end of the fin 23 forming a source 20, the other end of the fin 23 forming a drain 30; a gate 40 surrounding a middle portion of the fin 23 between the source 20 and the drain 30 via a gate dielectric 41; and a source contact 21 and a drain contact 31, the source contact 21 at least partially surrounding the source 20, and the drain contact 31 at least partially surrounding the drain 30. The source contact 21 and the drain contact 31 shown in fig. 13 may have a similar structure to the source contact 21 and the drain contact 31 described above in connection with fig. 9 to 12, and will not be described again here. In some embodiments, the semiconductor device 700 further includes an isolation medium 50 formed on the top surface of the substrate 10 around the fin 23.
Fig. 14 illustrates a perspective view of a semiconductor device 800 according to one embodiment of the present disclosure. As shown in fig. 14, the semiconductor device 800 is a gate-all-around field effect transistor. The semiconductor device 800 includes a substrate 10; a source contact 21 and a drain contact 31 provided on the substrate 10 at intervals; a plurality of source electrodes 20 in contact with the source contacts 21; a plurality of drains 30 in contact with the drain contacts 31; a plurality of channels 11 formed between the source electrode 20 and the drain electrode 30; and a gate 40 surrounding each channel 11 via a gate dielectric 41. The source contact 21 and the drain contact 31 shown in fig. 14 may have a similar structure to the source contact 21 and the drain contact 31 described above in connection with fig. 9 to 12, and will not be described again here. In some embodiments, semiconductor device 800 further includes an isolation medium 50 formed around substrate 10.
Fig. 15 illustrates a perspective view of a semiconductor device 900 according to one embodiment of the present disclosure. As shown in fig. 15, the semiconductor device 900 is a vertical structure nanowire field effect transistor. The semiconductor device 900 includes: a nanowire, one end of which forms a source electrode 20, the other end of which forms a drain electrode 30, and the middle of which forms a channel 11; a gate 40 surrounding the channel 11 via a gate dielectric 41; and a source contact and a drain contact (not shown), the source contact being in contact with the source 20 for electrical connection, the drain contact being in contact with the drain for electrical connection. The source and drain contacts of the semiconductor device 900 may have similar structures to the source and drain contacts 21 and 31 described above in connection with fig. 9 to 12, and will not be described again here.
While the principles of the present disclosure are described above in connection with planar field effect transistors, fin field effect transistors, ring gate field effect transistors, or vertical structure nanowire field effect transistors, it should be understood that in other embodiments, the described structures of source and drain contacts may be incorporated into other types of transistors.
The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the technical improvements in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (22)

  1. A semiconductor device, comprising:
    a source electrode and a drain electrode respectively having a first doping type;
    a gate electrode located between the source electrode and the drain electrode; and
    a source contact and a drain contact, the source contact in contact with the source and the drain contact in contact with the drain, each of the source contact and the drain contact including a semi-metal layer and a dopant doped in the semi-metal layer, the dopant being of a second doping type opposite the first doping type.
  2. The semiconductor device of claim 1, wherein the semi-metal layer comprises a two-dimensional semi-metal material.
  3. The semiconductor device of claim 2, wherein the two-dimensional semi-metallic material comprises at least one of: graphene and two-dimensional transition metal chalcogenides.
  4. The semiconductor device of claim 3, wherein the two-dimensional transition metal chalcogenide comprises at least one of:
    WTe 2 ；
    MoTe 2 ；
    W 2 XY, wherein X and Y are each one of sulfur (S), selenium (Se), and tellurium (Te), and X is different from Y; and
    Mo 2 XY, wherein X and Y are each one of sulfur (S), selenium (Se), and tellurium (Te), and X is different from Y.
  5. The semiconductor device according to claim 2, wherein in the case where the first doping type is p-type and the second doping type is N-type, the dopant includes nitrogen (N), and
    in the case where the first doping type is n-type and the second doping type is p-type, the dopant includes boron (B).
  6. The semiconductor device of claim 1, wherein the semi-metal layer comprises a three-dimensional semi-metal material.
  7. The semiconductor device of claim 6, wherein the three-dimensional semi-metallic material comprises at least one of: tin (Sn), bismuth (Bi), antimony (Sb), tellurium (Te), arsenic (As), and germanium (Ge), and compounds containing the above elements.
  8. The semiconductor device of claim 6, wherein the three-dimensional semi-metallic material comprises at least one of: spinel structure, perovskite structure, rutile structure, and semi-heusler and heusler structures.
  9. The semiconductor device according to claim 8, wherein,
    the spinel structure includes Fe 3 O 4 And CuV 2 S 4 At least one of (a) and (b);
    the perovskite structure comprises La 0.7 Sr 0.3 MnO 3 ；
    The rutile structure comprises CrO 2 And CoS 2 At least one of (a) and (b); and
    the half-heusler and heusler structures include at least one of NiMnSb and PbMnSb.
  10. The semiconductor device according to claim 6, wherein in the case where the first doping type is n-type and the second doping type is p-type, the dopant includes tin (Sn), and
    in the case where the first doping type is p-type and the second doping type is n-type, the dopant includes tellurium (Te).
  11. The field effect transistor of claim 1, wherein the field effect transistor is a planar field effect transistor, a fin field effect transistor, a ring gate field effect transistor, or a vertical structure nanowire field effect transistor.
  12. The semiconductor device of claim 1, wherein a distance between each of the source contact and the drain contact and the gate is 10nm or less.
  13. The semiconductor device according to claim 1, wherein each of the source electrode and the drain electrode comprises a semi-metallic material modulated into a semiconductor type.
  14. A method for manufacturing a semiconductor device, comprising:
    providing a source and a drain, the source and the drain each having a first doping type;
    providing a gate electrode, the gate electrode being located between the source electrode and the drain electrode; and
    a source contact and a drain contact are provided, the source contact being in contact with the source and the drain contact being in contact with the drain, each of the source contact and the drain contact comprising a semi-metal layer and a dopant doped in the semi-metal layer, the dopant being of a second doping type opposite to the first doping type.
  15. A semiconductor device, comprising:
    a source electrode and a drain electrode respectively having a first doping type;
    a gate electrode located between the source electrode and the drain electrode; and
    a source contact and a drain contact, the source contact in contact with the source and the drain contact in contact with the drain, each of the source contact and the drain contact comprising a semi-metal layer and a stress layer in contact with the semi-metal layer, the stress layer comprising a metallic material having a different coefficient of thermal expansion or a different lattice parameter than the semi-metal layer.
  16. The semiconductor device of claim 15, wherein the semi-metal layer comprises a two-dimensional semi-metal material or a three-dimensional semi-metal material.
  17. The semiconductor device of claim 15, wherein the stress layer is located over and/or laterally surrounding the semi-metal layer.
  18. The semiconductor device of claim 15, wherein the stress layer comprises a single layer or a stack of layers.
  19. The semiconductor device of claim 15, wherein the semi-metal layer comprises a doped semi-metal material or an undoped semi-metal material.
  20. The semiconductor device of claim 15, wherein a distance between each of the source contact and the drain contact and the gate is 10nm or less.
  21. The semiconductor device according to claim 15, wherein each of the source electrode and the drain electrode comprises a semi-metallic material modulated into a semiconductor type.
  22. A method for manufacturing a semiconductor device, comprising:
    providing a source and a drain, the source and the drain each having a first doping type;
    providing a gate electrode, the gate electrode being located between the source electrode and the drain electrode; and
    a source contact and a drain contact are provided, the source contact being in contact with the source, the drain contact being in contact with the drain, each of the source contact and the drain contact comprising a semi-metal layer and a stress layer in contact with the semi-metal layer, the stress layer comprising a metallic material having a different coefficient of thermal expansion or a different lattice parameter than the semi-metal layer.
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