WO2023159390A1

WO2023159390A1 - Semiconductor device and manufacturing method therefor

Info

Publication number: WO2023159390A1
Application number: PCT/CN2022/077465
Authority: WO
Inventors: 王学雯; 吴颖; 许俊豪
Original assignee: 华为技术有限公司
Priority date: 2022-02-23
Filing date: 2022-02-23
Publication date: 2023-08-31
Also published as: CN117280475A

Abstract

Embodiments of the present disclosure relate to a semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a source and a drain, each having a first doping type; a gate located between the source and the drain; and a source contact and a drain contact. The source contact is in contact with the source, and the drain contact is in contact with the drain. Each contact in the source contact and the drain contact comprises a semi-metal layer and a dopant doped in the semi-metal layer, and the dopant is of a second doping type opposite to the first doping type.

Description

Semiconductor device and manufacturing method thereof

technical field

Embodiments of the present disclosure generally relate to the field of semiconductor devices, and more particularly, to a semiconductor device and a manufacturing method thereof.

Background technique

Dennard Scaling states that as transistors get smaller in size, their power density remains constant. Therefore, the power consumption of the device is one of the key issues to be solved in the miniaturization of the device. For example, the power consumption of a complementary metal-oxide-semiconductor (CMOS) device can be obtained by Equation (1.1), where P is the device power, V _DD is the device operating voltage, and α _i is the "switch activation" of the ith circuit block in the device. Factor" (switching activity factor, 0<α _i <1), C _i is the total effective capacitance of the i-th circuit block (including all interconnections and transistor input capacitance of the i-th circuit block), f is the clock frequency, I _OFF is the off-state current of all transistors biased by the supply voltage V _DD . It can be seen from formula (1.1) that reducing device operating voltage and off-state current can effectively reduce device power consumption. And reducing the sub-threshold slope (Sub-threshold Slope, SS) of the device is a very effective way to reduce the operating voltage of the device.

Equation (1.2) is the calculation equation for the subthreshold slope SS of the device at a temperature of 300K, where

is called the volume factor, V _G is the gate voltage, ψ _s is the surface potential (that is, the difference between the gate voltage V _G and the gate oxide layer voltage),

is the thermal voltage. It can be seen from formula (1.2) that because the traditional MOSFET device is limited by the thermionic limit, its subthreshold slope SS cannot be lower than 60mV/dec. Therefore, in order to maintain a high target current I _ON and a large switching ratio I _ON /I _OFF , the device operating voltage V _DD is relatively large, resulting in high power consumption of the device. At present, in the 7nm and 5nm CMOS integrated circuit technology nodes, the operating voltage V _DD of the device has been reduced to 0.7V. However, since MOSFET devices are limited by the thermionic limit, the minimum operating voltage V _DD of integrated circuits is 0.64V, which cannot effectively reduce device power consumption in the next technology node (3nm/2nm).

Among low-power logic devices, a device with a sub-threshold slope SS<60mV/dec can effectively reduce the working voltage V _DD of the device, thereby reducing the power consumption of the device. However, for a device capable of achieving a subthreshold slope SS<60mV/dec, such as a tunneling field-effect transistor (Tunneling Field-effect Transistor, TFET), its operating current is often more than 2 orders of magnitude smaller than the target current. Therefore, these low-power logic devices also need to maintain a sufficiently high operating current if they want to be suitable for future low-power high-performance chips.

A conventional scheme utilizes the characteristics that the half-metal band gap is zero and the electronic density of states near the Fermi surface is close to zero, and it is proposed that a semi-metal with a specific Fermi level can effectively reduce the nail between the metal and the semiconductor. The pinch effect, thereby reducing the contact resistance between the metal and the semiconductor, makes its subthreshold slope SS approach 60mV/dec. However, a pure semi-metal contact still cannot break through the thermionic limit, so the subthreshold slope SS rate can only infinitely approach 60mV/dec, but cannot be less than 60mV/dec.

Contents of the invention

Embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, aiming to solve the above-mentioned problems and other potential problems existing in conventional semiconductor devices.

Embodiments of the present disclosure provide a low-power transistor device (including NMOS transistor and PMOS transistor) and its manufacturing process that are compatible with existing CMOS processes and use doped semi-metallic materials as source and drain contacts. Integrated in existing planar transistors, fin field effect transistors (FinFETs), ring gate field effect transistors (GAA FETs) and vertical structure nanowire field effect transistors (Vertical NWFET) structures, and then can realize CMOS based on this transistor Devices such as inverters and logic circuits.

According to a first aspect of the present disclosure, there is provided a semiconductor device including: a source and a drain respectively having a first doping type; a gate located between the source and the drain; and a source contact and a drain contact, the source contact is in contact with the source, the drain contact is in contact with the drain, and each of the source contact and the drain contact A contact includes a half-metal layer and a dopant doped in the half-metal layer, the dopant being a second doping type opposite to the first doping type.

In some embodiments, the half-metal layer includes a two-dimensional half-metal material.

In some embodiments, the two-dimensional semi-metallic material includes at least one of the following: graphene and two-dimensional transition metal chalcogenides.

In some embodiments, the two-dimensional transition metal chalcogenides include at least one of the following: WTe ₂ ; MoTe ₂ ; W ₂ XY, where X and Y are sulfur (S), selenium (Se) and tellurium (Te ), and X is different from Y; and Mo ₂ XY, wherein X and Y are respectively one of sulfur (S), selenium (Se) and tellurium (Te), and X is different from Y.

In some embodiments, where the first doping type is p-type and the second doping type is n-type, the dopant includes nitrogen (N), and in the first doping type When the heterotype is n-type and the second dopant type is p-type, the dopant includes boron (B).

In some embodiments, the half-metal layer includes a three-dimensional half-metal material.

In some embodiments, the three-dimensional semi-metallic material includes at least one of the following: tin (Sn), bismuth (Bi), antimony (Sb), tellurium (Te), arsenic (As), and germanium (Ge), and Compounds of the above elements.

In some embodiments, the three-dimensional semi-metallic material includes at least one of the following: a spinel structure, a perovskite structure, a rutile structure, and a semi-Hughler and Hughler structure.

In some embodiments, the spinel structure includes at least one of Fe ₃ O ₄ and CuV ₂ S ₄ ; the perovskite structure includes La _0.7 Sr _0.3 MnO ₃ ; the rutile structure includes CrO ₂ and at least one of CoS ₂ ; and the semi-Hugherella and Hugherder structures include at least one of NiMnSb and PbMnSb.

In some embodiments, when the first doping type is n-type and the second doping type is p-type, the dopant includes tin (Sn), and in the first doping type When the dopant type is p-type and the second dopant type is n-type, the dopant includes tellurium (Te).

In some embodiments, the field effect transistor is a planar field effect transistor, a fin field effect transistor, a gate-all-around field effect transistor or a vertical structure nanowire field effect transistor.

In some embodiments, the distance between each of the source contact and the drain contact and the gate is less than 10 nm.

In some embodiments, each of the source and the drain includes a half-metal material modulated to be semiconducting.

According to a second aspect of the present disclosure, there is provided a method for manufacturing a semiconductor device, comprising: providing a source and a drain respectively having a first doping type; providing a gate, the gate is located between the source and the drain; and a source contact and a drain contact are provided, the source contact is in contact with the source, the drain contact is in contact with the The drain contact, each of the source contact and the drain contact includes a half-metal layer and a dopant doped in the half-metal layer, the dopant being A second doping type opposite to the first doping type.

According to a third aspect of the present disclosure, there is provided a semiconductor device, including: a source and a drain each having a first doping type; a gate located between the source and the drain; and a source contact and a drain contact, the source contact is in contact with the source, the drain contact is in contact with the drain, and each of the source contact and the drain contact Each contact includes a half-metal layer and a stress layer in contact with the half-metal layer, the stress layer includes a metal material having a different thermal expansion coefficient or a different lattice parameter from the half-metal layer.

In some embodiments, the half-metal layer includes a two-dimensional half-metal material or a three-dimensional half-metal material.

In some embodiments, the stress layer is located on the half-metal layer and/or the stress layer laterally surrounds the half-metal layer.

In some embodiments, the stressor layer comprises a single layer or a stack of multiple layers.

In some embodiments, the half-metal layer includes a doped half-metal material or an undoped half-metal material.

According to a fourth aspect of the present disclosure, there is provided a method for manufacturing a semiconductor device, comprising: providing a source and a drain respectively having a first doping type; providing a gate, the gate is located between the source and the drain; and a source contact and a drain contact are provided, the source contact is in contact with the source, the drain contact is in contact with the The drain contact, each of the source contact and the drain contact includes a half-metal layer and a stress layer in contact with the half-metal layer, the stress layer includes a layer in contact with the half-metal Layers have metallic materials with different thermal expansion coefficients or different lattice parameters.

The structure of the semiconductor device in the embodiment of the present disclosure is similar to that of a traditional MOSFET device, the manufacturing process is relatively simple, and it is compatible with the existing CMOS process.

When the semiconductor device of the embodiment of the present disclosure is in the off state, due to the existence of the Schottky barrier and the pinning effect, and the reduction of the carrier concentration caused by the movement of the half-metal Fermi surface, the off state of the device The current is smaller than conventional MOSFET devices, and the subthreshold slope SS is less than 60mV/dec. In addition, when the semiconductor device of the embodiment of the present disclosure is working, the source-drain Schottky barrier is reduced until it disappears, the pinning effect is gradually weakened until it disappears, and the increase in carrier concentration brought about by the movement of the half-metal Fermi surface makes the device A larger target current can be obtained at a lower operating voltage V _DD , and the subthreshold slope SS is less than 60mV/dec. Therefore, the device structures and technical solutions proposed in the embodiments of the present disclosure can be applied to manufacture semiconductor devices with low power consumption and high performance.

This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or principal characteristics of the disclosure, nor is it intended to limit the scope of the disclosure.

Description of drawings

The above and other objects, features and advantages of embodiments of the present disclosure will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the present disclosure are shown by way of example and not limitation.

FIG. 1 shows a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

Fig. 2 shows the distribution of the Fermi surface of a p-type doped half-metal material.

Fig. 3 shows a schematic diagram of carrier distribution of an n-channel device using a p-type doped semi-metal material as a source-drain contact when the operating voltage is positive.

Fig. 4 shows a schematic diagram of carrier distribution of an n-channel device using a p-type doped semi-metal material as a source-drain contact when the operating voltage is negative.

FIG. 5 shows a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

Figure 6 shows the distribution of the Fermi surface of an n-type doped half-metal material.

FIG. 7 shows a schematic diagram of the carrier distribution of a p-channel device using an n-type doped semi-metal material as the source-drain contact when the working voltage is positive.

Fig. 8 shows a schematic diagram of carrier distribution of a p-channel device using an n-type doped semi-metal material as a source-drain contact when the operating voltage is negative.

FIG. 9 shows a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

FIG. 10 shows a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

FIG. 11 shows a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

FIG. 12 shows a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

FIG. 13 shows a perspective view of a semiconductor device according to one embodiment of the present disclosure.

FIG. 14 shows a perspective view of a semiconductor device according to one embodiment of the present disclosure.

FIG. 15 shows a perspective view of a semiconductor device according to one embodiment of the present disclosure.

In the respective drawings, the same or corresponding reference numerals denote the same or corresponding parts.

Detailed ways

Preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

As used herein, the term "comprise" and its variants mean open inclusion, ie "including but not limited to". The term "or" means "and/or" unless otherwise stated. The term "based on" means "based at least in part on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment." The term "another embodiment" means "at least one further embodiment". The terms "upper", "lower", "front", "rear" and other words indicating placement or positional relationship are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the principles of the present disclosure, rather than indicating or implying References to elements must have a particular orientation, be constructed, or operate in a particular orientation, and thus should not be construed as limiting the disclosure.

Embodiments of the present disclosure provide a semiconductor device and a method of manufacturing the same to solve the above-mentioned problems and other potential problems existing in conventional semiconductor devices. Hereinafter, the principle of the present disclosure will be described in detail with reference to the accompanying drawings and exemplary embodiments.

FIG. 1 shows a schematic cross-sectional view of a semiconductor device 100 according to an embodiment of the present disclosure. As shown in FIG. 1 , a semiconductor device 100 includes a substrate 10 , a source 20 , a drain 30 , a source contact 21 , a drain contact 31 and a gate 40 . Source 20 and drain 30 are formed at the top surface of substrate 10 . The source contact 21 is in contact with the source 20 for electrical connection. The drain contact 31 is in contact with the drain 30 for electrical connection. A gate 40 is formed on the top surface of the substrate 10 via a gate dielectric 41 . When the semiconductor device 100 is in operation, the channel 11 connecting the source 20 and the drain 30 may be formed in the substrate 10 . Taking an n-channel semiconductor device 100 as an example, the substrate 10 of the semiconductor device 100 has p-type doping, and its source 20 and drain 30 are heavily doped n-type regions. The source contact 21 and the drain contact 31 of the semiconductor device 100 use a p-type doped semi-metal material (p-SM). A p-type doped half-metal means that its Fermi surface _EF is modulated to the valence band (VB), as shown in Figure 2. When a positive voltage is applied to the gate 40 , an inversion layer is generated in the p-type substrate 10 , thereby forming a channel 11 , and electrons will be injected into the n-type source and drain

electrodes

20 , 30 and corresponding source and

drain contacts

21 , 31 . Thereby, the Fermi surface _EF of p-SM moves up, and gradually migrates from the valence band (VB) to the conduction band (CB). The resistance decreases, and at the same time, the hole concentration of the source 20 decreases, while the electron (carrier) concentration increases, so that the current increases rapidly, as shown in FIG. 3 . Therefore, compared with common nFETs, the semiconductor device 100 can obtain a larger working current, and at the same time, the subthreshold slope SS is reduced to below 60 mV/dec. However, when a negative voltage is applied to the gate 40 , hole accumulation occurs in the p-type substrate 10 , and the holes are injected into the n-type source and drain

electrodes

20 , 30 and corresponding source and

drain contacts

21 , 31 . Thus, the Fermi surface _EF of the p-SM moves further down in the valence band (VB), at this time the contact resistance between the source-

drain contacts

21, 31 and the n-type source-

drain electrodes

20, 30 increases, and the source The hole concentration of the electrode 20 increases, while the electron (carrier) concentration decreases, so that the current drops rapidly, as shown in FIG. 4 . Therefore, compared with common nFETs, the semiconductor device 100 can achieve a lower off-state current, while the subthreshold slope SS is less than 60 mV/dec. In general, since the sub-threshold slope SS of the semiconductor device 100 is less than 60 mV/dec, to achieve the same switching ratio (I _ON /I _OFF ), the operating voltage V _DD of the semiconductor device 100 is lower. At the same time, due to the existence of a larger contact resistance, the off-state current of the semiconductor device 100 is lower. Therefore, the semiconductor device 100 synergistically achieves low power consumption from the two aspects of reducing the operating voltage and reducing the off-state current.

FIG. 5 shows a schematic cross-sectional view of a semiconductor device 200 according to an embodiment of the present disclosure. The structure of the semiconductor device 200 shown in Figure 5 is similar to that of the semiconductor device 100 shown in Figure 1, the difference is that the semiconductor device 200 shown in Figure 5 is a p-channel device, while the semiconductor device 100 shown in Figure 1 is an n-channel device. Specifically, the substrate 10 of the semiconductor device 200 has n-type doping, and its source 20 and drain 30 are heavily doped p-type regions. The source contact 21 and the drain contact 31 of the semiconductor device 200 use an n-type doped semi-metal material (n-SM). An n-type doped half-metal means that its Fermi surface _EF is modulated to the conduction band (CB), as shown in Figure 6. When a positive voltage is applied to the gate 40 , charge accumulation occurs in the n-type substrate 10 , and electrons are injected into the p-type source and drain

electrodes

20 , 30 and corresponding source and

drain contacts

21 , 31 . Thus the Fermi surface _EF of the n-SM moves further up in the conduction band (CB), and at this moment the contact resistance between the source-

drain contacts

21, 31 and the p-type source-

drain electrodes

20, 30 increases, while the source The hole (carrier) concentration of 20 decreases, causing the current to drop rapidly, as shown in Figure 7. Therefore, compared with a common pFET, the semiconductor device 200 can achieve a lower off-state current, while the subthreshold slope SS is less than 60 mV/dec. And when a negative voltage is applied to the gate 40, an inversion layer is generated in the n-type substrate 10, thereby forming a channel 11, and holes are injected into the p-type source and drain

electrodes

20, 30 and corresponding source and

drain contacts

21, 31 , so that the Fermi surface _EF of the n-SM moves down, the contact resistance between the source-

drain contacts

21, 31 and the p-type source-

drain electrodes

20, 30 decreases, and the hole (carrier) concentration increases, so that the current increase rapidly, as shown in Figure 8. Therefore, compared with the common pFET, the semiconductor device 200 can obtain a larger working current, and at the same time, the subthreshold slope SS is reduced to below 60 mV/dec. Generally speaking, since the sub-threshold slope SS of the semiconductor device 200 is less than 60 mV/dec, to achieve the same switching ratio (I _ON /I _OFF ), the operating voltage V _DD of the semiconductor device 200 is lower. At the same time, due to the existence of a larger contact resistance, the off-state current of the semiconductor device 200 is lower. Therefore, the semiconductor device 200 also synergistically realizes low power consumption from the two aspects of reducing the operating voltage and reducing the off-state current.

Semiconductor devices according to embodiments of the present disclosure may be of various types, such as planar field effect transistors, fin field effect transistors, gate-all-around field effect transistors, or vertical structure nanowire field effect transistors. An exemplary structure of a semiconductor device will be described below with reference to FIGS. 9 to 15 .

FIG. 9 shows a schematic cross-sectional view of a semiconductor device 300 according to an embodiment of the present disclosure. The semiconductor device 300 is an n-type planar field effect transistor. As shown in FIG. 9 , a semiconductor device 300 includes a substrate 10 , a source 20 , a drain 30 , a source contact 21 , a drain contact 31 and a gate 40 . Source 20 and drain 30 are formed at the top surface of substrate 10 . The source contact 21 is in contact with the source 20 for electrical connection. The drain contact 31 is in contact with the drain 30 for electrical connection. A gate 40 is formed on the top surface of the substrate 10 via a gate dielectric 41 . The substrate 10 of the semiconductor device 300 has p-type doping, and its source 20 and drain 30 are heavily doped n-type regions. Exemplarily, the heavily doped n-type region may be Silicon Phosphorus Si:P (Silicon Phosphorus), where Si:P means doping phosphorus (P) into silicon (Si) to achieve n-type doping. The source contact 21 and the drain contact 31 of the semiconductor device 300 adopt a p-type doped half-metal material (p-SM), and the p-type doped half-metal material includes a half-metal layer and is doped in the half-metal layer adulterants in. Exemplary, the p-type doped half-metal material can be Bi:Sn (Bismuch Stannum), wherein Bi:Sn represents doping tin (Sn) in bismuth (Bi), that is, bismuth (Bi) forms a half-metal layer , tin (Sn) is doped in bismuth (Bi) as a dopant, thereby realizing p-type doping. In some examples, the semiconductor device 300 further includes a gate spacer 42 covering the gate 42 . In some examples, the semiconductor device 300 further includes an insulating medium 43 for isolating the source-

drain contacts

21 , 31 from the gate 40 .

FIG. 10 shows a schematic cross-sectional view of a semiconductor device 400 according to an embodiment of the present disclosure. The semiconductor device 400 is a p-type planar field effect transistor. As shown in FIG. 10 , the semiconductor device 400 includes a substrate 10 , a source 20 , a drain 30 , a source contact 21 , a drain contact 31 and a gate 40 . Source 20 and drain 30 are formed at the top surface of substrate 10 . The source contact 21 is in contact with the source 20 for electrical connection. The drain contact 31 is in contact with the drain 30 for electrical connection. A gate 40 is formed on the top surface of the substrate 10 via a gate dielectric 41 . The substrate 10 of the semiconductor device 400 has n-type doping, and its source 20 and drain 30 are heavily doped p-type regions. Exemplarily, the heavily doped p-type region may be silicon germanium Si:Ge (Silicon Germanium), where Si:Ge means doping germanium (Ge) into silicon (Si) to achieve p-type doping. The source contact 21 and the drain contact 31 of the semiconductor device 400 adopt an n-type doped half-metal material (n-SM), and the n-type doped half-metal material includes a half-metal layer and is doped in the half-metal layer adulterants in. Exemplary, the n-type doped half-metal material can be Bi:Te (Bismuch Tellurium), wherein Bi:Te represents doping tellurium (Te) in bismuth (Bi), that is, bismuth (Bi) forms a half-metal layer , tellurium (Te) is doped in bismuth (Bi) as a dopant, thereby realizing n-type doping. In some examples, the semiconductor device 400 further includes a gate spacer 42 covering the gate 42 . In some examples, the semiconductor device 400 further includes an insulating medium 43 for isolating the source-

drain contacts

21 , 31 from the gate 40 .

For the selection of half-metal materials, two categories of two-dimensional half-metal materials and three-dimensional half-metal materials can be used. In the future, it is also possible to develop one-dimensional half-metal materials and zero-dimensional half-metal materials, which can also be used as half-metal layers in the source-

drain contacts

21 , 31 . Two-dimensional semi-metallic materials include, but are not limited to, graphene, two-dimensional transition metal chalcogenides, and the like. Two-dimensional transition metal chalcogenides can be, for example, WTe ₂ , MoTe ₂ , W ₂ XY (X, Y=S, Se, Te, X≠Y) and Mo ₂ XY (X, Y=S, Se, Te, X ≠ one or more of Y). In some embodiments, the three-dimensional half-metal material can be half-metal elements and some metalloid elements in the periodic table, including but not limited to tin (Sn), bismuth (Bi), antimony (Sb), tellurium (Te), arsenic (As) and germanium (Ge), and compounds containing these elements. Compounds of the above elements include, but are not limited to, TaAs, ZrTe ₅ , Na ₃ Bi, Cd ₃ As ₂ and GdPtBi. In some embodiments, the three-dimensional semi-metallic material can be other compounds with semi-metallic properties, including but not limited to spinel structure (example, Fe ₃ O ₄ , CuV ₂ S ₄ ), perovskite structure (example Exemplary, La _0.7 Sr _0.3 MnO ₃ ), Rutile structures (Exemplary, CrO ₂ , CoS ₂ ) and Half-Heusler and Heusler structures (Exemplary, NiMnSb, PbMnSb) .

The acquisition of doped half-metal materials can be achieved by element doping in the half-metal layer to adjust the Fermi level of the half-metal materials. For two-dimensional semi-metallic materials, such as graphene, for example, the graphene can be made n-type by doping nitrogen (N), and the graphene can be made p-type by doping boron (B). For a three-dimensional semi-metallic material, such as bismuth (Bi), it can be effectively p-type doped by doping tin (Sn), and can be effectively n-type doped by doping tellurium (Te). The Fermi surface of semi-metallic materials can be effectively tuned by element doping.

In some embodiments, the distance between the source-

drain contacts

21 , 31 and the gate 40 should be as narrow as possible to reduce the average carrier change caused by thermal disturbance. For example, the distance between the source-

drain contacts

21 , 31 and the gate 40 may be below 10 nm. In addition, in order to reduce the impact of thermal disturbance, semi-metal materials whose energy bands are modulated into semiconductor type can be used as the source and drain

electrodes

20 and 30 in contact with the source and

drain contacts

21 and 31, and the modulation method can be element doping Or stress regulation, can also be achieved by controlling the thickness or shape of semi-metallic materials. Exemplarily, for the semi-metallic material Bi _1-x Sb _x , the transition from semi-metal to semiconductor can be induced by changing the content of Sb; for the semi-metallic material Bi ₈ Te ₇ S ₅ , the semi-metal can be induced by controlling the thickness of the material Metal to semiconductor transition.

In some embodiments, a method for fabricating

semiconductor devices

300 and 400 is also provided. The method includes: providing a source 20 and a drain 30 each having a first doping type; providing a gate 40 positioned between the source 20 and the drain 30; and providing the source Contact 21 and drain contact 31, source contact 21 is in contact with source 20, drain contact 31 is in contact with drain 30, each of source contact 21 and drain contact 31 includes The half-metal layer and the dopant doped in the half-metal layer, the dopant is a second doping type opposite to the first doping type. In case the first doping type is n-type, the second doping type is p-type. While the first doping type is p-type, the second doping type is n-type. The content described above with reference to FIG. 9 and FIG. 10 can be incorporated into the method for manufacturing the

semiconductor devices

300 and 400 , and will not be repeated here.

FIG. 11 shows a schematic cross-sectional view of a semiconductor device 500 according to an embodiment of the present disclosure. The semiconductor device 500 is an n-type or p-type planar field effect transistor. As shown in FIG. 11 , a semiconductor device 500 includes a substrate 10 , a source 20 , a drain 30 , a source contact 21 , a drain contact 31 and a gate 40 . Source 20 and drain 30 are formed at the top surface of substrate 10 . The source contact 21 is in contact with the source 20 for electrical connection. The drain contact 31 is in contact with the drain 30 for electrical connection. A gate 40 is formed on the top surface of the substrate 10 via a gate dielectric 41 . In some examples, the semiconductor device 500 further includes a gate spacer 42 covering the gate 42 . In some examples, the semiconductor device 500 further includes an insulating medium 43 for isolating the source-

drain contacts

21 , 31 from the gate 40 . In the case that the semiconductor device 500 is an nFET, the substrate 10 of the semiconductor device 500 has p-type doping, and its source 20 and drain 30 are heavily doped n-type regions. Exemplarily, the heavily doped n-type region may be Silicon Phosphorus Si:P (Silicon Phosphorus), where Si:P means doping phosphorus (P) into silicon (Si) to achieve n-type doping. In case the semiconductor device 500 is a pFET, the substrate 10 of the semiconductor device 500 has n-type doping, and its source 20 and drain 30 are heavily doped p-type regions. Exemplarily, the heavily doped p-type region may be silicon germanium Si:Ge (Silicon Germanium), where Si:Ge means doping germanium (Ge) into silicon (Si) to achieve p-type doping.

The source contact 21 includes a semi-metal layer 211 and a stress layer 212 . The drain contact 31 includes a semi-metal layer 311 and a stress layer 312 . The half-

metal layers

211 and 311 may be doped half-metal layers or undoped half-metal layers. The half-metal material in the half-

metal layers

211 and 311 may be a two-dimensional half-metal material or a three-dimensional half-metal material. The stress layers 212 and 312 can control the stress of the

semi-metal layers

211 and 311 respectively. For 2D half-metal materials, the electron concentration of _MoTe2 can be regulated by stress. For three-dimensional semi-metallic materials, such as TaAs, the stress layers 212 and 312 can control the stress of the

semi-metallic layers

211 and 311 respectively, so as to adjust its band gap so that its Weyl point (Weyl point) changes, thereby affecting its charge transport performance. . In addition, stress regulation can also change the energy band shape. When the band curvature becomes sharper, the subthreshold slope SS of the device can be reduced more effectively. Therefore, stress regulation is also a means to effectively adjust the Fermi surface of semimetallic materials. The stress layers 212 and 312 may be metal materials with different thermal expansion coefficients or different lattice parameters from the half-

metal layers

211 and 311 . As shown in FIG. 11 , the stress layer 212 is located above the half-metal layer 211 , and the stress layer 312 is located above the half-metal layer 311 . With this arrangement, stressor layers 212 and 312 primarily provide out-of-plane stress.

In some embodiments, the distance between the source-

drain contacts

electrodes

20 and 30 in contact with the source and

drain contacts

FIG. 12 shows a schematic cross-sectional view of a semiconductor device 600 according to one embodiment of the present disclosure. The semiconductor device 600 is an n-type or p-type planar field effect transistor. As shown in FIG. 12 , the semiconductor device 600 includes a substrate 10 , a source 20 , a drain 30 , a source contact 21 , a drain contact 31 and a gate 40 . Source 20 and drain 30 are formed at the top surface of substrate 10 . The source contact 21 is in contact with the source 20 for electrical connection. The drain contact 31 is in contact with the drain 30 for electrical connection. A gate 40 is formed on the top surface of the substrate 10 via a gate dielectric 41 . In some examples, the semiconductor device 500 further includes a gate spacer 42 covering the gate 42 . In some examples, the semiconductor device 500 further includes an insulating medium 43 for isolating the source-

drain contacts

21 , 31 from the gate 40 . In the case that the semiconductor device 600 is an nFET, the substrate 10 of the semiconductor device 600 has p-type doping, and its source 20 and drain 30 are heavily doped n-type regions. Exemplarily, the heavily doped n-type region may be Silicon Phosphorus Si:P (Silicon Phosphorus), where Si:P means doping phosphorus (P) into silicon (Si) to achieve n-type doping. In case the semiconductor device 600 is a pFET, the substrate 10 of the semiconductor device 600 has n-type doping, and its source 20 and drain 30 are heavily doped p-type regions. Exemplarily, the heavily doped p-type region may be silicon germanium Si:Ge (Silicon Germanium), where Si:Ge means doping germanium (Ge) into silicon (Si) to achieve p-type doping.

metal layers

semi-metal layers

211 and 311 respectively. For two-dimensional semi-metallic materials, for example, the electron concentration of MoTe ₂ can be adjusted by stress. For three-dimensional semi-metallic materials, such as TaAs, the stress layers 212 and 312 can control the stress of the

semi-metallic layers

metal layers

211 and 311 . As shown in FIG. 12 , the stress layer 212 laterally surrounds the half-metal layer 211 , and the stress layer 312 laterally surrounds the half-metal layer 311 . With this arrangement, stressor layers 212 and 312 primarily provide in-plane stress.

In some embodiments, the distance between the source-

drain contacts

electrodes

20 and 30 in contact with the source and

drain contacts

In some embodiments, if omnidirectional stress is to be provided, the schemes of applying stress shown in FIG. 11 and FIG. 12 can also be combined, or other double stress layer or more stress layer stacking schemes can be adopted.

In some embodiments, a method for fabricating

semiconductor devices

500 and 600 is also provided. The method includes: providing a source 20 and a drain 30 each having a first doping type; providing a gate 40 positioned between the source 20 and the drain 30; and providing the source Contact 21 and drain contact 31, source contact 21 is in contact with source 20, drain contact 31 is in contact with drain 30, each of source contact 21 and drain contact 31 includes The half-

metal layer

211, 311 and the

stress layer

212, 312 in contact with the half-

metal layer

211, 311, the

stress layer

212, 312 includes a metal material having a different thermal expansion coefficient or a different lattice parameter from the half-metal layer. In case the first doping type is n-type, the second doping type is p-type. While the first doping type is p-type, the second doping type is n-type. The content described above with reference to FIG. 11 and FIG. 12 can be incorporated into the method for manufacturing the

semiconductor devices

500 and 600 , and will not be repeated here.

In addition, both the source 20 and the drain 30 of the planar field effect transistor shown in FIGS. 9 to 12 can retain the epitaxial process, and can still provide sufficient stress for the device channel, and ensure that the device achieves a larger operating current through the stress technology. . Epitaxial growth refers to the growth of a single crystal layer with certain requirements and the same crystal orientation as the substrate on a single crystal substrate (substrate), as if the original crystal had grown outward for a period.

FIG. 13 shows a perspective view of a semiconductor device 700 according to one embodiment of the present disclosure. As shown in FIG. 13 , the semiconductor device 700 is a FinFET. The semiconductor device 700 includes a substrate 10; a fin 23 formed on the substrate 10, one end of the fin 23 forms the source 20, and the other end of the fin 23 forms the drain 30; a gate 40 is formed between the source 20 and the Between the drain 30 is surrounded by the middle portion of the fin 23 via the gate dielectric 41; and the source contact 21 and the drain contact 31, the source contact 21 at least partially surrounds the source 20, and the drain contact 31 Drain 30 is at least partially surrounded. The source contact 21 and the drain contact 31 shown in FIG. 13 may have a similar structure to the source contact 21 and the drain contact 31 described above in conjunction with FIGS. Let me repeat. In some embodiments, the semiconductor device 700 further includes an isolation dielectric 50 formed on the top surface of the substrate 10 around the fin 23 .

FIG. 14 shows a perspective view of a semiconductor device 800 according to one embodiment of the disclosure. As shown in FIG. 14 , the semiconductor device 800 is a gate-all-around field effect transistor. The semiconductor device 800 includes a substrate 10; a source contact 21 and a drain contact 31 are arranged at intervals on the substrate 10; a plurality of sources 20 are in contact with the source contact 21; a plurality of drains 30 are connected to the drain A pole contact 31 contacts; a plurality of channels 11 formed between source 20 and drain 30 ; and a gate 40 surrounds each channel 11 via a gate dielectric 41 . The source contact 21 and the drain contact 31 shown in FIG. 14 may have a similar structure to the source contact 21 and the drain contact 31 described above in conjunction with FIGS. Let me repeat. In some embodiments, the semiconductor device 800 further includes an isolation dielectric 50 formed around the substrate 10 .

FIG. 15 shows a perspective view of a semiconductor device 900 according to one embodiment of the present disclosure. As shown in FIG. 15, the semiconductor device 900 is a vertical structure nanowire field effect transistor. The semiconductor device 900 includes: a nanowire forming a source 20 at one end, a drain 30 at the other end, and a channel 11 in its middle; a gate 40 surrounding the channel 11 via a gate dielectric 41; and a source contact and A drain contact (not shown), the source contact contacts the source 20 for electrical connection, and the drain contact contacts the drain for electrical connection. The source contact and the drain contact of the semiconductor device 900 may have structures similar to those of the source contact 21 and the drain contact 31 described above in conjunction with FIGS. 9 to 12 , which will not be repeated here.

Although the principles of the present disclosure have been described above in connection with planar field effect transistors, fin field effect transistors, gate-all-around field effect transistors, or vertical structure nanowire field effect transistors, it should be understood that in other embodiments, the described The structure of source and drain contacts can be incorporated into other types of transistors.

Having described various embodiments of the present disclosure above, the foregoing description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and alterations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principle of each embodiment, practical application or technical improvement in the market, or to enable other ordinary skilled in the art to understand each embodiment disclosed herein.

Claims

A semiconductor device, characterized in that, comprising:

a source electrode and a drain electrode respectively having a first doping type;

a gate located between the source and the drain; and

a source contact and a drain contact, the source contact being in contact with the source, the drain contact being in contact with the drain, the source contact and the drain contact being Each contact includes a half-metal layer and a dopant doped in the half-metal layer, the dopant being a second doping type opposite to the first doping type.
The semiconductor device according to claim 1, wherein the half-metal layer comprises a two-dimensional half-metal material.
The semiconductor device according to claim 2, wherein the two-dimensional semi-metallic material comprises at least one of the following: graphene and two-dimensional transition metal chalcogenides.
The semiconductor device according to claim 3, wherein the two-dimensional transition metal chalcogenide comprises at least one of the following:

WTe 2 ;

MoTe 2 ;

W 2 XY, wherein X and Y are each one of sulfur (S), selenium (Se) and tellurium (Te), and X is different from Y; and

Mo 2 XY, wherein X and Y are respectively one of sulfur (S), selenium (Se) and tellurium (Te), and X and Y are different.
The semiconductor device according to claim 2, wherein in the case where the first doping type is p-type and the second doping type is n-type, the dopant includes nitrogen (N) ,and

In a case where the first doping type is n-type and the second doping type is p-type, the dopant includes boron (B).
The semiconductor device according to claim 1, wherein the half-metal layer comprises a three-dimensional half-metal material.
The semiconductor device according to claim 6, wherein the three-dimensional half-metal material comprises at least one of the following: tin (Sn), bismuth (Bi), antimony (Sb), tellurium (Te), arsenic (As) and germanium (Ge), and compounds containing the above elements.
The semiconductor device according to claim 6, wherein the three-dimensional semi-metallic material comprises at least one of the following: a spinel structure, a perovskite structure, a rutile structure, and a semi-Hughler and Hughler structure.
The semiconductor device according to claim 8, wherein,

The spinel structure includes at least one of Fe 3 O 4 and CuV 2 S 4 ;

The perovskite structure includes La 0.7 Sr 0.3 MnO 3 ;

The rutile structure includes at least one of CrO2 and CoS2 ; and

The semi-Hugherella and Hugherder structures include at least one of NiMnSb and PbMnSb.
The semiconductor device according to claim 6, wherein in the case where the first doping type is n-type and the second doping type is p-type, the dopant includes tin (Sn) ,and

In the case where the first doping type is p-type and the second doping type is n-type, the dopant includes tellurium (Te).
The field effect transistor according to claim 1, wherein the field effect transistor is a planar field effect transistor, a fin field effect transistor, a ring gate field effect transistor or a vertical structure nanowire field effect transistor.
The semiconductor device according to claim 1, wherein the distance between each of the source contact and the drain contact and the gate is 10 nm or less.
The semiconductor device according to claim 1, wherein each of the source and the drain includes a half-metal material modulated into a semiconductor type.
A method for manufacturing a semiconductor device, comprising:

providing a source and a drain each having a first doping type;

providing a gate located between the source and the drain; and

A source contact and a drain contact are provided, the source contact contacts the source, the drain contact contacts the drain, the source contact and the drain contact Each contact in includes a half-metal layer and a dopant doped in the half-metal layer, the dopant being a second doping type opposite to the first doping type.
A semiconductor device, characterized in that, comprising:

a source electrode and a drain electrode respectively having a first doping type;

a gate located between the source and the drain; and

a source contact and a drain contact, the source contact being in contact with the source, the drain contact being in contact with the drain, the source contact and the drain contact being Each contact includes a half-metal layer and a stress layer in contact with the half-metal layer, and the stress layer includes a metal material having a different thermal expansion coefficient or a different lattice parameter from the half-metal layer.
The semiconductor device according to claim 15, wherein the half-metal layer comprises a two-dimensional half-metal material or a three-dimensional half-metal material.
The semiconductor device according to claim 15, wherein the stress layer is located on the half-metal layer and/or the stress layer laterally surrounds the half-metal layer.
The semiconductor device according to claim 15, wherein the stress layer comprises a single layer or a stack of multiple layers.
The semiconductor device according to claim 15, wherein the half-metal layer comprises a doped half-metal material or an undoped half-metal material.
The semiconductor device according to claim 15, wherein a distance between each of the source contact and the drain contact and the gate is 10 nm or less.
The semiconductor device according to claim 15, wherein each of the source and the drain includes a half-metal material modulated into a semiconductor type.
A method for manufacturing a semiconductor device, comprising:

providing a source and a drain each having a first doping type;

providing a gate located between the source and the drain; and

A source contact and a drain contact are provided, the source contact contacts the source, the drain contact contacts the drain, the source contact and the drain contact Each contact in includes a half-metal layer and a stress layer in contact with the half-metal layer, and the stress layer includes a metal material having a different thermal expansion coefficient or a different lattice parameter from the half-metal layer.