KR100839752B1 - Manufacture method of semiconductor device structure using self-aligned epitaxial layers - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a semiconductor device structure using a self-aligned epitaxial growth layer as a channel and a method of manufacturing the same, comprising: a first step of growing a template epitaxial layer on a semiconductor substrate; A second step of growing a template after the first step; A third step of depositing a self-aligned epi layer after the second step; A fourth step of forming a CMP surface after the third step; Removing the template after the fourth step and growing an oxide film; A sixth step of depositing a gate thin film after the fifth step; Forming a gate pattern after the sixth step and passivating the insulating layer; and including a self-aligned epitaxial channel of a semiconductor device having a technology of 45 nm or less, which is very difficult to fabricate due to extremely miniaturization. It can be formed by growth.

Self-aligned epitaxial growth layer, semiconductor device structure, MOS, CMOS, SOI-CMOS

Description

Manufacture method of semiconductor device structure using self-aligned epitaxial layers}

1 is a cross-sectional view schematically showing a conventional MOS device.

2 illustrates a method of manufacturing a semiconductor device structure using a self-aligned epitaxial growth layer as a channel according to an embodiment of the present invention, and shows a method of manufacturing a MOS device.

3A to 3G are cross-sectional views illustrating a manufacturing step according to FIG. 2.

4 shows a method of manufacturing a semiconductor device structure using a self-aligned epitaxial growth layer as a channel according to another embodiment of the present invention, and shows a method of manufacturing a CMOS device.

5A through 5K are cross-sectional views illustrating a manufacturing step of FIG. 4.

6 shows a method of manufacturing a semiconductor device structure using a self-aligned epitaxial growth layer as a channel according to another embodiment of the present invention, and shows a method of manufacturing a SOI-CMOS device.

7A to 7C are cross-sectional views illustrating a manufacturing step according to FIG. 6.

Explanation of symbols on the main parts of the drawings

111 semiconductor substrate, 112 well, 113 gate oxide film, 114 gate, 115 sidewall, 116 source-drain, 117 metal junction, 118 insulating film, 121 semiconductor substrate, 122 well, 123 gate oxide film 124: gate, 125 sidewall, 126: elevated source-drain, 127: metal junction, 128: insulating film, 131: semiconductor substrate, 132: oxide film, 133: channel, 134: gate oxide film, 135: gate, 136: insulating film

201: semiconductor substrate, 202: template epi layer, 203: template, 204: self-aligned epi layer, 205: CMP surface, 206: oxide film, 207: gate thin film, 208: gate pattern, 209: insulating film

301: semiconductor substrate, 203: template epi layer, 303: template, 304: sacrificial oxide film, 305: P-well, 306: N-well, 307: self-aligned epi layer, 308: P-well external diffusion, 309: N-well diffusion, 310: CMP surface, 311: sacrificial oxide film, 312: ion implantation for PMOS body junction, 313: ion implantation for NMOS body junction, 314: gate oxide film, 315: gate thin film, 316: PMOS gate, 317 NMOS gate, 318: PMOS body junction, 319: NMOS body junction, 320: insulating film

401: semiconductor substrate, 402: oxide film, 403: SOI, 404: channel, 405: gate oxide film, 406: PMOS well, 407: NMOS well, 408: PMOS gate, 409: NMOS gate, 410: PMOS body, 411: NMOS Body, 412: device isolation oxide film

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device structure and a method for fabricating the same, and in particular, a self-alignment structure suitable for forming a channel of a semiconductor device whose technology is advanced to 45 nm or less, which is very difficult to manufacture due to extremely miniaturization. A semiconductor device structure using an epitaxial growth layer as a channel, and a method of manufacturing the same.

In recent years, Complementary Metal-Oxide Semiconductor (CMOS) technology has reduced the minimum line width to less than 70 nm and has been announced to store more than a few Gbits of memory. These technological development efforts will continue, and by 2013, a minimum line width of 35 nm and an integration density of 10 ¹⁰ cm ^-2 are expected. Nevertheless, there are many concerns about whether the value-added integration of silicon semiconductors will reach its limit and continue to develop in 2013, which is ~ 10nm level according to Moore's law. It is becoming. On the other hand, applications of MOS (Metal-Oxide Semiconductor) devices are increasingly being used for high-speed RF (Radio Frequency) and micro-communication, which are considered to be the limit of performance, and the development of various information technology (IT) communication technologies And the convergence of BT (Biology Technology) and NT (Nano Technology) are expanding to a wide range of applications such as System-on-Chip (SoC). In addition, to achieve this purpose, attempts have been made to replace the structure and manufacturing process of semiconductor devices in three dimensions or with new materials. [KH Shim, SH Kim, YJ Song, NE Lee, SW Lim, JY Kang, Development of SiGe heterostructure epitaxial growth and device fabrication technology using RPCVD, JKIEEME 18, 285, 2005]

Recently, various efforts have been made to improve the function of CMOS to implement an SoC for various electronic devices. For example, a Bipolar Complementary Metal- BiCMOS (SiCe Heterojunction Bipolar Transistor) or HMOS (Heterostructure MOS) is added. Oxide Semiconductor, bipolar CMOS) has been tried. Recently, RF functional devices or optical functional devices are integrated to form a system-on-chip, which is expected to increase the price and performance of the system. In order to achieve high integration and high speed, an optoelectronic device is attached to a silicon integrated circuit to implement a silicon optoelectronic integrated circuit to achieve intra- and inter-chip communication. Problems related to this are power management by low power operation, reduction of semiconductor device manufacturing cost, etc., and efforts to develop an unprecedented three-dimensional new device.

On the other hand, device structures with a minimum line width of 45 nm or less begin to be developed, and along with the development of process technology, technologies such as quantum effects, physical new areas such as uncertain current flow, excessive power consumption, design complexity, and tunneling Research has been attempted to overcome difficulties. That is, research and development are mainly attempted to solve various kinds of technical problems that devices having nano-scale gates will face. The main candidates expected to achieve such advances include a silicon on insulator (SOI) device, and a change in device architecture to which new quantum physics is applied by heterojunction devices. As mentioned above, as the adoption of a two-dimensional channel reaches its limit, an attempt has been made to employ a three-dimensional channel in a device.

In addition, as control of device structures, processes, and circuit driving by classical physics and statistics has reached a very difficult scale, it has become difficult to control reproducibility and uniformity with conventional techniques. In order to overcome this problem, attention is focused on the direction of next-generation semiconductor technology. One of the types of semiconductor devices that are attracting attention as such next-generation semiconductor devices is MODFET (MOdulation Doped Field Effect Transistor), also known as HEMT. Attempts have been made to employ heterojunction layers of III-V compound semiconductors as well as group IV semiconductors in such MODFET devices. [K.H. Shim, et al., Solid-State Technology, Mar. 51-56, 2004] Similarly, the technology development for the three-dimensional Fin-MOS has been actively developed, and it is possible to use about twice as much process margin in minimizing the channel at 30 nm or less, and the subthreshold leakage current The great advantage is that they are blocked very effectively. In other words, the three-dimensional heterojunction structure, and the structure that adds the speed-control effect to control the stress will emerge as a key technology in creating new devices.

1A to 1C are schematic diagrams of a conventional metal-oxide semiconductor field-effect transistor (Si MOSFET) device, a typical MOSFET (FIG. 1A), a strained-MOSFET using elevated-SiGe (FIG. 1B), and a FinMOSFET using SOI (FIG. 1A). Shows 1c).

1A is a cross-sectional view of a conventional MOSFET device which is the most used ever. The well 112 is formed on the semiconductor substrate 111, and the gate oxide film 113 and the gate 114 are fabricated. The device is announced in the 10nm range, but below 65nm, the limit is shown by the variation of the subthreshold current and the threshold voltage. Therefore, in the case of such a conventional high-end device, a prediction has been made that the structure and material of the device should be changed below 45 nm.

As described above, in the case of conventional MOSFETs, the problem is seriously hindered in the stable operation of the device when operating at high voltage or high frequency instead of simple manufacturing. In an attempt to overcome this problem, a method of fabricating a fully depleted SOI MOSFET is proposed.

However, the fabrication of semiconductor devices, such as MOSFETs with SOI structures, presents an uneconomical problem of using silicon substrates fabricated at very expensive special SOI processes. In addition, there is a limit that the yield of the semiconductor device is greatly reduced depending on the uniformity and performance of the SOI silicon substrate. In addition, the SOI structure has a problem of acting as a 1 / f noise source because a large amount of incomplete bonds or trap centers exist at the silicon-oxide interface.

1B is an example of a semiconductor device using strained channels. It is basically the same as MOSFET of FIG. 1A, but PMOS (P-Channel Metal-Oxide Semiconductor, P-type metal oxide film) is applied to the source and drain 116 by growing an epitaxial layer having a large lattice constant, such as SiGe, and applying a compressive stress to the channel. Semiconductor) increases the mobility of holes in the channel under the gate oxide film 123 and decreases the subthreshold current. In addition, the epi-layer of the source-drain is grown in an elevated structure to decrease the contact resistance and the sheet resistance, thereby improving the conduction characteristics of the device. In a similar manner, an NMOS (N-Channel Metal-Oxide Semiconductor, N-type metal oxide semiconductor) film is deposited on top of the device to increase the transfer speed of electrons by subjecting the channel to tensile stress. This device structure is expected to be usefully applied to the 45nm band, but after that, it is expected to change to the device structure of thin body SOI or FinMOS without solving the fundamental problem of short channel effect.

1C is the structure of FinMOS, which is expected to be useful at 30 nm and below. An oxide layer 132 was deposited on the semiconductor substrate 131, and a channel 133 was formed thereon, and the gate oxide layer 134 and the gate 135 were sequentially deposited and formed. The channel is completely isolated by SOI, and the fin structure channel is wrapped around the gate to reduce the subthreshold current caused by the Short Channel Effect (SCE). However, there is a difficulty in developing a smaller device structure due to the difficulty of photo-transfer in order to produce patterns of 30 nm or less. Therefore, it is necessary to simplify the manufacturing process and to increase process cost and reliability.

The trap-detrap increased by hot carriers in MOSFETs of the prior art suggests low and high frequency noise. [Y.J. Song, et al., Semiconductor Science and Technology, 19, 791-797, 2004] Moreover, the design parameters and the optimization of the circuit are due to the consideration of the very complicated electrical characteristics of fabricating and using MOS devices on SOI. The burden is on. Therefore, MOSFETs have the characteristics of speeding up the operation speed of current scaling methods, but there are various difficulties. Therefore, there is a need to devise a special new structure device that conducts stably in a local channel in the device structure.

Accordingly, the present invention has been proposed to solve the above-mentioned conventional problems, and an object of the present invention is to self-align epitaxial growth of a channel of a semiconductor device in which technology is advanced to 45 nm or less, which is very difficult to manufacture due to extremely miniaturization. A semiconductor device structure using a self-aligned epitaxial growth layer that can be formed as a channel, and a method of manufacturing the same are provided.

In order to achieve the above object, a method of manufacturing a semiconductor device structure using a self-aligned epitaxial growth layer as a channel according to an embodiment of the present invention,

Growing a template epi layer on the semiconductor substrate; A second step of growing a template after the first step; A third step of depositing a self-aligned epi layer after the second step; A fourth step of forming a CMP surface after the third step; Removing the template after the fourth step and growing an oxide film; A sixth step of depositing a gate thin film after the fifth step; And a seventh step of forming a gate pattern after the sixth step and passivating the insulating layer.

Hereinafter, an embodiment according to the present invention, a semiconductor device structure using a self-aligned epitaxial growth layer as a channel, and a technical concept of a method of manufacturing the same will be described with reference to the accompanying drawings.

FIG. 2 illustrates a method of manufacturing a semiconductor device structure using a self-aligned epitaxial growth layer as a channel according to an embodiment of the present invention, and illustrates a method of manufacturing a MOS device, and FIGS. 3A to 3G are manufactured by FIG. It is a cross-sectional view showing the steps.

As shown therein, a first step ST1 of growing the template epitaxial layer 202 on the semiconductor substrate 201; A second step (ST2) of growing the template (203) after the first step; A third step (ST3) of depositing a self-aligned epi layer (204) after the second step; A fourth step (ST4) of forming a CMP (Chemical Mechanical Polishing) surface after the third step (205); A fifth step (ST5) of removing the template (203) and growing an oxide film (206) after the fourth step; A sixth step ST6 for depositing a gate thin film 207 after the fifth step; And forming a gate pattern 208 after the sixth step and passivating the insulating film 209 (ST7) to fabricate a MOS semiconductor device structure.

In the third step, at least one gas of silane (SiH ₄ ), disilane (Si ₂ H ₆ ), and dichlorosilane (SiCl ₂ H ₂ ) gas is used as a main reaction gas as a gas source of silicon. It is characterized by.

In the third step, at least one or more gases of AsH ₃ , PH _3, and B ₂ H ₆ may be diluted with hydrogen gas or helium gas when the impurities are doped.

In the fifth step, the removal thickness of the template 203 is adjusted so that the stress state of the channel layer is adjusted according to the lattice constant of the template 203.

In the sixth step, an in-situ doped poly (IDP) layer is deposited by doping a high concentration of impurities in-situ on the gate thin film 207 so that the gate thin film 207 has low resistance. It is done.

4 illustrates a method of manufacturing a semiconductor device structure using a self-aligned epitaxial growth layer as a channel according to another embodiment of the present invention, and shows a method of manufacturing a CMOS device, and FIGS. 5A to 5K are manufactured by FIG. 4. It is a cross-sectional view showing the steps.

As shown therein, an eleventh step (ST11) of growing the template epitaxial layer 302 on the semiconductor substrate 301; A twelfth step (ST12) of growing the template (303) after the eleventh step; A thirteenth step (ST13) for forming a sacrificial oxide film (304) after the twelfth step and performing ion implantation of the P-well (305) and the N-well (306); A fourteenth step (ST14) of removing the sacrificial oxide film (304) after the thirteenth step and depositing a self-aligned epi layer (307); A fifteenth step ST15 of removing the CMP surface 310 after the fourteenth step; A sixteenth step (ST16) of removing the template (303) after the fifteenth step and growing a sacrificial oxide film (311); A seventeenth step (ST17) of performing ion implantation 312 for PMOS body junction and ion implantation 313 for NMOS body junction after the sixteenth step; An eighteenth step (ST18) of removing the sacrificial oxide film (311) after the seventeenth step, growing the gate oxide film (314), and depositing a gate thin film (315); A nineteenth step ST19 for forming a PMOS gate 316 and an NMOS gate 317 after the eighteenth step; A twentieth step (ST20) of forming a PMOS body junction (318) and an NMOS body junction (319) after the nineteenth step; And a twenty-first step ST21 for depositing the insulating film 320 after the twelfth step, thereby manufacturing a CMOS semiconductor device structure.

The thirteenth step may be performed by depositing a thick insulating film on the sacrificial oxide film 304.

In the sixteenth step, the removal thickness of the template 303 is adjusted so that the stress state of the channel layer is adjusted according to the lattice constant of the template 303.

In the eighteenth step, the gate thin film 315 may be doped with a high concentration of impurities in-situ to deposit an IDP layer so that the gate thin film 315 may have a low resistance.

FIG. 6 illustrates a method of manufacturing a semiconductor device structure using a self-aligned epitaxial growth layer as a channel according to another embodiment of the present invention, and shows a method of manufacturing an SOI-CMOS device, and FIGS. 7A to 7C are FIGS. The cross-sectional view showing the manufacturing step by.

As shown therein, a thirty-first step ST31 of forming an oxide film 402 and an SOI 403 on the semiconductor substrate 401; A thirty-second step (ST32) of growing a template epitaxial layer on the semiconductor substrate (401) after the thirty-first step; A thirty-third step (ST33) of growing the template after the thirty-second step; A thirty-fourth step (ST34) for forming a sacrificial oxide film after the thirty-third step and performing ion implantation of the P-well (406) and the N-well (407); Removing the sacrificial oxide layer after the thirty-fourth step and depositing a self-aligned epitaxial layer (ST35); A 36 th step (ST36) of removing the CMP surface after the 35 th step; Removing the template after the 36th step and growing a sacrificial oxide film (ST37); A 38 th step (ST38) to perform ion implantation for PMOS body junction and ion implantation for NMOS body junction after the 37 th step; A thirty-ninth step (ST39) for removing the sacrificial oxide film, growing a gate oxide film (405), and depositing a gate thin film after the thirty-eighth step; A 40th step (ST40) of forming a PMOS gate (408) and an NMOS gate (409) after the 39th step; A forty-first step (ST41) of forming a PMOS body (410) junction and an NMOS body (411) junction after the forty step; A 42nd step (ST42) of growing a device isolation oxide film (412) after the 41st step; And a 43rd step ST43 for depositing an insulating film after the 42nd step, to fabricate an SOI-CMOS semiconductor device structure.

The thirty-fourth step may include depositing a thick insulating film on the sacrificial oxide film.

In the step 37, the removal thickness of the template is adjusted so that the stress state of the channel layer is adjusted according to the lattice constant of the template.

In the 39 th step, the gate thin film is doped with a high concentration of impurities in-situ to deposit an IDP layer so that the gate thin film is controlled to have low resistance.

A semiconductor device structure using the self-aligned epitaxial growth layer according to the present invention configured as described above and a method of manufacturing the same will be described in detail with reference to the accompanying drawings. In the following description of the present invention, detailed descriptions of well-known functions or configurations will be omitted if it is determined that the detailed description of the present invention may unnecessarily obscure the subject matter of the present invention. In addition, terms to be described below are terms defined in consideration of functions in the present invention, which may vary according to intention or precedent of a user or an operator, and thus, the meaning of each term should be interpreted based on the contents throughout the present specification. will be.

First of all, the present invention intends to form a channel of a semiconductor device in which the technology is advanced to 45 nm or less due to extremely miniaturization by self-aligned epitaxial growth.

<Example 1>

3A to 3G are cross-sectional views of devices schematically illustrated to explain a method of forming the core of the device of FIG. 2. The present invention provides a structure of a device using a template and a strained-fin channel having a self-aligned structure and a method of fabricating the same for forming a microchannel in the present invention.

In the present invention, since the epitaxial growth of the template is used as a channel, the channel thickness can be precisely controlled to about 1 nm. Therefore, 1) 1D strained channel, 2) Fin structure using Epi, 3) Self-aligned channel up to nm, 4) Easy to apply SOI, 5) Dynamic Threshold Voltage Metal-Oxide Semiconductor (DTMOS) by body contact 6) The manufacturing process is simple and the manufacturing cost is low.

The present invention can be applied to further improve the high-speed operation characteristics for use in the high-speed digital-analog circuit of the 1 ~ 10GHz band. Higher specifications are required to apply circuits such as static random access memory (SRAM), central processing unit (CPU), and analog to digital converter (ADC) in applications such as high frequency communication, microwave sensors, and radar. . Therefore, the key is to adopt a device structure that takes advantage of the new three-dimensional structure to create a very fine channel and increase the operating speed and breakdown voltage at the same time compared to the conventional silicon semiconductor.

As in ST1 of FIG. 2 and FIG. 3A, the template epitaxial layer 202 is grown on the semiconductor substrate 201. To grow SiGe and silicon as epitaxial layer, equipment for Atmospheric Pressure Chemical Vapor Deposition, Equipment for Low Pressure Chemical Vapor Deposition, or Ultra High Vacuum Chemical Vapor Deposition It is preferred to use equipment for this purpose and to use such equipment in a reducing atmosphere of hydrogen. In particular, it is necessary to grow a quantum well layer with a thickness as thin as several nm and to accurately control the uniformity of the mole fraction of Ge within 0.02%.

In order to fabricate an element on the semiconductor substrate 201, a semiconductor substrate of silicon is first cleaned using a known cleaning method such as H ₂ SO ₄ / H ₂ O ₂ and H ₂ O / HF cleaning, RCA method, and the like. Thereafter, the diffusion blocking layer including the buffer layer is formed by epitaxial growth. In this case, the diffusion blocking layer is formed of an epitaxial layer having an energy band structure that has a diffusion coefficient of impurities more than twice as large as that of the upper semiconductor thin film and forms a quantum well that can serve as a drain of an excess carrier. It features.

The epi of the template layer is later patterned to adjust the lattice constant to stress the epi growth of the fin channel layer to be laterally grown. For example, when SiGeC is applied, the lattice constant is increased when the Ge content is increased to control the contents of Si, Ge, and C, and when the content of C is increased, the lattice constant is decreased. Therefore, when the SiGeC layer containing a lot of Ge is used for the template, the Fin channel receives tensile stress, and if the C content is high, the compressive stress is received. Since the epitaxial growth is performed on the semiconductor substrate, the content of the atoms can be artificially controlled. The influence of the lattice constant is transferred to the epichannel layer grown on the side surface.

In ST2 and FIG. 3B of FIG. 2, a template pattern is formed by photophotographic transfer using a photoresist, and then a template 203 is formed by dry etching. Since the surface of the template epi layer 202 has to be flat, heat treatment is performed at a high temperature of 1100 ^° C. or higher, and atoms of the surface diffuse in a hydrogen atmosphere to form a flat surface having low surface energy.

In ST3 of FIG. 2 and FIG. 3C, the epitaxial layer 204 for the self-alignment channel is deposited by Ultra High Vacuum Chemical Vapor Deposition (UHVCVD). During the growth of such epitaxial layers 204, the native oxide, which is formed on the surface of a semiconductor substrate, that is, a wafer, between the charges in the growth chamber is 900 ^o C to 1000 ^o C. It is removed by heat treatment at a temperature of hydrogen atmosphere for about 2 minutes or more. The growth chamber is then adapted to the temperature and gas atmosphere for epitaxial growth. The epitaxial growth apparatus described above is equipped with a function of a rapid thermal process (RTP) such as a halogen lamp or an RF induction heater, so that the epitaxial layers can be continuously grown in a complex structure. Can be. In epitaxial growth, the concentration of elements such as P, As, and B can be controlled in the range of 10 ¹⁵ -10 ¹⁸ cm ^-3 as n-type or p-type impurities.

Silane (SiH ₄ ) or disilane (Si ₂ H ₆ ) or dichloro is the gas source of silicon for minimizing the effect transmitted from the semiconductor thin film, increasing the effect of insulation isolation, and for high quality epitaxial growth. Silane (SiCl ₂ H ₂ ) gas may be used as the main reaction gas. For the doping of impurities, a gas such as AsH ₃ , PH ₃ , B ₂ H ₆ is diluted with hydrogen gas or helium gas.

In ST4 of FIG. 2 and FIG. 3D, the CMP surface 205 is formed. That is, the epitaxial layer for the channel portion of the surface portion 205 is removed to adjust the template pattern. Here, planarization is performed using an oxide film and / or a nitride film deposited by CVD (Chemical Vapor Deposition) for uniform etching of the surface. After flattening, the generated defects are removed and heat treated in a hydrogen atmosphere to flatten the surface at the atomic layer level. When the surface is planarized at the atomic level, there is little interfacial scattering in the Fin channel, thereby greatly increasing the mobility of electrons or holes. This principle has been very important in devices employing heterojunction semiconductor channels.

In ST5 and FIG. 3E of FIG. 2, the template 203 is removed using wet etching having a high selective etching ratio. The surface is then oxidized to grow an oxide film 206 for use as a sacrificial oxidation that is surface protective oxidation. The self-aligned epi layer formed here uses a channel of Fin structure. The stress state of the channel layer can be adjusted according to the lattice constant of the template. Strained-Fin presented in this form is the only patent provided. In particular, since the thickness of the channel fin is controlled by epitaxial growth, it is very important that the thickness accuracy can be precisely adjusted up to 1 nm.

In ST6 of FIG. 2 and FIG. 3F, a gate thin film 207 is deposited. Chemical vapor deposition, such as reduced pressure chemical vapor deposition (RPCVD) or ultra high vacuum chemical vapor deposition (UHVCVD), allows the gate thin film to be uniformly deposited in a shape having a large aspect ratio. At this time, in order to ensure uniform deposition on both the top and side portions, the deposition is performed in order of successively low temperature seed layer growth followed by rapid gate thin film growth. The gate thin film is doped with a high concentration of impurities in-situ to control the gate resistance is low. The resistance of the gate is a very important device parameter that controls the device's operating speed and high frequency noise.

In ST7 and FIG. 3G of FIG. 2, the gate pattern 208 is made of photoresist using photoresist, and the gate is defined by wet etching. Formation of the MOS structure is completed by the epitaxial layer formed by the gate, the oxide film and the self alignment, and then passivated with the insulating film 209. Of course, the highly integrated circuit continues the metallization process after the shape of the device is completed, such a conventional technique can be applied to this process.

The present invention can be easily applied to a SOI substrate as well as a bulk substrate as a semiconductor substrate to produce a channel having a stressed Fin structure. The present invention relates to a structure of a semiconductor device and a method of fabricating the same, to overcome the difficulty of fabrication due to the miniaturization of a semiconductor device and to minimize the subthreshold current, which is a problem of the micro device. In addition, the advantages of simplifying the structure and manufacturing method of the device to provide low production cost and high reliability are very important. In addition, body contact is possible by connecting the lower part of the fin channel to the semiconductor substrate, and it is also possible to drain excess carriers generated by hot carriers, and to control the power consumption and operation speed flexibly by manufacturing the DTMOS device structure. It can be applied to the circuit. In addition, heterojunction structures made of materials such as Si, SiGe, and SiGeC may be used for the same principle as the semiconductor substrate and the epi layer.

<Example 2>

The second embodiment is as described in FIGS. 4 and 5A-5K and shows an embodiment for the fabrication of CMOS using a self-aligned epi layer as a channel.

As in ST11 and FIG. 5A of FIG. 4, a template epitaxial layer 302 is deposited over the semiconductor substrate 301. As described above, the template epi layer is composed of several elements, and is designed in a structure capable of controlling the stress of the channel epi layer grown on the side surface.

In ST12 and FIG. 5B of FIG. 4, photophotographic transfer is performed with photoresist to form a template pattern, and then the template 303 is formed by dry etching.

In ST13 and FIG. 5C of FIG. 4, the sacrificial oxide film 304 is formed and phototransferred to perform ion implantation of the P-well 305 and the N-well 306. If necessary, an additional thick insulating film may be deposited. The well is formed by self-implantation using the sacrificial oxide film or the insulating film as a mask. These wells are important for effectively blocking subthreshold currents or leakage currents to the gate edges by maintaining the proper spacing and doping concentration with the channel.

In ST14 and FIG. 5D of FIG. 4, the sacrificial oxide film 304 is removed and an epitaxial layer 307 to be used as a channel is grown. At this time, the deposition of the epi channel layer shows another redistribution to the external diffusion of impurities implanted into the source-drain region. As above, the concentration of impurities out-diffusion is properly controlled because it affects the leakage current and transconductance characteristics of the device. Where reference numeral 308 is P-well external diffusion and reference 309 is N-well external diffusion.

In ST15 and FIG. 5E of FIG. 4, the upper CMP surface 310 is etched away. As shown in FIG. 3D, an intermediate layer of an oxide film or a nitride film is deposited and planarized to have an overall uniform planarization. Similarly, after planarization, heat treatment is performed to remove defects and to obtain a flatter surface at the atomic layer level. Surface planarization is a very important process step that controls the mobility of the carriers conducting in the channel layer.

In ST16 and FIG. 5F of FIG. 4, the template 303 is removed by wet etching having a high etching selectivity, and then another sacrificial oxide film 311 is grown.

In ST17 and FIG. 5G of FIG. 4, a pattern corresponding to the contact of the P-well 305 and the N-well 306 is formed using photoresist using photoresist, respectively, and the P-type 312 and the N-type, respectively. (313) Ion implantation of impurities. This is to reduce the contact resistance of the ohmic junction, and is implanted with the energy of ions in proper contact with the well, and then heat treated with Rapid Thermal Annealing (RTA) to activate impurities.

In ST18 and FIG. 5G of FIG. 4, the gate oxide film 314 is grown after the sacrificial oxide film 311 is removed by wet etching. The gate thin film 315 is then deposited. In-situ doped Poly (IDP) layer of polycrystalline thin film which injects high concentration of impurities at low temperature is deposited and used as gate.

In ST19 and FIG. 5I of FIG. 4, a gate pattern is formed by photophotographic transfer using photoresist, and gates 316 and 317 for PMOS and NMOS are formed by dry etching, respectively.

In ST20 and 5J of FIG. 4, a PMOS body junction 318 and an NMOS body junction 319 are formed. That is, metal silicides 318 and 319 are deposited on the source and the drain to make ohmic contact. In this case, when the silicide is formed by depositing a metal thin film as a whole, the process may be performed with silicides in which silicides are self-aligned in the source-gate-drain. In such silicide, a basic metal thin film of Co, Ni, Ti, and a TiN, Pt thin film protecting the same are used as a multi-layer structure. In particular, when the silicide having a structure such as Ni / Pt is applied to the extremely micro device, the thermal characteristics are excellent.

In ST21 and FIG. 5K of FIG. 4, an insulating film 320 for passivation is deposited. In this way, the fabrication of CMOS having the Fin channel to which the stress is applied is simple, and the reproducibility and uniformity can be improved. Body contact is possible by connecting the lower part of the fin channel to the semiconductor substrate through ion implantation. Accordingly, it is possible to drain the excess carrier generated by the hot carrier, and to manufacture and drive the DTMOS device structure, it can be applied as a circuit that flexibly adjusts the power consumption and operation speed.

<Example 3>

The third embodiment is as described in Figures 6 and 7A-7C.

In FIG. 6 and FIG. 7A, an oxide film 402 and an SOI 403 are formed and used on the semiconductor substrate 401. At this time, the thickness of the oxide film and the thickness of the SOI affect the device isolation and the formation of the body contact of the device fabricated above, so that it is adjusted to a thickness suitable for the process conditions.

In FIG. 6, ST32 to ST41 and FIG. 7B refer to devices fabricated under almost the same conditions as those of the device structure described in FIGS. 4 and 5A to 5J. The PMOS well 406 and the NMOS well 407 are formed on the oxide film 402, and the channel 404, the gate oxide film 405, the PMOS gate 408, and the NMOS gate 409 are sequentially formed. It is showing. In addition, a PMOS body 410 and an NMOS body 411 are formed. By adopting SOI, the insulation effect from the board is more excellent, which is advantageous for RF circuit application and reduces the leakage current flowing to the board. On the other hand, there is a possibility of lowering the performance of the device due to the low heat transfer effect as an intrinsic problem of the SOI substrate in which the oxide film is present.

In FIG. 6, ST43 and 7C are similar to those of FIG. 7B, but the structure in which the thickness of the SOI layer is controlled to be thinner and the oxide film 412 for device isolation is grown between the PMOS and the NMOS to ensure electrical insulation between the devices. In this structure, the thickness of the SOI can be reduced to several nm, making it well suited for applications in microchannels.

As a next-generation semiconductor device according to the present invention, a MOSFET having a three-dimensional structure is generally improved by increasing mobility of a carrier to improve high-speed operation characteristics, low leakage current, and nonlinear operation characteristics due to a short channel. Improves. In applying the heterojunction semiconductor described above, compound semiconductors such as SiGe, SiGeC, GaAs, InP, GaN, and SiC can be used as appropriate.

For example, the energy gaps of Si, Ge, and SiC are 1.1, 0.7, 2.3 eV, and the lattice constants are 5.43, 5.64, and 4.37 kV, respectively, when no stress due to the difference in lattice constant is applied. In the silicon semiconductor, the electron mobility reaches 1,500 cm ² / Vs when the impurity concentration is 10 ¹⁶ cm ⁻³ or less, but when the doping concentration increases by 10 to 100 times, the electron mobility is severely reduced to several hundreds. In contrast, SiGe itself has high mobility from 10 ¹⁸ cm ^-3 to 2,000 cm ² / Vs, and in the case of pseudomorphic, the collision cross-sectional area of the carrier decreases due to deformation of the band gap, resulting in mobility of 3,000 It has the advantage of increasing to -4,000 cm ² / Vs. Therefore, the heterojunction structure can be applied to the epitaxial layer for the Fin channel of the present patent. In this case, it is expected that the improvement of performance obtained in the heterojunction will be further added.

As described above, by fabricating a semiconductor device using the device structure, it is possible to reduce the value of the power consumption and the delay time compared to the conventional Si MOS, and as a current limiting function by applying a strained-fin channel in a three-dimensional structure Therefore, the linear characteristics of the CMOS can be improved. The ultra-miniaturization of semiconductor devices is achieved by epi-growth self-alignment method with template, and it provides advantages such as low voltage drive of less than 1.5V, accurate threshold voltage control and low power consumption. Therefore, the operation characteristics of several tens of gigabit ULSI and several tens of gigahertz may be applicable to not only memory devices, but also radio wave integrated circuits and millimeter wave integrated circuits. It can also be used to implement next-generation converged semiconductor devices such as CPUs, microprocessors, photonic integrated circuits, and system-on-chips.

As described above, the semiconductor device structure using the self-aligned epitaxial growth layer as a channel and a method of manufacturing the self-aligned channel of a semiconductor device whose technology is advanced to 45 nm or less, which is very difficult to manufacture due to extremely miniaturization. There is an effect that can be formed by the type epi growth.

Although the above has been described as being limited to the preferred embodiment of the present invention, the present invention is not limited thereto and various changes, modifications, and equivalents may be used. Therefore, the present invention can be applied by appropriately modifying the above embodiments, it will be obvious that such application also belongs to the scope of the present invention based on the technical idea described in the claims below.

Claims (14)

Growing a template epi layer on the semiconductor substrate; A second step of growing a template after the first step; A third step of depositing a self-aligned epi layer after the second step; A fourth step of forming a CMP surface after the third step; Removing the template after the fourth step and growing an oxide film; A sixth step of depositing a gate thin film after the fifth step; A seventh step of forming a gate pattern after the sixth step and passivating the insulating layer; A method of manufacturing a semiconductor device structure using a self-aligned epitaxial growth layer as a channel, characterized in that to produce a MOS semiconductor device structure. The method of claim 1, wherein the third step, As a gas source of silicon, at least one selected from silane (SiH ₄ ), disilane (Si ₂ H ₆ ), and dichlorosilane (SiCl ₂ H ₂ ) gas is used as a main reaction gas. A method of manufacturing a semiconductor device structure using an alignment epitaxial growth layer as a channel. The method of claim 1, wherein the third step, Method for manufacturing a semiconductor device structure using a self-aligned epitaxial growth layer as a channel, characterized in that at least one gas selected from AsH ₃ , PH ₃ , and B ₂ H ₆ is diluted with hydrogen gas or helium gas when doping impurities . The method according to claim 1, wherein the fifth step, The method of manufacturing a semiconductor device structure using a self-aligned epitaxial growth layer as a channel, characterized in that the removal thickness of the template is adjusted so that the stress state of the channel layer is adjusted according to the lattice constant of the template. The method according to claim 1, wherein the sixth step, A method of manufacturing a semiconductor device structure using a self-aligned epitaxial growth layer as a channel, characterized in that the gate thin film is doped with a high concentration of impurities in-situ to deposit an IDP layer so that the resistance of the gate thin film is controlled to be low. An eleventh step of growing a template epi layer on the semiconductor substrate; A twelfth step of growing a template after the eleventh step; Forming a sacrificial oxide film after the twelfth step and performing ion implantation of the P-well and the N-well; Removing the sacrificial oxide film after the thirteenth step and depositing a self-aligned epi layer; A fifteenth step of removing the CMP surface after the fourteenth step; Removing the template after the fifteenth step and growing a sacrificial oxide film; A seventeenth step of performing ion implantation for PMOS body junction and ion implantation for NMOS body junction after the sixteenth step; An eighteenth step of removing the sacrificial oxide film, growing a gate oxide film, and depositing a gate thin film after the seventeenth step; A nineteenth step of forming a PMOS gate and an NMOS gate after the eighteenth step; A twentieth step of forming a PMOS body junction and an NMOS body junction after the nineteenth step; A twenty-first step of depositing an insulating film after the twentieth step; The method of manufacturing a semiconductor device structure using a self-aligned epitaxial growth layer as a channel, characterized in that to produce a CMOS semiconductor device structure. The method according to claim 6, wherein the thirteenth step, A method of manufacturing a semiconductor device structure using a self-aligned epitaxial growth layer as a channel, comprising: depositing a thick insulating film on the sacrificial oxide film. The method of claim 6, wherein the sixteenth step, The method of manufacturing a semiconductor device structure using a self-aligned epitaxial growth layer as a channel, characterized in that the removal thickness of the template is adjusted so that the stress state of the channel layer is adjusted according to the lattice constant of the template. The method of claim 6, wherein the eighteenth step, A method of manufacturing a semiconductor device structure using a self-aligned epitaxial growth layer as a channel, characterized in that the gate thin film is doped with a high concentration of impurities in-situ to deposit an IDP layer so that the resistance of the gate thin film is controlled to be low. A thirty first step of forming an oxide film and SOI on the semiconductor substrate; A thirty-second step of growing a template epi layer on the semiconductor substrate after the thirty-first step; A thirty-third step of growing a template after said thirty-second step; A thirty-fourth step of forming a sacrificial oxide film after the thirty-third step and performing ion implantation of the P-well and the N-well; Removing the sacrificial oxide layer after the thirty-fourth step and depositing a self-aligned epi layer; Removing the CMP surface after the 35th step; Removing the template after the thirty-sixth step and growing a sacrificial oxide film; A thirty-eighth step of performing ion implantation for PMOS body junction and ion implantation for NMOS body junction after the 37 th step; Removing the sacrificial oxide film, growing a gate oxide film, and depositing a gate thin film after the thirty-eighth step; A 40th step of forming a PMOS gate and an NMOS gate after the 39th step; A forty-first step of forming a PMOS body junction and an NMOS body junction after the forty-second step; A 42nd step of growing a device isolation oxide film after the 41st step; A 43rd step of depositing an insulating film after the 42nd step; A method of manufacturing a semiconductor device structure using a self-aligned epitaxial growth layer as a channel, characterized in that to produce a SOI-CMOS semiconductor device structure. The method of claim 10, wherein the 34th step, A method of manufacturing a semiconductor device structure using a self-aligned epitaxial growth layer as a channel, comprising: depositing a thick insulating film on the sacrificial oxide film. The method of claim 10, wherein the 37 step, The method of manufacturing a semiconductor device structure using a self-aligned epitaxial growth layer as a channel, characterized in that the removal thickness of the template is adjusted so that the stress state of the channel layer is adjusted according to the lattice constant of the template. The method of claim 10, wherein the 39th step, A method of manufacturing a semiconductor device structure using a self-aligned epitaxial growth layer as a channel, characterized in that the gate thin film is doped with a high concentration of impurities in-situ to deposit an IDP layer so that the resistance of the gate thin film is controlled to be low. delete

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