KR20070069160A - A semiconductor device including semiconductor regions having differently strained channel regions and a method of manufacturing the same - Google Patents

Abstract

By locally modifying the intrinsic stress of a dielectric layer laterally enclosing gate electrode structures of a transistor configuration formed in accordance with in-laid gate techniques, the charge carrier mobility of different transistor elements may individually be adjusted. In particular, in in-laid gate structure transistor architecture, NMOS transistors and PMOS transistors may receive a tensile and a compressive stress, respectively.

Description

A semiconductor device comprising semiconductor regions having different strained channel regions and a method for manufacturing the same.

 In general, the present invention relates to the formation of integrated circuits, and more particularly to the formation of semiconductor regions with increased charge carrier mobility, such as channel regions of field effect transistors, by creating strain in the semiconductor regions. will be.

Fabrication of integrated circuits requires the formation of multiple circuit elements on a given chip area in accordance with the specified circuit layout. To this end, substantially crystalline semiconductor regions with or without additional dopant material are defined at substrate locations specified to act as “active” regions (ie, at least temporarily to serve as conductive regions). In general, a plurality of process technologies are currently being implemented, and for complex circuits such as microprocessors, storage chips, etc., MOS technology has superior characteristics in terms of operating speed and / or power consumption and / or cost efficiency. Is the most promising approach. During the formation of complex integrated circuits using MOS technology, millions of transistors (ie, N-channel transistors and / or P-channel transistors) are formed on a substrate including a crystalline semiconductor layer. MOS transistors, regardless of whether N-channel transistors or P-channel transistors are considered, are high doped drains (with weakly doped or undoped channel regions disposed between the drain and source regions). And so-called PN junctions formed by the interface of the source regions. The conductivity of the channel region (i.e., the drive current capability of the conductive channel) is formed adjacent to the channel region and controlled by the gate electrode separated from them by a thin insulating layer. The conductivity of the channel region under the formation of the conductive channel due to the application of an appropriate control voltage to the gate electrode depends on the dopant concentration and the mobility of the charge carriers, and for a given expansion of the channel region in the transistor width direction, the source region And the distance between the drain region and the drain region (also referred to as channel length). Thus, with respect to the ability to rapidly create a conductive channel under the insulating layer under application of a control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of the MOS transistors. Thus, because the channel generation rate (i.e., the conductivity of the gate electrode) and the channel resistance substantially determine the transistor characteristics, the reduction in channel length, the associated channel resistance reduction and the increase in gate resistance can cause the channel length to operate in integrated circuits. It becomes the dominant design condition for increasing speed.

However, the continued reduction in transistor dimensions involves a number of problems associated with this that must be addressed so as not to overly offset the benefits obtained by steadily reducing the channel length of the MOS transistors. One major issue in this regard is the development of improved photolithography and etching strategies to reliably and reproducibly produce circuit elements of critical dimensions, such as the gate electrode of transistors, for new device creation. In addition, highly sophisticated dopant profiles in the vertical as well as in the transverse direction are required in the drain and source regions to provide low sheet resistivity and contact resistance with respect to the desired channel controllability. In addition, the vertical position of the PN junctions with respect to the gate insulating layer also represents an important design criterion in terms of leakage current control, in which the reduction in channel length is also associated with the drain with respect to the interface formed by the gate insulating layer and channel region. This is because the depth of the source regions is required. According to other approaches, epitaxially grown regions, which are referred to as raised drain and source regions, are formed at a specific offset relative to the gate electrode, thereby increasing the area of the raised drain and source regions. Provides increased conductivity while maintaining a shallow PN junction with respect to the gate insulating layer.

In other prior art solutions, the problem of increasing the resistivity of polysilicon gate electrodes in very large scaled devices is by replacing metal doped polysilicon currently used as the gate electrode material (in spite of this, Maintaining a self-aligned process sequence for forming the drain and source regions and the gate electrode). This can be done by forming a dummy gate that can act as an implantation mask during the formation of the drain and source regions in relation to the removable sidewall spacers. After embedding the dummy gate in an interlayer dielectric, the dummy gate can be replaced with a highly conductive gate material such as metal. In this "in-laid" gate electrode approach, transistor performance can be greatly improved. However, the limited channel conductivity problem is not addressed by this approach.

Moreover, because the continuous reduction in critical dimensions (ie, gate length of transistors) requires adaptation to the process steps described above and possibly new developments for very complex process techniques, certain channel lengths Increasing the charge carrier mobility of the channel region relative to also improves the device performance of the transistor elements, thus avoiding most of the process adaptations described above with respect to device scaling, while avoiding future technology nodes for scaled devices. It has been proposed to offer the possibility of achieving comparable performance improvements with advances. In principle, at least two mechanisms can be used in combination or separately to increase the mobility of charge carriers in the channel region. First, the dopant concentration in the channel region can be reduced, thus reducing scattering events for charge carriers, thus increasing conductivity. However, the reduction of dopant concentration in the channel region greatly affects the threshold voltage of the transistor device, and thus, if other mechanisms for adjusting the desired threshold voltage are not developed, the dopant concentration reduction is a less attractive approach. Second, the lattice structure of the channel region can be deformed, for example, by generating a tensile stress or compressive stress to generate a strain corresponding to the channel region, which is responsible for the mobility for each of the electrons and holes. Will change. For example, the generation of tensile strain in the channel region increases the mobility of the electrons, where depending on the size and direction of the tensile strain, an increase in mobility up to 120% or more can be obtained, which also directly corresponds to Can be converted into an increase in conductivity. On the other hand, the compressive strain in the channel region increases the mobility of the holes, thus offering the possibility of improving the performance of P-type transistors. The introduction of stress or strain technology into integrated circuit fabrication is a very promising approach to additional device generations, for example, where strained silicon is a "new" type of semiconductor, where a new type of semiconductor Can be fabricated at high speed and powerful semiconductor devices without requiring expensive semiconductor materials and fabrication techniques.

As a result, it has been proposed to introduce, for example, a silicon / germanium layer or a silicon / carbon layer in or below the channel region, in order to create tensile or compressive stresses that can generate corresponding strains. Although transistor performance can be significantly improved by the introduction of a stress-generating layer in or below the channel region, much effort must be put into implementing the formation of stress layers corresponding to conventional and certified MOS technology. For example, additional epitaxial growth techniques must be developed and implemented in the process flow to form germanium-containing or carbon-containing stress layers at appropriate locations in or below the channel region. Thus, process complexity is greatly increased, thereby also increasing the production cost and the possibility of yield reduction.

In view of the foregoing circumstances, there is an alternative technique that allows the creation of different desired stress conditions in different semiconductor regions while providing the possibility of forming improved transistor architectures including the introduction of highly conductive gate electrodes. need.

The following presents a summary of the invention to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is not intended to identify key elements or essential elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some ideas in a simplified form as a prelude to the more detailed description that is described later.

In general, the present invention is a so-called “in-laid” gate having improved stress or strain strategies to provide strain of at least two different sizes or types in two different semiconductor regions. It is directed to a technique that enables a combination of process strategies with the possibility of forming improved transistor architectures such as transistor elements comprising structures. As a result, different regions within the die region or across the entire substrate having a plurality of individual die regions may be used to individually adapt the charge carrier mobility and thus its conductivity to specific process and device requirements. Different strained semiconductor regions may be received. In particular, different types of transistors, such as N-type or N-channel transistors and P-type or P-channel transistors, may receive different types or strains of strain in each channel region, and at the same time Due to the possibility of forming in-laid gate electrode structures based on highly conductive materials such as metals, gate conductivity can be improved if desired.

According to one exemplary embodiment of the present invention, the method includes forming a first position holder structure over a first semiconductor region formed in a semiconductor layer located on a substrate. A second position holder structure is formed over the second semiconductor region formed in the semiconductor layer, and a dielectric layer having a certain intrinsic stress is deposited over the semiconductor layer to surround the first and second position holder structures. Additionally, the portion of the dielectric layer surrounding the second position holder structure is modified to change the intrinsic stress in that portion. Finally, the first and second position holder structures are replaced with a conductive material.

According to another exemplary embodiment of the present invention, a method includes forming a first position holder structure over a first channel region of a first transistor, and a second position holder structure over a second channel region of a second transistor. Forming a step. The first drain and source regions are formed adjacent to the first channel region, and the second drain and source regions are formed adjacent to the second channel region. Furthermore, a first dielectric layer having a first intrinsic stress is formed over the first drain and source regions, and a second dielectric layer having a second intrinsic stress different from the first intrinsic stress is formed over the second drain and source regions. Finally, the first position holder structure is replaced by the first gate electrode structure and the second position holder structure is replaced by the second gate electrode structure.

According to another exemplary embodiment of the present invention, a semiconductor device comprises a first transistor element having a first gate electrode having a first height and a second having a second gate electrode having a second height Transistor elements. The device further includes a first dielectric layer having a first intrinsic stress and transversely surrounding the first gate electrode, wherein the first intrinsic stress acts substantially uniformly to the first height in the first dielectric layer. In addition, the device includes a second dielectric layer having a second intrinsic stress and transversely surrounding the second gate electrode, wherein the second intrinsic stress is different from the first intrinsic stress and has a second height in the second dielectric layer. Until it works substantially uniformly.

The invention can be understood by reference to the following detailed description considered in connection with the accompanying drawings, in which like reference numerals designate like elements.

1A-1H illustrate cross-sectional views of a semiconductor device during various stages of fabrication, wherein each stress layer is formed in proximity to semiconductor regions in accordance with a process strategy that enables formation of in-laid gate electrode structures. Different strains are produced in different semiconductor regions.

2 schematically illustrates a cross-sectional view of a semiconductor device during a fabrication stage, where the intrinsic stress of the stress layer is locally deformed according to further exemplary embodiments.

3A and 3B are cross-sectional views of a semiconductor device at a fabrication stage where ion species are deposited at constant locations to improve stress transfer to each semiconductor region in accordance with further exemplary embodiments of the present invention. Schematically shows.

While various modifications and alternative forms of the invention are possible, the specific embodiments thereof are shown by way of example in the drawings and described in detail herein. However, the description of specific embodiments herein is not intended to limit the invention to the particular forms disclosed, and its intention is to be within the spirit and scope of the invention as defined by the following claims. It is intended to cover modifications, equivalents, and alternatives.

In the following, exemplary embodiments of the present invention are described. For clarity, not all features of an actual implementation are described in this specification. Naturally, in the deployment of all these practical embodiments, numerous implementation-specific decisions, such as system-related compliance and business-related constraints, which may vary from implementation to implementation, must be made to achieve the developer's specific goals. In addition, such development efforts may be complex and time-consuming, but it should be understood that this will be a routine for those skilled in the art having the benefit of this disclosure.

The invention will be explained with reference to the accompanying drawings. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the invention with details known to those skilled in the art. Nevertheless, the attached drawings are included to describe illustrative examples of the present invention. The words and phrases used herein should be interpreted to have a meaning consistent with the words and phrases understood by those skilled in the art. No specific definition of a term or phrase (ie, a definition other than the usual and customary meanings understood by those skilled in the art) is implied through the consistent use of the term or phrase herein. For the scope in which a term or phrase has a special meaning, this particular definition will be presented directly in this specification in a definite manner, directly and unambiguously providing a specific definition of the term or phrase.

The invention is based on the idea that strain in a semiconductor region, such as a channel region of a transistor element, can be generated very effectively by a layer of material having a specific intrinsic stress formed in the vicinity of the semiconductor region of interest. Even on very small scales, such as the different channel regions of complementary transistor pairs, allowing for effective local adjustment of strain in the die region or in different substrate regions including a plurality of die regions. By providing a process strategy, improved strain technology can be combined with improved transistor architecture, thus providing high gate conductivity associated with high charge carrier mobility and thus channel conductivity for even very large scaled transistors. Further exemplary embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

1A schematically illustrates a cross-sectional view of a semiconductor device 100 that includes a substrate 101, where the substrate is any suitable substrate for forming circuit elements of integrated circuits such as microprocessors, storage chips, and the like. Can be represented. Substrate 101 may represent a bulk semiconductor substrate, such as a silicon substrate, or in certain embodiments, may represent a silicon-on-insulator (SOI) substrate, where semiconductor layer 102 is substrate 101. And a crystalline silicon layer formed on an insulating layer (not shown) within. Since most advanced integrated circuits manufactured according to MOS techniques are fabricated on a silicon basis, in the detailed description below, this may often be referred to as silicon with respect to the semiconductor layer 102, where gallium arsenide, germanium, silicon It should be understood that any other suitable semiconductor materials, such as germanium, or any other III-V or II-VI semiconductor materials, may also be used in the present invention. Similarly, semiconductor layer 102 may represent an upper portion of a bulk semiconductor substrate, although shown as a separate layer.

The semiconductor device 100 includes a first position holder structure 104a formed of any suitable material, such as silicon dioxide, amorphous carbon, or the like. The first position holder structure 104a is formed over the first semiconductor region 107a, which may represent the first channel region if the transistor is formed by the first position holder 104a. First doped regions 106a, which may be arranged symmetrically or asymmetrically with the first semiconductor region 107a, may be formed in layer 102, and in the illustrated embodiment, in the form of drain and source regions Can be provided. That is, the vertical and horizontal dopant profiles of the first doped regions 106a can be designed according to the device requirements of a particular transistor type. Thus, in certain embodiments, doped regions 106a represent first drain and source regions comprising an internal dopant material that adds a particular type of conductivity to these regions. In the present embodiment, the regions 106a are N-doped, and the regions 106a combined with the first semiconductor region 107a may have characteristics of an N-channel transistor. In addition, sidewall spacers 105a are formed on the sidewalls of the first position holder 104a, which sidewall spacers 105a exhibit, in certain embodiments, the desired high etch selectivity in subsequent etching processes. It may be different from the first position holder 104a in the material structure to produce it. For example, the sidewall spacers 105a may be made of amorphous carbon, silicon nitride, silicon dioxide, or the like.

Similarly, second position holder structure 104b may be formed over second semiconductor region 107b, which in some embodiments may represent a channel region of a channel region of a second transistor element. In addition, the doped regions 106b may be formed adjacent to the second semiconductor region 107b to define the drain and source regions and the channel region of the specified transistor type in certain embodiments. For example, the second semiconductor region 107b surrounded by the doped regions 106b may be positioned subsequent to the first semiconductor region 107a surrounded by the respective doped regions 106a, but the improved It may be separated from them by an isolation structure 103, which may be provided in the form of a trench isolation structure as is typically used in semiconductor devices. When representing a semiconductor structure, regions 107b and 106b may be of the same type as regions 107a and 106a or may represent other types of transistors, such as P-type or P-channel transistors. However, the first and second semiconductor regions 107a and 107b are located at very different locations within the same die region and require circuitry to receive strains of different types or sizes to provide different electrical characteristics. Can represent elements. Similarly, regions 107a and 107b may represent different circuit elements or even different die portions located in different substrate regions, such as a central region and a peripheral region, and the first and second semiconductor regions. Strain techniques for 107a and 107b may provide more uniform electrical properties for semiconductor devices fabricated on the central and peripheral regions of the substrate 101. With respect to the second position holder 104b and the sidewall spacers 105b formed on the sidewalls, the same criteria apply as for the corresponding elements 104a and 105a.

A typical process flow for forming semiconductor device 101 as shown in FIG. 1A may include the following processes. After forming or receiving the substrate 101 comprising the semiconductor layer 102, implant sequences establish a vertical dopant profile specified within the first and second semiconductor regions 107a, 107b. To be performed. Thereafter, the first and second position holders 104a and 104b may be formed by well-established deposition, photolithography and etching techniques, where the first and second position holders 104a and 104b are formed. ) (Ie, the horizontal dimension (or gate length dimension) of these elements in FIG. 1A) can be adapted to design the requirements, and will be approximately 100 nm (much smaller for very improved integrated circuits). Can be. Thereafter, dopant species may be introduced to form doped regions 106a and 106b therein. Depending on the device requirements, the device 100 may be masked correspondingly, for example by a photoresist mask, to form the regions 106a and 106b separately with the desired type of dopant material. During these implants, the position holders 104a and 104b act as implant masks to substantially avoid dopant intrusion into the respective semiconductor regions 107a and 107b. Thereafter, the sidewall spacers 105a and 105b may be formed by anisotropically etching the material layer while depositing a corresponding material layer. Typically, a liner material may be deposited before the spacer material so that when the semiconductor layer 102 is exposed to an anisotropic etching atmosphere, the surface is not excessively damaged. For convenience, the corresponding liner is not shown in FIG. 1A. Subsequently, an additional implantation process may be carried out, possibly based on an additional photoresist mask, where the first and second position holders 104a, 104b also combine with the respective sidewall spacers 105a, 105b. ) Acts as an injection mask to obtain the desired transverse dopant profile in each of the doped regions 106a and 106b. Corresponding anneal cycles may then be performed to activate the dopants in regions 106a and 106b as well as to recrystallize the damaged crystal portions. Alternatively, the corresponding anneal processes may be performed after one or more of the aforementioned implants.

In some examples where a very sophisticated transverse dopant profile is required, additional sidewall spacers (not shown) may be formed following an additional implantation step to obtain a more complex dopant profile in regions 106a and 106b. . Subsequently, in certain embodiments, sidewall spacers 105a and 105b may be removed by a selective etching process based on well-established process recipes. For example, the spacers 105a and 105b made of silicon nitride may be selectively removed by hot phosphoric acid. In other examples, spacers 105a and 105b may be removed by a plasma etching process, in some embodiments, a liner (not shown) typically used as an etch stop layer may be maintained during an injection cycle, It can be used as an etch stop layer during removal of the spacers 105a and 105b. In other embodiments, the spacers 105a, 105b may be maintained during further processing of the device 100.

1B schematically illustrates the device 100 in an improved manufacturing stage. Here, device 100 includes a dielectric layer 108 having a specified inherent stress, which is formed to be surrounded by first and second position holders 104a and 104b. The term “intrinsic stress” is understood to specify a certain type of stress (ie, tensile or compressive stress), or any change therein (ie, magnitude of stress as well as orientation-dependent tensile or compressive stress). Thus, in one embodiment, dielectric layer 108 may have an intrinsic tensile stress having a magnitude of approximately 0.1 to 1.0 GPa (Giga-Pascals). Dielectric layer 108 may be comprised of any suitable material, such as silicon nitride. In one exemplary embodiment, the device 100 further includes a conformal etch stop layer 109 having a different material structure compared to the dielectric layer 108 and having a much smaller thickness as compared to the dielectric layer 108. can do. For example, the etch stop layer 109 may be made of silicon dioxide.

The etch stop layer 109 may be formed by well-established plasma enhanced chemical vapor deposition (PECVD) techniques based on precursor materials such as TEOS or silane, if provided. The dielectric layer 108 may be formed by PECVD techniques based on known process recipes, where the process parameters may be adjusted to achieve the desired intrinsic stress. For example, silicon nitride can be deposited with high compressive or tensile stresses, where the type and magnitude of stress is used to control deposition temperature, deposition pressure, tool configuration, and ion bombardment during the deposition process. It can be easily adjusted by adjusting process parameters such as bias power, plasma power and the like. For example, during silicon nitride deposition, increased ion bombardment (ie, increased bias power) promotes the generation of compressive stress when the remaining parameters are the same. In some specific embodiments, after deposition of dielectric layer 108, the resulting topography may be planarized, for example, by chemical mechanical polishing (CMP) according to well-established process recipes. Thereby, excess material in the dielectric layer 108 may be removed to a specified degree to substantially reach a planar surface, or in some exemplary embodiments, material removal may be in first and second positions. It may continue until the top surfaces of the holders 104a and 104b are exposed. However, in other embodiments, additional processing may be performed without planarizing layer 108.

FIG. 1C shows the device 100 in a further improved fabrication stage, where a portion of the layer 108 that was surrounding the second location holder 104 is removed, while the first location holder 104a remains the remaining dielectric layer. It is still embedded at least in the transverse direction by 108 (which is referred to as 108a). Moreover, resist mask 110, if provided, is formed on device 100 to expose a relevant portion of layer 102 including second position holder 104b and etch stop layer 109.

The resist mask 110 may also be formed according to photolithography techniques that may be used in differently doping P-type and N-type transistors, so that corresponding processes are well-established. Thereafter, dielectric layer 108 may be selectively etched by an anisotropic process recipe to finally obtain dielectric layer 108a with the specified inherent stress. During the anisotropic etching process, the etch stop layer 109 may, if provided, prevent damage and / or excessive material removal of exposed portions of the semiconductor layer 102.

1D schematically illustrates a device 100 having a second dielectric layer 111 having a second specified intrinsic stress, which is the dielectric layer portion 108a, the second position holder 104b, and the exposed semiconductor layer ( 102 or etch stop layer 109. The exposed portion of the etch stop layer 109 may be removed prior to deposition of the second dielectric layer 111 when considered to be inadequate due to any damage caused by the preceding anisotropic etching process of the dielectric layer 108. In this case, an additional etch stop layer similar to layer 109 may be deposited, which in turn may also cover dielectric layer portion 108a (shown in dashed lines) and with second position holder 104b. The exposed portions of the semiconductor layer 102 may be covered. For convenience, this etch stop layer portion is still indicated as 109. The provision of the etch stop layer 109 on the semiconductor layer 102 may be beneficial in forming contact openings in subsequent fabrication stages. However, in other embodiments, etch stop layer 109 may be omitted.

The second dielectric layer 111, which may be composed of any suitable material, such as silicon nitride, may be deposited by well-established deposition recipes, where the process parameters are set to provide the desired intrinsic stress according to the device requirements. Controlled. As mentioned above, silicon nitride can be readily deposited based on well-established process recipes having a wide range of compressive and tensile stresses (eg, 1.0 GPa compressive stress to 1.0 GPa tensile stress). In one particular embodiment, the intrinsic stress of the second dielectric layer 111 is designed to add compressive stress to the second semiconductor region 107b, where this region represents the channel region of the P-type transistor. Thereafter, excess material of the dielectric layer 111 and possibly as shown in FIGS. 1C and 1D (when the dielectric layer 108 is flattened or not planarized to a level far above the first position holder 104a). Excess material in the portion 108a of the layer may be removed by a CMP process, thus also planarizing the topography of the device 100.

1E schematically illustrates the device 100 after the above-described process sequence. Thus, device 100 has a layer portion 108 that transversely surrounds first position holder 104a and a second layer portion 111b that transversely surrounds second position holder 104b. Substantially planner topography. As a result, the substantially uniformly acting intrinsic stress of the layer portion 108a (here, which is shown as tensile stress 118a) is characterized by the respective strain in the first semiconductor region 107a and thus the strain (ie In this example, a tensile strain) is generated, which typically increases the electron mobility in this region. Similarly, the layer portion 111b (in this example, illustrated in the form of compressive stress 121b) having a second intrinsic stress that acts substantially uniformly has a corresponding deformation or in the second semiconductor region 107b or A strain (in this example, a compressive strain) is created, thereby increasing the mobility of the holes. Other configurations may be anticipated for producing other strains in the semiconductor regions 107a and 107b. For example, intrinsic stress 118a may be a compressive stress and intrinsic stress 121b may be a tensile stress, or both intrinsic stresses 118a and 121b may be tensile or compressive stress, and vary in magnitude. Can be. In other examples, the intrinsic stress 118a or 121b may be selected to yield substantially zero strain in each semiconductor region, while other semiconductor regions receive strain of the desired size. This configuration can be beneficial in providing P-type transistors and N-type transistors of more uniform electrical characteristics, where the performance of the N-type transistors is not degraded while the mobility of the P-type transistors is increased. Should not.

1F schematically shows the device 100 with the position holders 104a and 104b removed. Furthermore, each gate insulating layer 113a and 113b is formed over the first and second semiconductor regions 107a and 107b, respectively.

Removal of the position holders 104a and 104b may be performed by a selective etching process, which may include a plasma etching process and / or a wet chemical etching process. For example, the position holders 104a, 104b when composed of silicon dioxide or amorphous carbon, relative to the layer portions 108 and 111b when composed of silicon nitride, for example, based on well-established process recipes. And may be easily selectively etched with respect to the material of the first and second semiconductor regions 107a and 107b. For example, the removal process may include a plasma etching process that selectively removes the required amount of the first and second location holders 104a and 104b, with the remainder of these location holders subsequently being regions 107a. , 107b) can be removed by a high isotropic or wet etching process so as not to overly damage it. In other embodiments, additionally or alternatively, damaged surface portions of regions 107a and 107b may be oxidized, for example, by thermal or wet chemical oxidation, wherein the oxidized portion is formed in regions 107a, 107b) can be removed by a highly selective wet chemical etching process, for example based on hydrofluoric acid (HF), without significant damage.

After removal of the position holders 104a and 104b, the gate insulating layers 113a and 113b may be formed by oxidation and / or deposition in accordance with design requirements. For example, gate insulating layers 113a and 113b may be thermally oxidized or wet chemically oxidized according to well-established recipes to obtain a finely adjusted layer thickness as required for improved transistor devices. It can be formed by. By this, the thickness of the gate insulating layer may be in the range of 1.5 to several nanometers. In other embodiments, very thin thermal oxide can be formed, followed by deposition of a suitable dielectric material to achieve the desired final thickness of the gate insulating layers 113a and 113b. The corresponding deposited layer is shown by dashed lines and indicated at 112. Gate insulating layers 113a and 113b may also be formed by only the deposited layer 112. In some exemplary embodiments, prior to the formation of the gate insulating layers 113a, 113b, the initial length 112a of the opening defined by the position holder 104a is much larger for the gate electrode of the desired value to be formed. At this time, a dielectric layer such as layer 112 may be deposited in a very conformal manner and with a precisely defined layer thickness. Subsequently, the material deposited at the bottom of the opening (ie on region 107a) may be removed in an anisotropic etching process similar to that used in typical sidewall spacer techniques. In this way, the gate length of the transistor structures can be fine-adjusted to compensate for variations in photolithography or to extend the resolution of photolithography. Thereafter, each gate insulating layer may be formed as described above.

FIG. 1G schematically illustrates a semiconductor device 100 in which a layer of conductive material 123 is formed over the structure of FIG. 1F. Layer 123 may be composed of doped polysilicon or may comprise a metal or metal compound in embodiments for highly improved semiconductor devices. For example, layer 123 may comprise tungsten, tungsten silicide, aluminum, nickel, copper, or any compounds thereof, and the like. Depending on the type of material used for layer 123, corresponding deposition techniques may be used. For example, polysilicon, aluminum, tungsten, tungsten silicides and the like can be readily deposited based on well-established chemical vapor deposition (CVD) techniques. In other cases, plating methods, such as electroplating or electroless plating, can be used to reliably fill the respective openings over the first and second semiconductor regions 107a and 107b. Thereafter, all excess material of layer 123 may be removed by any suitable technique, such as etching, chemical mechanical polishing, and any combination thereof.

FIG. 1H schematically illustrates a semiconductor device 100 from which excess material of layer 123 has been removed and an additional interlayer insulating film 126 is formed as the top layer of the resulting structure. Thus, device 100 includes a gate electrode structure 124a over a first semiconductor region 107a and a second gate electrode structure 124b over a second semiconductor region 107b, thus providing a first transistor element. 130a and the second transistor element 130b are defined. In addition, as shown in FIG. 1H, the layer portion 108a provides a first intrinsic stress 118a that acts substantially uniformly on the gate electrode structure 124a up to a height 125a, and the second layer portion ( 111b provides a second intrinsic stress 121b that acts substantially uniformly on second gate electrode structure 124b up to its height 125b. As a result, depending on the stresses 118a and 121b, respective strains or strains are achieved in the relevant semiconductor regions or channel regions 107a and 107b. Thus, the charge carrier mobility in these channel regions is individually adjustable by correspondingly controlling the stresses 118a and 121b. In particular, the transistor configuration as shown in FIG. 1H is substantially planar and doped regions 106a and 106b (ie, respective drain and source regions) with respect to the associated gate electrode structures 124a and 124b. Self-aligned formation). In addition, gate electrode structures 124a and 124b may be formed of a highly conductive material, such as a metal, a metal compound, high doped polysilicon, or any combination thereof. In certain embodiments, gate electrode structures 124a and 124b are substantially composed of metal.

2 schematically illustrates a semiconductor device 200 at an intermediate fabrication stage in accordance with further exemplary embodiments of the present invention. In FIG. 2, the same or similar components as shown in FIGS. 1D and 1E are denoted by the same reference signs, except for the preceding “2” instead of “1”. Thus, device 200 includes a substrate 201 having a semiconductor layer 202 formed thereon, the semiconductor layer 202 having first and second semiconductor regions having associated doped regions 206a and 206b. (207a, 207b). Position holders 204a and 204b are embedded transversely in dielectric layer 208 having a specified intrinsic stress. In addition, a resist mask 210 is formed over the dielectric layer 208 to expose such portions of the device associated with the second semiconductor region 207b. Regarding the formation of the device 200 as shown in FIG. 2, reference is made to the detailed description of FIGS. 1A, 1B and 1C.

In addition, device 200 is subjected to ion bombardment 240 to modify the stress characteristics of the layer portion 208b of dielectric layer 208 that is not covered by resist mask 210. For example, heavy inert ions, such as xenon, argon, silicon, and the like, may be implanted in the portion 208b, thereby relaxing at least partially specified intrinsic stress. As a result, the layer portion 208a maintains the specified intrinsic stress, thus creating a specific strain in the first semiconductor region 207a, the corresponding strain of the second semiconductor region 207b being quite different from this. This depends on the degree of relaxation in layer portion 208b. For example, dielectric layer 208 may have been deposited with high compressive stress to greatly improve hole mobility in first semiconductor region 207a, for example, when regions 206a and 207a exhibit a P-type transistor configuration. Can be. By mitigating the initial compressive stress of the layer portion 208b to a certain degree, the amount of reduction in electron mobility in the second semiconductor region 207b (when designed as an N-type channel region) is then adjusted in accordance with design requirements. Can be. As already mentioned above, the first and second semiconductor regions 207a and 207b need not necessarily represent different types of channel regions, but may also represent the same channel regions, for example, with different degrees of operating characteristics or The desired degree for adjusting device uniformity can be achieved by a process technique as shown in FIG. 2.

Further processing of device 200 may also continue as described with reference to device 100 shown in FIGS. 1E-1H.

3A schematically illustrates a semiconductor device 300 in accordance with further exemplary embodiments of the present invention. Device 300 may represent a device similar to that shown in FIG. 1E, such that identical or similar components are denoted by the same reference numerals, except for the preceding “3” instead of “1”. Thus, detailed descriptions of these components are omitted here. In addition, device 300 is subjected to ion implantation 350 to insert photo ion species, such as hydrogen, helium or oxygen, into semiconductor layer 302 or substrate 301. Ion implantation 350 is performed at a high dose and appropriate energy, thereby achieving a high impurity concentration at the desired depth in layer 302 and / or substrate 301. For example, the peak concentration initially injected may be selected to achieve a concentration in the range of approximately 10 ²¹ to 10 ²³ atoms / cm ³ . Typical implant parameters for helium or hydrogen can be approximately 3 to 15 keV, depending on the desired penetration depth with a dose of approximately 5 × 10 ¹⁵ to 2 × 10 ¹⁶ ions per cm ² . Thereafter, the heat treatment is performed for a period of several minutes, such as at temperatures of approximately 350 to 1,000 degrees Celsius (typically at approximately 700 to 950 degrees Celsius), so as to " Bubbles ”or“ voids ”. Since ion implantation 350 is performed through layer portions 308a and 311b (where the position holders 304a and 304b are still present), a substantially uniform depth for the bubbles 351 is achieved. do. Since light inert species are introduced, the stop mechanism during implantation is mainly based on the interaction with crystal electrons, so that the damage and thus the stress relaxation in layers 308a and 311b are negligible. . Because of the bubbles 351, a certain degree of mechanical dissociation of the regions 306a, 307a, 306b, 307b from the remaining layer 302 and / or the substrate 301 can be achieved, so that the layer portions ( The stress transfer from 308a, 311b to the respective regions 307a, 307b is greatly improved. Therefore, the strain technique for the regions 307a and 307b can be greatly improved, and thus the charge carrier mobility and channel conductivity can be improved more efficiently.

In other embodiments, ion implantation 350 may be performed at an initial fabrication stage, such as prior to formation of layer couples 308a and 311b, possibly prior to formation of location holders 304a and 304b. Thus, all mitigating effects (although they can be very small as described above) can be avoided. Bubbles 351 may then be generated during all anneal cycles to activate dopants in regions 306a and 306b.

3B schematically shows a semiconductor device 300, where the position holders 304a, 304b are removed before ion implantation 350. In this case, the implantation energy can be selected to position the photo ion implants in the semiconductor layer 302 without substantially affecting the regions 306a and 306b. Thus, the semiconductor regions 307a and 307b can be very efficiently decoupled from the remaining semiconductor layer 302 by the bubbles 351. Thus, the stress transmitted to the regions 307a and 307b also greatly increases. In addition, the bubbles 351 themselves act as a stress source, thus also creating a corresponding strain in the respective regions 307a, 307b. In this way, two efficient strain-inducing mechanisms can be combined.

As a result, the present invention provides a semiconductor device and its formation technique, wherein different semiconductor regions receive different strains while allowing the formation process to form planar transistor architectures comprising highly conductive gate electrodes. can do. To this end, the dielectric layer that transversely surrounds the gate electrode structures of the various transistor elements is locally deformed, so that at least two different strain elements are obtained in each channel region. Thus, complementary transistor pairs can be formed, each transistor having a different strained channel region. Deformation of the strain-induced stress layer can be achieved by removing certain portions of the layer, replacing it with layer portions having other intrinsic stresses, and / or relieving the intrinsic stresses to the desired extent. Moreover, due to the combination of improved stress or strain engineering techniques and processes for in-laid gate electrode structures, very largely conductive gate electrode structures can be achieved, thus even 100 nm and much smaller gate lengths. Provides improved gate and channel conductivity for very large scaled devices with In addition, local stress deformation can advantageously be combined with a mechanism for efficiently decoupling channel regions from adjacent materials, thereby significantly improving the efficiency of stress transfer to each channel region.

The specific embodiments disclosed are merely exemplary, as the invention may be practiced in different but apparent equivalent ways to those skilled in the art having the benefit of the disclosure herein. For example, the disclosed process steps can be performed in a different order. Moreover, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. Accordingly, it is to be understood that the specific embodiments disclosed are modified or modified, and all such changes are within the spirit and scope of the invention. Accordingly, the scope of protection required herein is as set forth in the claims below.

Claims (12)

Forming a first position holder structure (104a) over a first semiconductor region (107a) formed in a semiconductor layer (102) positioned on a substrate (101); Forming a second position holder structure (104b) over a second semiconductor region (107b) formed in said semiconductor layer (102); Depositing a dielectric layer (108) having a specified intrinsic stress on the semiconductor layer (102) so as to surround the first and second position holder structures (104a, 104b); Modifying a portion of the dielectric layer (108) to change the intrinsic stress on the portion of the dielectric layer (108) surrounding the second position holder structure (104b); And Replacing the first and second position holder structures (104a, 104b) with a conductive material. 2. The method of claim 1, further comprising forming doped regions 106a and 106b in the semiconductor layer 102 adjacent to the first and second semiconductor regions 107a and 107b. How to. 3. The method of claim 2, wherein forming the doped regions 106a, 106b comprises introducing at least one dopant species by an implantation process while using the first and second position holder structures as an implantation mask. And comprising a step. 4. The method of claim 3, wherein forming the doped regions 106a, 106b comprises forming at least one sidewall spacer element on sidewalls of each of the first and second position holder structures, as well as the at least one. Using one sidewall spacer as an implantation mask during at least one step of the ion implantation process. 6. The method of claim 5, further comprising removing the at least one sidewall spacer prior to depositing the dielectric layer (108). The method of claim 1, wherein deforming the portion surrounding the second position holder (104b) comprises removing the portion. 8. The method of claim 7, further comprising depositing a second dielectric layer 126 over the semiconductor layer 102, wherein the second dielectric layer 126 is a second intrinsic different from the intrinsic stress of the dielectric layer 108. And having a stress. 9. The method of claim 8, further comprising removing material of the second dielectric layer (126) to expose the top surface of the second position holder structure (104b). 8. The method of claim 7, further comprising planarizing the surface of the second dielectric layer (126) prior to removing the portion surrounding the second position holder structure (104b). The method of claim 1, wherein deforming the portion surrounding the second position holder structure (104b) includes selectively relieving the intrinsic stress of the portion. 11. The method of claim 10, wherein said intrinsic stress is selectively relaxed by ion bombardment to said portion. The method of claim 1, wherein the voids caused by the inert species are injected while injecting the inert species into a region adjacent to at least one of the first semiconductor region 107a and the second semiconductor region 107b. Further comprising heat treating the substrate to form a substrate.

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