KR101229526B1 - Technique for forming a contact insulation layer with enhanced stress transfer efficiency - Google Patents

Abstract

Prior to the formation of the metal silicide, high compatibility with conventional processes is obtained by removing the outer spacer 109 used to form highly complex side dopant profiles. At the same time, the contact liner layer 115 can be located closer to the channel region, thereby implementing a highly efficient stress transfer mechanism to create the corresponding strain within the channel region.

Description

TECHNIQUE FOR FORMING A CONTACT INSULATION LAYER WITH ENHANCED STRESS TRANSFER EFFICIENCY}

The present invention generally relates to the formation of integrated circuits (ICs). More specifically, it relates to the formation of a contact insulating layer in the presence of spacer elements in the manufacture of field effect transistors (FETs).

IC fabrication requires the formation of a large number of circuit elements on a given chip area, depending on the particular circuit layout. In general, a number of process technologies are currently being implemented, and for complex circuits such as microprocessors, storage chips, etc., CMOS technology is currently the most promising approach due to its superior characteristics in terms of operating speed and / or power consumption. . During fabrication of a composite IC using CMOS technology, a myriad of complementary transistors, namely N-channel transistors and P-channel transistors, are formed on a substrate comprising a crystalline semiconductor layer. Regardless of whether the transistor is an N-channel transistor or a P-channel transistor, the MOS transistor is formed by the interface of the heavily doped drain and source regions and the reversely doped channel region disposed between the drain region and the source region. So-called PN junctions formed.

Conductivity of the channel region, ie drive current capacity of the conducting channel, is controlled by a gate electrode formed over the channel region and separated by a thin insulating layer. In the formation of the conduction channel due to the application of the appropriate control voltage to the gate electrode, the conductivity of the channel region is determined by the dopant concentration, the mobility of the majority charge carriers, and the predetermined expansion of the channel region in the transistor width direction. This depends on the distance between the source and drain regions, also referred to as the channel length. Thus, in combination with the ability to rapidly create a conduction channel under the insulating layer upon application of a control voltage to the gate electrode, the conductivity of the channel region substantially determines the performance of the MOS transistor. Thus, the reduction in channel length and associated reduction in channel resistivity makes channel length a major design criterion for increasing the operating speed of the IC.

However, the reduction of the transistor dimension involves a number of issues related to the transistor dimension that must be addressed in order to ensure that the benefits resulting from the continuous reduction in the channel length of the MOS transistors are not unfairly offset. One major problem in this regard is the development of advanced photolithography and etching strategies for reliably and reproducibly creating critical dimension circuit elements such as gate electrodes of transistors for new device generation. Furthermore, highly sophisticated dopant profiles are needed in the drain and source regions in the vertical as well as lateral directions to provide low sheet and contact resistivity in combination with the desired channel controllability. In addition, the vertical position of the PN junctions relative to the gate insulating layer is also a major design criterion in terms of leakage current control. Thus, reducing the channel length also requires reducing the depth of the drain and source regions for the interface formed by the gate insulating layer and the channel region, thus requiring sophisticated implantation techniques. According to another approach, epitaxially grown regions are formed at a specific offset relative to the gate electrode (these regions are called raised drain and source regions), thus improving conductivity. While providing a protruding drain and source regions of a while maintaining a shallow PN junction with respect to the gate insulating layer.

Regardless of the technical approach used, in producing highly complex dopant profiles and forming metal silicide regions in the drain and source regions and gate electrodes in a self-aligned manner Sophisticated spacer technology is essential to act as a mask. Since the critical dimension, ie the continuous reduction in the transistor gate length, requires the adaptation of the process techniques associated with the above identified process steps and possibly new development, the charge carriers in the channel region for a given channel length It has been proposed to improve device performance of transistor elements by increasing mobility. In principle, at least two or more mechanisms can be used together or separately to increase the charge carrier mobility of the channel region. First, by reducing the dopant concentration in the channel region, it is possible to reduce scattering events and thus increase conductivity for charge carriers. However, the reduction of the dopant concentration in the channel region has a significant effect on the threshold voltage of the transistor device, so the method of reducing the dopant concentration becomes less attractive unless other mechanisms are developed to adjust the desired threshold voltage.

Second, the lattice structure in the channel region can be deformed, for example, by creating a tensile strain or a compressive strain, which modifies the mobility for electrons and holes. . For example, the generation of tensile strain in the channel region increases the mobility of the electrons. Depending on the size of the tensile strain, the mobility can be increased by 20%, which directly leads to an increase in conductivity. On the other hand, compressive stress in the channel region increases the mobility of the holes, thereby providing a possibility for improving the performance of the P-type transistors.

As a result, it has been proposed to introduce, for example, a silicon / carbon layer or a silicon / germanium layer in or below the channel region to create tensile or compressive stress. The introduction of stress generating layers in or below the channel region can significantly improve transistor performance, but significant effort is required to implement the formation of such stress layers with conventional proven CMOS techniques. For example, additional epitaxial growth techniques must be developed and implemented to be included in the process flow to form germanium-containing or carbon-containing stress layers at appropriate locations in or below the channel region. Thus, the process becomes quite complicated, thereby increasing the production cost and increasing the possibility of decreasing the production yield.

Another promising way is to create stress in the insulating layer, which is formed after the formation of the transistor elements to bury the transistors and accepts metal contacts that provide electrical connection of the transistors to the gate electrode and drain / source regions. . Typically, such insulating layers include at least one etch stop layer or liner and additional dielectric layers that can be selectively etched against the etch stop layer or liner. In the following, this insulating layer will be referred to as a contact layer and the etch stop layer will be referred to as a contact liner layer. In order to obtain an efficient stress transfer mechanism into the channel region of the transistor to create strain, the contact liner layer located in the vicinity of the channel region should be located close to the channel region. However, in advanced transistor structures that require a triple spacer scheme to achieve a highly complex lateral dopant profile, conventional triple spacer schemes are epitaxially grown since a significant amount of stress in the contact liner layer is "absorbed" by the spacers. Despite the advantages in process complexity over stress layers, it is currently a relatively unattractive way to create strain in the channel regions of advanced transistors.

In view of the foregoing, there is a need for an improved technique that enables stress generation in the channel region without the need for complex and expensive epitaxial growth techniques.

A schematic summary of the invention is described below for a basic understanding of some aspects of the invention. This summary is not an exhaustive description of the invention, nor is it intended to identify key or critical elements of the invention or to delineate the scope of the invention. It is intended to illustrate some concepts of schematic form as a prelude to the more detailed description that is presented later.

In general, the present invention provides for the formation of a contact liner layer in the vicinity of the channel regions of each transistor element, i.e. the formation of an etch stop layer of a dielectric layer stack used to bury transistor elements to form electrical contacts through the layer. It is about the technology that makes this possible. Thus, the contact liner layer can be formed or handled to exhibit a specific internal stress so that the specific internal stress can be transferred very efficiently to the channel region to create a strain corresponding to the channel region, thereby allowing charge carrier mobility and hence transistors. It may offer the possibility to improve the overall performance of the devices.

The method according to an embodiment of the present invention includes forming a transistor device comprising a gate electrode structure comprising at least one internal spacer device and an external spacer device. The outer spacer device is then removed and a contact liner layer is formed over the transistor device.

A method according to another embodiment of the present invention includes forming a first transistor element having a first gate electrode structure comprising at least one inner spacer element and an outer spacer element. Furthermore, a second transistor element is formed, which has a second gate electrode structure comprising at least one inner spacer element and an outer spacer element. The method further includes removing external spacers of the first gate electrode structure and the second gate electrode structure. In addition, a first contact liner layer having a first internal stress is formed over the first transistor element and a second contact liner layer having a second internal stress is formed over the second transistor element.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention may be understood with reference to the accompanying drawings, in which like reference numerals indicate like elements.

1A-1E schematically illustrate cross-sectional views of transistor devices during various fabrication steps in forming a contact liner layer close to a channel region in accordance with one embodiment.

2 schematically illustrates a cross-sectional view of a semiconductor device including two transistor elements having different internal stresses in respective portions of the contact liner layer and receiving the contact liner layer close to each channel region, according to one embodiment. .

While the invention is susceptible to various modifications and alternative forms, specific embodiments of the invention are shown by way of example in the drawings and are described in detail herein. However, the description of specific embodiments is not intended to limit the invention to the particular forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the claims. Put it.

Hereinafter, embodiments of the present invention will be described. For clarity, not all features of an actual implementation are described in this specification. Of course, in developing any such practical embodiments, numerous implementation specific decisions must be made to achieve the specific goals of the developer, which may vary from implementation to implementation, such as complying with system related and business related constraints. In addition, such development efforts can be complex and time consuming but will be routine to those skilled in the art who benefit from the present invention.

The invention is now described with reference to the accompanying drawings. Various structures, systems and devices in the drawings are schematically depicted so as not to obscure the invention for purposes of explanation only and to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present invention. The terms and phrases used herein should be understood to be understood as understood by one of ordinary skill in the art. It is to be understood that the consistent use of the term or phrase herein does not imply any particular definition of the term or phrase, that is, a definition different from the general and customary meanings understood by those skilled in the art. If a term or phrase has a special meaning, that is, a meaning other than what is understood by one of ordinary skill in the art, it will be expressly set forth herein in a definite manner that directly and explicitly provides a particular definition for the term or phrase.

In general, the present invention solves the problem of efficiently transferring stress from the contact liner layer to the channel region while maintaining high compatibility with conventional processes. For this purpose, spacer elements are provided that have the size required by implantation and silicide requirements to take into account high diffusivity implant species such as boron and phosphorus. On the other hand, however, the effective distance from the drain and source regions can be significantly reduced in that the outermost spacer is removed prior to the formation of the contact liner layer. As such, the removal process for the outermost spacer element can be designed so as not to adversely affect any silicide regions formed on the gate electrodes and the drain and source regions. Further embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

1A-1E illustrate cross-sectional views of semiconductor device 100. The semiconductor device 100 includes a substrate 101, which may be any substrate suitable for the formation of circuit elements of an IC. For example, substrate 101 may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or any other suitable substrate on which a crystalline semiconductor layer suitable for forming transistor devices is formed. Formed into and on the substrate 101 is a transistor element 150 in an intermediate fabrication step, in which the transistor element 150 includes a gate electrode 102 formed on the gate insulating layer 103 and Gate insulating layer 103 separates gate electrode 102 from channel region 104, which may be a portion of substrate 101 or a portion of any suitable semiconductor layer formed on substrate 101. As can be seen in silicon-based highly complex ICs such as CPUs, memory chips, ASICs (on-demand semiconductor integrated circuits) and the like, transistor device 150 has a gate length of 100 nm or less (ie, the gate electrode of FIG. 1A). Any type of field effect transistor, such as an N-channel transistor or a P-channel transistor). As a result, the gate insulating layer 103 may have an appropriate thickness in the range of about 1.2 nm or less to several nm, depending on the overall dimensions of the gate electrode 102. Although the present invention is very advantageous when combined with very small transistor devices having a gate length of about 100 nm or less than 50 nm, it is found that the invention can be easily applied to less sophisticated transistor devices in principle.

The semiconductor device 100 further includes an offset spacer 105 formed on the sidewalls of the gate electrode 102. The offset spacer 105 may be composed of any suitable dielectric material, such as silicon dioxide, silicon nitride, silicon oxynitride, or the like. The width of the offset spacer 105 is selected in accordance with the process requirements for forming the horizontal dopant profile of the extension region 106 formed in the substrate 101 adjacent the channel region 104. The semiconductor device 100 may further include an internal spacer element 107 formed adjacent the sidewalls of the gate electrode 102. The inner spacer element 107 may be separated from the offset spacer 105 by a liner 108, the liner 108 having a moderately high etch selectivity with respect to the material of the inner spacer 107. Consists of matter. In one embodiment, the inner spacer 107 may be made of silicon nitride and the liner 108 formed on the horizontal portions of the substrate 101 and over the gate electrode 102 may be made of silicon dioxide. Can be. For this material composition, a number of established anisotropic etch recipes with high etch selectivity are known. In other embodiments, the inner spacer 107 may be comprised of silicon dioxide or silicon oxynitride, while the liner 108 is silicon nitride to exhibit a reasonably high etch selectivity for established anisotropic etching techniques. It can be configured as. Device 100 has an outer spacer element 109 having a width selected to meet process requirements for an ion implantation process that is subsequently performed to form deep drain and source regions adjacent to extension regions 106. It includes more. The outer spacer element 109 is separated from the inner spacer 107 by the etch stop layer 110, which also covers the horizontal portions of the liner 108 and is resistant to the material of the outer spacer 109. It is composed of a material that exhibits a moderately high etch selectivity. In one embodiment, the outer spacers 109 may be composed of silicon dioxide, while the etch stop layer 110 may be composed of silicon nitride. In one embodiment, different material compositions may be provided for the outer spacer 109 and the etch stop layer 110 as long as the required etch selectivity between the two materials is maintained. For example, in one embodiment, the outer spacers 109 may be comprised of silicon nitride, while the etch stop layer 110 may be comprised of silicon dioxide.

As shown in FIG. 1A, a typical process flow for forming semiconductor device 100 may include the following processes. For example, an appropriate gate insulating material layer and gate electrode material are formed in the form of silicon dioxide, or nitrogen-enriched silicon dioxide for the gate insulating layer 104 and for the gate electrode 102. After forming in the form of pre-doped or undoped polysilicon, an established patterning process can be performed based on advanced photolithography and etching techniques. After patterning the gate insulating layer 104 and the gate electrode 102, an appropriate dielectric material, such as silicon dioxide, silicon nitride, or the like, is deposited to a predetermined thickness substantially corresponding to the width of the offset spacer 105 to form an offset spacer ( 105 may be formed. Thereafter, a suitable anisotropic etching process may be performed to remove excess material on the top surface of the gate electrode 102 and the horizontal portions of the device 100, such as the exposed portions of the substrate 101. Thereafter, an ion implantation process may be performed to form a portion of the extended regions 106, and the implant conditions and dopants required for the formation of the extended regions 106 and the deep drain and source regions, as described below. Other implant cycles may be performed to form pre-amorphized regions (not shown) and / or halo regions (not shown) in the substrate 101 to obtain a profile. Thereafter, the liner 108 may be formed by depositing a suitable material, which may be silicon dioxide, which may be deposited based on the plasma enhanced chemical vapor deposition (PECVD) technique established in one embodiment. In other embodiments, the liner 108 may be deposited in the form of silicon nitride. Subsequently, spacer material for the inner spacer 107 may be deposited by PECVD techniques, while the material composition of the liner 108 to the inner spacer 107 may be selected to exhibit a high etch selectivity. In one embodiment, the inner spacer material 107 may comprise silicon nitride, where the liner 108 may consist substantially of silicon dioxide. In other embodiments, the inner spacer material 107 may be comprised of silicon oxynitride or silicon dioxide, and the liner 108 may be formed of silicon nitride.

Thereafter, established anisotropic etching techniques can be used to remove excess material of the spacer material, thereby forming the inner spacer 107. The anisotropic etching process, on the other hand, stops reliably on or in liner 108. Thereafter, an additional suitable implantation process may be performed in accordance with device requirements to fine tune the lateral dopant profile of extension regions 106. Next, in one embodiment the etch stop layer 110 may be conformally deposited in the form of a silicon nitride layer, and then in this embodiment silicon diox to form the outer spacer element 109. A spacer material consisting of seeds can be deposited and anisotropically etched. Corresponding anisotropic etching recipes are established in the art. In other embodiments, etch stop layer 110 may be deposited as a silicon dioxide layer, while outer spacers 109 may be formed from a silicon nitride layer.

1B schematically illustrates a semiconductor device 100 at a more advanced stage of fabrication. As shown, a portion of the etch stop layer 110 formed on the exposed horizontal portions of the gate electrode 102 and the substrate 101 (FIG. 1A) is removed. The remainder of the etch stop layer 110 is now labeled 110a. Further, deep source and drain regions 111 are formed next to the extension regions 106.

The device 100 shown in FIG. 1B may be formed by an etching step, which is designed as a substantially anisotropic etching process to selectively remove exposed portions of the etch stop layer 110 in certain embodiments. Can be. As such, established selective etching recipes can be used and the etching process can reliably stop in and on the liner 108. In this case, the etch stop layer 110 and the liner 108 are formed of different materials exhibiting a certain degree of etching selectivity. Due to this etching process for removing exposed horizontal portions of the etch stop layer 110, as indicated by 110b, the lateral expansion of the etch stop layer 110a substantially reduces the width of the outer spacer element 109. It is decided to correspond. Furthermore, during subsequent implantation to form the deep drain and source regions 111 and to further dope the gate electrode 102, the corresponding stack of layers comprising layers 110 and 108 in FIG. Facilitate control of the ion implantation process to form / drain regions 111. After implantation, rapid heat to activate dopants in extension regions 106 and deep drain / source regions 111 and to recrystallize crystalline damage caused by previous pre-crystallization and other implant processes. A rapid thermal anneal process can be performed.

1C schematically illustrates a semiconductor device 200 according to an alternative embodiment for forming deep source / drain regions 111 and determining lateral extension 110b of the etch stop layer 110a. In FIG. 1C, the etching process for forming etch stop layer 110a is configured such that exposed horizontal portions of liner 108 are also removed to form residual portion 108a. Thus, the etching process is designed to reliably stop on the semiconductor material of the substrate 101, and in certain embodiments of the present invention the semiconductor material of the substrate is substantially comprised of silicon. As a result, the corresponding regions of gate electrode 102 and substrate 101 are exposed during subsequent implantation processes to form deep drain / source regions 111. Thereafter, a rapid heat treatment process may be performed as described with reference to FIG. 1B.

In highly advanced transistor devices, the conductivity of the heavily doped regions such as gate electrode 102 and the contact regions of deep drain / source regions 111 are usually increased by providing a metal compound on top of these regions. . This is because the metal silicon compound may have higher conductivity as compared to the heavily doped silicon material. For example, titanium, cobalt and nickel are typically provided in highly advanced devices to form corresponding metal silicide regions of reduced resistivity. Prior to the deposition of any suitable metal, such as nickel, the surface portions must be exposed when initially starting from the semiconductor device 100 as shown in FIG. 1B, and / or the surface under consideration as shown in FIG. 1C. Surface contamination can be removed when the parts are already substantially exposed. In embodiments in which the liner 108 consists substantially of silicon dioxide, the corresponding etching process for exposing associated surface portions and / or removing contaminants (especially oxide residues) may be performed by etching etch stop layer 110a. As well as highly selective etching chemicals that do not substantially affect the substrate 101 and the gate electrode 102. For example, diluted fluoric acid (HF) may be used to selectively remove oxides and oxide residues to silicon and silicon nitride.

1D schematically illustrates the semiconductor device 100 after a corresponding etching process for selectively removing surface contaminants and / or exposing respective surface portions. Furthermore, in one particular embodiment, this highly selective etching process is also used to substantially completely remove the outer spacer element 109. As shown, semiconductor device 100 includes a liner 108a, which is further reduced by the corresponding etching process to produce liner 108b. Further, in some examples, an under-etch region that is contoured by the etch stop layer 110a may be formed due to the isotropic nature of the etching process. Similarly, the upper sidewall portions 102a of the gate electrode 102 may be exposed during the extended etching process, in which case the offset spacers 105 are made of substantially the same material as the liner 108b. Offset spacers 105 may also be reduced if configured. The correspondingly reduced offset spacer is now indicated as 105a. In other embodiments, liner 108 and outer spacers 109 may be composed of dielectric materials other than silicon dioxide, such as silicon nitride, while etch stop layer 110a may be comprised of silicon dioxide. have. In this case, substantially the same process flow may be used with suitable etching chemicals, such as hot phosphoric acid, to remove the outer spacers 109 and expose the intended surface portions.

Thereafter, a suitable metal may be deposited by sputter deposition based on established recipes. For example, cobalt, titanium, nickel or other refractory metals can be deposited based on device requirements. During sputter deposition of metal, which is a reasonably direct deposition technique, portions of each etch stop layer 110a also substantially prevent metal deposition. As a result, except for the exposed top sidewall portions 102a, metal deposition is substantially by the dimensions of the outer spacer element 109, ie by the side dimensions 110b, although the outer spacer element 109 is removed. Locally substantially limited to the area determined by. During subsequent heat treatment to initiate a chemical reaction between the deposited metal and silicon, the metal silicide is preferably the upper sidewall portions 102a and the top surface of the gate electrode 102 and the exposed surface of the substrate 101. Formed on exposed silicon portions, such as portions.

As would be the case if the outer spacers 109 were still present, the formation of the metal silicide in the drain / source region 111 was caused by the lateral extension 110b of the etch stop layer 110a even though an underetch region could have been created. Substantially determined since metal penetration in this case can be significantly impeded and metal diffusion towards channel region 104 can also be significantly reduced. As a result, the formation of the metal silicide is limited to the portions of the drain / source regions 111 initially defined by the outer spacer 109 (FIGS. 1B and 1C) and at the same time a contact liner formed after the metal silicide formation The material of the layer can be close to the channel region 104, thereby significantly improving the stress transfer mechanism for creating the desired strain within the channel region 104.

1E schematically illustrates the semiconductor device 100 after the above-described process. Thus, device 100 includes metal silicide regions 113 in drain / source regions 111, the location and dimensions of which are defined by an outer spacer 109, ie etch stop layer 110a and its Substantially defined by the lateral extension 110b. In addition, a corresponding metal silicide region 114 is formed on top of the gate electrode 102, and an increased surface area where a reduced offset spacer 105a (FIG. 1D) can be used for conversion of silicon to metal silicide, That is, providing the upper sidewall portions 102a allows more of the gate electrode 102 to be converted to a highly conductive material. The device 100 also includes a contact liner layer 115 formed on the transistor element 150, which may be comprised of, for example, silicon nitride and may have a specific internal stress. have. As is well known, deposition parameters such as pressure, temperature, bias voltage, etc. to obtain specific internal stresses ranging from tensile stress of about 1 GPa (giga pascal) to compressive stress of about 1 GPa during the PECVD process for depositing silicon nitride. Can be selected. As a result, the corresponding internal stress can be selected to efficiently produce the corresponding strain in the channel region 104, which can eventually lead to improved transistor operation. In addition, since the process parameters of the PECVD process can be selected to obtain a highly non-directional deposition operation, any underetch regions that may have been formed also within the dielectric material surrounding the transistor element 150. It can be at least partially filled to substantially prevent any voids.

As a result, the relevant portions of the contact liner layer 115 are closer to the channel region 104 by removing the outer spacers 109, which can usually be performed during the precleaning process required prior to the formation of the metal silicide. This can significantly improve stress transfer and thus increase charge carrier mobility. At the same time, a high degree of compatibility with conventional process techniques is maintained without negatively affecting the formation of the highly complex side dopant profile of the extended region 106 and the drain / source regions 111. In addition, the increased surface area of the gate electrode 102, i.e., the upper sidewall portions 102a, which are exposed during the removal of the outer spacer 109, provides improved electrode conductivity, which may improve performance of the transistor 150. It can also contribute.

2 schematically illustrates a cross-sectional view of a semiconductor device 200 in accordance with a further exemplary embodiment of the present invention. The semiconductor device 200 may include a first transistor element 250 and a second transistor element 260 formed on the substrate 201. Regarding the configuration of the substrate 201, the same criteria as described above with reference to the substrate 101 apply. In addition, the first and second transistor elements 250 and 260 may include substantially the same components as described above with reference to FIG. 1E. That is, the first and second transistor elements 250 and 260 may include a gate electrode structure including the gate electrode 202, and are separated from the inner spacer 207 by a liner 208b over the gate electrode structure. Offset spacers 205a are formed. The corresponding etch stop layer 210a may be formed on the inner spacer 207. Although "outer" spacer elements are no longer provided at this stage of manufacture, for consistency, the spacers 207 of the first and second transistor elements 250 and 260 may be referred to as "inner" spacer elements. will be. In addition, the first and second transistor elements 250 and 260 may include a channel region 204, and the channel region 204 is separated from the gate electrode 202 by the gate insulating layer 203. An extended region 206 and deep source / drain regions 211 may be provided, with each metal silicide region, such as nickel silicide regions 213, formed in deep drain / source regions 211. The corresponding metal silicide region 214 may be formed on top of the gate electrode 202. The first and second transistor elements 250, 260 may each other in the type of dopants used to form the corresponding extension regions 206, source / drain regions 211, and channel regions 204. For example, the first transistor 250 may be an N-channel transistor, while the second transistor 260 may be a P-channel transistor. In other embodiments, additionally or alternatively, the first and second transistors 250, 260 may differ in other transistor characteristics, such as gate length, thickness of the gate insulating layers 203, and the like. In addition, a contact liner layer 215 is formed on the first and second transistor elements 250, 260. Finally, the first transistor element 250 may be covered by the resist mask 216.

As shown in FIG. 2, a typical process flow for forming semiconductor device 200 may include processes substantially the same as described above with reference to semiconductor device 100, with extended regions 206 and a source. During the formation of the / drain regions 211, and in any of the previously performed implantation procedures to create a suitable vertical dopant profile in each channel regions 204, different types of dopants may be used for the first and second transistors. Appropriate masking steps may be performed to implant into devices 250 and 260. During formation of the device 200, as described above with reference to FIGS. 1D and 1E, external spacer elements may be provided prior to corresponding implantation for the formation of source / drain regions, where the external spacer elements may then and The metal silicide regions 214 and 213 may be removed prior to formation. In addition, the contact liner layer 215 may be formed to have a specific internal stress in accordance with any suitable deposition technique, and the specific internal stress may be appropriately selected to increase the performance of the first transistor device 250. For example, because the tensile strain can increase electron mobility when this transistor element is an N-channel transistor, the internal stress of the contact liner layer 215 may cause channel region 204 of the first transistor element 250. It can be an appropriately sized tensile stress that provides a tensile strain to the. After formation of the contact liner layer 215, the resist mask 216 is formed based on any photolithography masks that may be used to form different types of extension regions 206 and source / drain regions 211. Can be. Thereafter, device 200 may undergo treatment 217, which is designed to form contact liner layer portion 215a over second transistor element 260, wherein contact liner layer portion 215a may be removed. The internal stress is different from that of the contact liner layer 215 formed over the one transistor element 250.

In one embodiment, treatment 217 may include an ion implantation process with any suitable ion species, such as xenon, argon, or the like, which may alter the internal structure of the contact liner layer 215 being deposited. It can produce some degree of stress relaxation. For example, tensile stress can have a negative effect on hole mobility in the channel region of a P-channel transistor, and thus, by applying a process 217 to relax the stress, the channel region of the second transistor element 260 ( 204 may be substantially unaffected by the stress generated initially of layer 215. In another embodiment, layer 215 may be formed with inherent compressive stress, for example when first transistor element 250 is a P-channel transistor, and then a second transistor, which may be an N-channel transistor. The compressive stress may be relaxed by the process 217 to prevent or at least reduce the effect of the compressive stress on the channel region 204 of the element 260. Thus, the performance of the P-channel transistor 250 can be improved most efficiently because the stress layer 215 is very close to each channel region 204, while the compressive stress for the N-channel transistor 260 The effect can be adjusted according to the device requirements. In particular, stress relaxation can be controlled by appropriately controlling process 217 to achieve improved symmetry during operation of transistors 250 and 260.

In other embodiments, the process 217 may include removal of the portion 215a by any suitable etching process, after which the portion 215a desires to significantly improve the performance of the second transistor element 260. It can be replaced by an additional contact liner layer with internal stress. As such, an additional contact liner layer may also be deposited over the first transistor element 250, thereby attenuating the effect of the initially deposited contact liner layer 215, but this may be due to the initially deposited contact liner layer ( 215 may be considered when adjusting the inherent stress magnitudes.

As a result, the present invention provides an improved technique for transferring stress from the contact liner layer to the channel region of the transistor elements. Here, the contact liner layer is very close to the channel region by the removal of the outer spacer element used to create the appropriate side dopant profile. In addition, the removal process can be performed prior to the formation of the metal silicide regions so that a high degree of compatibility with conventional process flows can be obtained, while at the same time a precleaning process performed prior to metal deposition is used to remove external spacers. It can also be used advantageously. In addition, the removal process of the outer spacers exposes an increased portion of the gate electrode, further improving the formation of metal silicide in the gate electrode, which can lead to an increase in conductivity of the gate electrode. Removal of the outer spacers is performed in the front end of line (FEoL) in conjunction with the metal silicide precleaning process so that any metallic cross-contamination can be prevented.

The specific embodiments described above are illustrative only, as the present invention may be modified and practiced in different but equivalent ways apparent to those skilled in the art that would benefit from the teachings herein. For example, the above described process steps may be performed in a different order. In addition, the present invention is not limited to the details of the structure or design shown herein except as described in the claims below. Specific embodiments described above may be modified or changed and all such modifications may be considered within the spirit and scope of the present invention. Therefore, matters to be protected in the present specification are set forth in the claims below.

Claims (11)

(a) forming a transistor device including a gate electrode structure including at least one internal spacer device and an external spacer device, and forming the transistor device (i) forming a gate electrode over the channel region, wherein the gate electrode is formed to be separated from the channel region by a gate insulating layer; (Ii) forming the at least one internal spacer element adjacent sidewalls of the gate electrode; (Iii) forming an etch stop layer to separate the at least one inner spacer element and the outer spacer element; (Iii) forming the outer spacer element, and forming the outer spacer element include depositing a layer of spacer material, anisotropically etching the spacer material layer to form the outer spacer element, and forming the outer spacer. Etching the etch stop layer using a device as an etch mask; And (v) forming drain / source regions using the inner spacer element and the outer spacer element as implant masks; (b) removing the external spacer element; (c) after removing the external spacer element, forming a silicide region on the gate electrode and the drain / source regions; And (d) after forming the silicide region, forming a stress contact liner layer over the transistor device. delete delete delete delete The method of claim 1, In the step (ii) of forming the at least one inner spacer element adjacent to sidewalls of the gate electrode, an offset spacer element is further formed between the sidewalls of the gate and the at least one inner spacer element. How to. The method of claim 6, Forming a liner prior to forming the inner spacer element, wherein the liner serves as an etch stop layer during forming the inner spacer element. (a) forming a first transistor element having a first gate electrode structure comprising at least one inner spacer element and an outer spacer element; (b) forming a second transistor element having a second gate electrode structure comprising at least one inner spacer element and an outer spacer element, forming the first transistor element and forming the second transistor element Each step is (i) forming a first gate electrode and a second gate electrode over the channel region, wherein the first gate electrode and the second gate electrode are formed to be separated from the channel region by a gate insulating layer; (Ii) forming the at least one internal spacer element adjacent to sidewalls of each of the first gate electrode and the second gate electrode; (Iii) forming an etch stop layer to separate the at least one inner spacer element and the outer spacer element; And (Iii) forming the outer spacer element, and forming the outer spacer element include depositing a layer of spacer material, anisotropically etching the spacer material layer to form the outer spacer element, and forming the outer spacer. Etching the etch stop layer using a device as an etch mask; (c) removing the external spacer element of each of the first gate electrode structure and the second gate electrode structure; (d) after removing the external spacer element, using the etch stop layer as a mask, on the first gate electrode and the second gate electrode, and each of the first transistor element and the second transistor element Forming a silicide region on the drain / source regions; And (e) after forming the silicide region, forming a first contact liner layer having a first internal stress on the first transistor element and a second contact liner layer having a second internal stress on the second transistor element. Method comprising the steps. 9. The method of claim 8, And wherein the first internal stress and the second internal stress are different from each other. 9. The method of claim 8, Forming the first contact liner layer and the second contact liner layer comprises depositing a contact liner layer having the first internal stress on the first transistor element and the second transistor element, and the second internal stress. Selectively relaxing the contact liner layer formed over the second transistor element to obtain a semiconductor device. 9. The method of claim 8, Forming the first contact liner layer and the second contact liner layer comprises depositing a contact liner layer having the first internal stress on the first transistor element and the second transistor element; Selectively removing a portion of the contact liner layer overly, and depositing an additional contact liner layer having the second internal stress on the first transistor element and the second transistor element. .

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