WO2023125894A1 - Cold-source schottky transistor and preparation process therefor - Google Patents

Abstract

A cold-source Schottky transistor and a preparation process therefor. The cold-source Schottky transistor comprises a substrate (101), a source region, a drain region (4), a channel region (3), a source electrode, a drain electrode and a gate electrode, wherein the source region is arranged on the substrate (101), the source region comprises a first source region (1) and a metal region (2) connected to the first source region (1), and the first source region (1) is a heavily doped region; the drain region (4) is arranged on the substrate (101), the drain region (4) is a heavily doped region, and the doping type of the drain region (4) is opposite to that of the first source region (1); the channel region (3) is arranged on the substrate (101), the channel region (3) is located between the metal region (2) and the drain region (4), and a gate electrode dielectric (5) is arranged on the upper side and/or the lower side of the channel region (3); the source electrode is arranged on the source region; the drain electrode is arranged on the drain region (4); and the gate electrode is arranged on the gate electrode dielectric (5).

Description

Cold Source Schottky Transistor and Its Fabrication Process

Cross References to Related Applications

This application claims the priority of Chinese Patent Application No. 2021116737179 filed on December 31, 2021, entitled "Cold Source Schottky Transistor and Its Manufacturing Process". The entire content of the above application is incorporated by reference into this application in its entirety.

technical field

The invention relates to the technical field of semiconductors, in particular to a cold source Schottky transistor and a preparation process thereof.

Background technique

The miniaturization of metal-oxide-semiconductor field-effect transistors (MOSFETs) under Moore's Law has led to the continuous development of information technology over the past few decades. By reducing the channel length of transistors, switching speeds have become faster, device densities have become higher, and circuits become more powerful and efficient. However, the exponential increase in device performance cannot continue forever as predicted by Moore's Law. Among the problems faced by transistor technology today, power consumption is a prominent issue due to the limitation of reduction in supply voltage. Especially under the limitation of the device principle of MOSFET, no matter what kind of channel material and device structure are used, the limit of the sub-threshold swing (SS) at room temperature is 60mV/dec. This is a physical limitation of existing MOSFET designs, which prevents further reductions in supply voltage and power dissipation of MOSFET devices.

Contents of the invention

The invention provides a cold-source Schottky transistor and its preparation process, which are used to solve the defect that the sub-threshold swing of the MOSFET cannot exceed 60mV/dec in the prior art, so that the power supply voltage and power consumption of the MOSFET device cannot be further reduced.

The invention provides a cold source Schottky transistor, comprising:

Substrate;

a source region disposed on the substrate, the source region comprising a first source region and a metal region connected to the first source region, the first source region being a heavily doped region;

a drain region disposed on the substrate, the drain region is a heavily doped region, and the doping type of the drain region is opposite to that of the first source region;

a channel region, disposed on the substrate, the channel region is located between the metal region and the drain region, and a gate dielectric is provided on the upper side and/or lower side of the channel region;

a source disposed on the source region;

a drain disposed on the drain region;

The gate is arranged on the gate dielectric.

According to a cold source Schottky transistor provided by the present invention, the channel region is an intrinsic region or a lightly doped region.

According to the cold source Schottky transistor provided by the present invention, the first source region is a P-type heavily doped region, and the drain region is an N-type heavily doped region.

According to the cold source Schottky transistor provided by the present invention, the first source region is an N-type heavily doped region, and the drain region is a P-type heavily doped region.

According to a cold source Schottky transistor provided by the present invention, the doping concentration of the first source region is 1e ¹⁹ cm ^-3 -1e ²² cm ^-3 , and the length of the first source region is 20 nm, so The thickness of the first source region is 10 nm.

According to a cold source Schottky transistor provided by the present invention, the doping concentration of the drain region is 1e ¹⁹ cm ^-3 -1e ²² cm ^-3 , and the length of the drain region is 20 nm, and the drain region The thickness is 10nm.

According to a cold source Schottky transistor provided by the present invention, the doping concentration of the channel region is 1e ¹⁵ cm ^-3 , the length of the channel region is 20nm, and the thickness of the channel region is 10nm .

According to a cold source Schottky transistor provided by the present invention, the work function of the metal region is 5.0 eV, the length of the metal region is 10 nm, and the thickness of the metal region is 10 nm.

According to the cold source Schottky transistor provided by the present invention, the material of the first source region, the drain region and the channel region is silicon.

The present invention also provides a preparation process of a cold source Schottky transistor, comprising:

forming a well region on the substrate;

forming a channel region, a source terminal and a drain terminal on the well region;

forming a metal region on the source;

forming a first source region on the source end and forming a drain region on the drain end;

forming a gate dielectric in the channel region;

A gate is formed on the gate dielectric, a source is formed on the metal region and the first source region, and a drain is formed on the drain region.

According to the preparation process of a cold source Schottky transistor provided by the present invention, the formation of a metal region on the source terminal includes:

Form a layer of hard mask on the channel region, source terminal and drain terminal;

providing a patterned layer on the hard mask;

Etching the hard mask with no pattern layer, exposing the source end and part of the channel region;

Generate a metal layer over the entire device surface;

Etching the metal layer to remove the metal layer on the channel region and part of the metal layer at the source end;

The hard mask and the metal layer on the surface of the hard mask are removed.

According to the preparation process of a cold source Schottky transistor provided by the present invention, the formation of the first source region on the source end and the drain region on the drain end includes:

growing silicon carbide epitaxially on the exposed source and drain ends of the well region to form a first source material layer and a drain material layer;

Pre-amorphization implantation doping is performed on the first source region material layer and the drain region material layer to form the first source region and the drain region.

In the cold source Schottky transistor and its preparation process provided by the present invention, the source region of the cold source Schottky transistor is composed of a heavily doped first source region and a metal region, and the metal region is in contact with the channel region, and the metal region is in contact with the channel region. A Schottky barrier is formed between the channel regions. In the case of no gate voltage, because the Schottky barrier is very wide, it is difficult for electrons in the source region to tunnel through the Schottky barrier. The forbidden band filters the electrons injected by the external electrodes, and the thermal current is greatly reduced in the forbidden band energy range of the first source region, so that the corresponding off-state current will be very low. In the case of a certain source-drain bias, in the process of increasing the gate voltage, the Schottky barrier between the channel region and the metal region is lowered, making the Schottky barrier thinner until the low-energy region When the Schottky barrier is thin enough, the tunneling current will increase rapidly, and the electrons in the low-energy region of the source region tunnel through the Schottky barrier, so that the subthreshold swing can be lower than 60mV/dec.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are For some embodiments of the present application, those of ordinary skill in the art can also obtain other drawings based on these drawings without creative effort.

Fig. 1 is the structural representation of the cold source Schottky transistor provided by the present invention;

Fig. 2 is the energy band structure diagram of the cold source Schottky transistor provided by the present invention without applying a bias voltage;

Fig. 3 is the energy band structure diagram of the cold source Schottky transistor under the condition of applying positive bias provided by the present invention;

Fig. 4 is the graph of Id-Vg provided by the present invention;

Fig. 5 is a side view of the device generated in step S1 provided by the present invention;

Fig. 6 is a side view of the device generated in step S2 provided by the present invention;

Fig. 7 is a side view of the device generated in step S3 provided by the present invention;

Fig. 8 is a side view of the device generated in step S4 provided by the present invention;

Fig. 9 is a side view of the device generated in step S5 provided by the present invention;

Fig. 10 is a side view of the device generated in step S6 provided by the present invention;

Fig. 11 is a side view of the device generated in step S7 provided by the present invention;

Fig. 12 is a side view of the device generated in step S8 provided by the present invention;

Fig. 13 is a side view of the device generated in step S9 provided by the present invention;

FIG. 14 and FIG. 15 are respectively a top view and a side view of the device generated in step S10 provided by the present invention;

Fig. 16 is a side view of the device generated in step S11 provided by the present invention;

Fig. 17 is a side view of the device generated in step S12 provided by the present invention;

Fig. 18 is a side view of the device generated in step S13 provided by the present invention;

FIG. 19 and FIG. 20 are respectively a top view and a side view of the device generated in step S14 provided by the present invention;

FIG. 21 and FIG. 22 are respectively a top view and a side view of the device generated in step S15 provided by the present invention;

Figure 23 and Figure 24 are the top view and side view of the device generated in step S16 provided by the present invention, respectively;

Figure 25 and Figure 26 are the top view and side view of the device generated in step S17 provided by the present invention, respectively;

FIG. 27 and FIG. 28 are respectively a top view and a side view of the device generated in step S18 provided by the present invention;

FIG. 29 and FIG. 30 are respectively a top view and a side view of the device generated in step S19 provided by the present invention;

FIG. 31 and FIG. 32 are respectively a top view and a side view of the device generated in step S20 provided by the present invention;

Figure 33 and Figure 34 are respectively the top view and the side view of the device generated in step S21 provided by the present invention;

Figure 35 and Figure 36 are the top view and side view of the device generated in step S22 provided by the present invention, respectively;

Figure 37 and Figure 38 are the top view and side view of the device generated in step S23 provided by the present invention, respectively;

FIG. 39 and FIG. 40 are respectively a top view and a side view of the device generated in step S24 provided by the present invention;

Figure 41 and Figure 42 are the top view and side view of the device generated in step S25 provided by the present invention, respectively;

Figure 43 and Figure 44 are respectively the top view and the side view of the device generated in step S26 provided by the present invention;

Fig. 45 is a side view of the device generated in step S27 provided by the present invention;

Fig. 46 is a side view of the device generated in step S28 provided by the present invention;

Fig. 47 is a side view of the device generated in step S29 provided by the present invention;

FIG. 48 and FIG. 49 are respectively a top view and a side view of the device generated in step S30 provided by the present invention;

Figures 50-52 are respectively the top view, side view and cross-sectional view of the device generated in step S31 provided by the present invention;

53-55 are the top view, side view and cross-sectional view of the device generated in step S32 provided by the present invention;

56-58 are the top view, side view and cross-sectional view of the device generated in step S33 provided by the present invention;

Figure 59 and Figure 60 are respectively a side view and a cross-sectional view of the device generated in step S34 provided by the present invention;

Figure 61 and Figure 62 are respectively a side view and a cross-sectional view of the device generated in step S35 provided by the present invention;

Figure 63 and Figure 64 are respectively a side view and a cross-sectional view of the device generated in step S36 provided by the present invention;

Figure 65-Figure 67 are respectively the top view, side view and cross-sectional view of the device generated in step S37 provided by the present invention;

Fig. 68 is a side view of the device generated in step S38 provided by the present invention;

FIG. 69 and FIG. 70 are respectively a top view and a cross-sectional view of the device generated in step S39 provided by the present invention;

Fig. 71 and Fig. 72 are respectively the top view and the sectional view of the device that step S40 provided by the present invention generates;

FIG. 73 and FIG. 74 are respectively a top view and a cross-sectional view of the device generated in step S41 provided by the present invention;

Fig. 75 is a cross-sectional view of the device generated in step S42 provided by the present invention;

76-78 are respectively the top view, side view and cross-sectional view of the device generated in step S43 provided by the present invention.

Reference signs:

1: first source region; 2: metal region; 3: channel region; 4: drain region; 5: gate dielectric;

101: substrate; 102: shielding oxide layer; 103: well region; 104: pad oxide layer;

105: first silicon nitride; 106: isolation pattern; 107: tetraethyl orthosilicate;

108: fin region; 109: etch barrier layer; 110: amorphous silicon; 111: amorphous carbon;

112: gate pattern; 113: polyoxide; 114: second silicon nitride;

115: cover pattern; 116: second amorphous carbon; 117: pattern layer; 118: metal layer;

119: silicon carbide; 120: silicon oxide; 121: third silicon nitride;

122: first phosphosilicate glass; 123: bottom interface layer; 124: dielectric;

125: TiAi-based alloy; 126: the first metal tungsten; 127: the second phosphosilicate glass;

128: source-drain contact pattern; 129: second metal tungsten.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the present invention. Obviously, the described embodiments are part of the embodiments of the present invention , but not all examples. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

The cold source Schottky transistor and its manufacturing process of the present invention will be described below with reference to FIGS. 1 to 78 .

As shown in FIG. 1 , a cold source Schottky transistor provided by the present invention includes a substrate 101 , a source region, a drain region 4 , a channel region 3 , a source electrode, a drain electrode and a gate electrode.

Specifically, the source region, the drain region 4 and the channel region 3 are all arranged on the substrate 101, wherein the source region includes a first source region 1 and a metal region 2, and the metal region 2 is connected to the first source region 1; The channel region 3 is located between the metal region 2 and the drain region 4, and the upper and/or lower sides of the channel region 3 are provided with a gate dielectric 5, the source is arranged on the source region, and the drain is arranged on the drain region 4 , the gate is arranged on the gate dielectric 5, and the first source region 1 is a heavily doped region, and the drain region 4 is a heavily doped region, so that the Fermi level of the first source region 1 and the drain region 4 in the price band. And the doping types of the first source region 1 and the drain region 4 are opposite.

The source region is composed of a heavily doped first source region 1 and a metal region 2, and the metal region 2 is in contact with the channel region 3, a Schottky barrier is formed between the metal region 2 and the channel region 3, and the gate is not applied. In the case of high pressure, because the Schottky barrier is very wide, it is difficult for the electrons in the source region to tunnel through the Schottky barrier, and because the forbidden band of the first source region 1 filters the electrons injected by the external electrode, in the first The thermal current is greatly reduced in the forbidden band energy range of the source region 1, so that the corresponding off-state current will be very low. In the case of a certain source-drain bias, in the process of increasing the gate voltage, the Schottky barrier between the channel region 3 and the metal region 2 is lowered, making the Schottky barrier thinner until When the Schottky barrier in the low-energy region is thin enough, the tunneling current will increase rapidly, and the electrons in the low-energy region of the source region tunnel through the Schottky barrier, so that the subthreshold swing can be lower than 60mV/dec.

It should be noted that when the gate voltage is applied, the electrons in the high-energy region of the Schottky barrier decrease, and no current will be generated in the high-energy region; at this time, the low-energy region of the Schottky barrier becomes narrower, and the electrons in the low-energy region of the source region Tunneling the Schottky barrier, the tunneling current increases rapidly, and the subthreshold swing is lower than 60mV/dec.

Moreover, it should be noted that since the Schottky barrier formed between the metal region 2 and the first source region 1 (heavily doped region) is very thin, it is almost an ohmic contact, so the metal region 2 and the first source region The Schottky barrier between 1 has little effect on the current flow.

Here, the cold source is realized by the junction formed by the first source region 1 and the metal region 2 .

In this way, the cold source Schottky transistor can achieve a relatively large on-state current compared with the tunneling field effect transistor TFETs, and can achieve a higher switching rate than the negative capacitance field effect transistor NC-FETs, and there is no hysteresis; The main body of the device uses silicon as the material. Compared with the traditional MOSFET, the entire device structure has only been modified and adjusted in the source area, that is, the original N (or P) type semiconductor is replaced by a P (or N) type semiconductor + metal (Metal) The structure is highly compatible with existing MOSFETs in terms of materials and processing technology, which increases the potential for practical applications; and, compared with P-Metal-N cold source transistors, this cold source Schottky transistor has no source The effect of electric phonon scattering brought by the N-type part of the region can realize more efficient cold source injection.

In an optional embodiment of the present invention, the channel region 3 can be an intrinsic region or a lightly doped region, so that the Schottky barrier formed between the channel region 3 and the metal region 2 is very wide, and when no gate voltage is applied In the case of , it is difficult for the electrons in the source region to tunnel through the Schottky barrier, thereby reducing the corresponding off-state current.

In an optional embodiment of the present invention, the first source region 1 can be a P-type heavily doped region, and the drain region 4 can be an N-type heavily doped region, or the first source region 1 can be an N-type heavily doped region , the drain region 4 may be a P-type heavily doped region.

Moreover, the doping concentration of the first source region 1 may be 1e ¹⁹ cm ⁻³ to 1e ²² cm ⁻³ , the length of the first source region 1 is 20 nm, and the thickness of the first source region 1 is 10 nm. The doping concentration of the drain region 4 is 1e ¹⁹ cm ^-3 -1e ²² cm ^-3 , the length of the drain region 4 is 20nm, and the thickness of the drain region 4 is 10nm.

Here, the doping concentration of the first source region 1 may be 1e ²¹ cm ^-3 (that is, 1*1021 per cubic centimeter), and the doping concentration of the drain region 4 may be 1e ¹⁹ cm ^-3 , specifically, the first source region The doping concentration of the drain region 1 and the drain region 4 can be determined according to the material of the first source region and the drain region and the material of the substrate, and can be specifically determined according to the actual situation.

In this embodiment, the channel region 3 may be a lightly doped region, and the doping concentration of the channel region 3 is 1e ¹⁵ cm ⁻³ , the length of the channel region 3 is 20 nm, and the thickness of the channel region 3 is 10 nm. Specifically, the channel region 3 may be lightly doped with N-type or lightly P-type according to the work function of the metal region.

In an optional embodiment, the material of the gate dielectric 5 may be hafnium oxide, and the thickness of the gate dielectric 5 may be 1.5 nm. Moreover, the cold source Schottky transistor may include two gates, and the two gates are respectively arranged on the two gate dielectrics 5, so that under the action of the double gates, the gate control capability is effectively improved, and the device can be more efficient. well turned on and off.

In this embodiment, the left end of the first source region 1 is a source contact, the right end of the drain region 4 is a drain contact, and the upper and lower sides of the gate dielectric 5 are gate contacts, wherein the work function of the gate contact can be 4.5 eV.

In some embodiments, the work function of the metal region 2 may be 5eV, the length of the metal region 2 may be 10 nm, and the thickness of the metal region may be 10 nm. Here, the work function, length and thickness of the metal region are not specifically limited, but may be determined according to the actual material selected.

In this embodiment, the first source region 1 and the metal region 2 may be in contact horizontally, and the first source region 1 and the metal region 2 may also be in contact vertically or along other directions (that is, contact at an angle).

In this embodiment, the material of the substrate can be silicon (Si) or germanium (Ge), or a III-V group material, and the first source region can also be silicon (Si) or germanium (Ge), a III-V group material , where III-V materials include: InSb, GaSb, InAs, AlSb, AlAs, GaAs, InGaAs, InAlAs, InP, InGaP, etc.; the material of the metal region can be Au, Co, Cu, Pd, Pt, Ti, W , TiN, NiSi ₂ and so on.

As shown in Figure 2, when no bias voltage is applied, the first source region 1, metal region 2, channel region 3 and drain region 4 have a uniform Fermi level; as shown in Figure 3, when the drain is applied When a voltage of 0.2V is applied to the gate and a voltage of 1V is applied to the gate, the first source region 1, metal region 2, channel region 3 and drain region 4 no longer have a uniform Fermi level, resulting in the formation of electrons and holes. The quasi-Fermi level, the applied forward bias reduces the height of the Schottky barrier, the diffusion movement of the carriers is greater than the drift movement, and the carriers in the source region are injected into the channel region 3 and recombined while diffusing With a certain concentration gradient, the carriers in the channel region 3 are injected into the drain region 4 and diffused while recombining to generate a certain concentration gradient, forming a steady state distribution.

As shown in Figure 4, Figure 4 is the approximate Id-Vg curve obtained by simulation in Sentaurus TCAD, that is, the influence diagram of the gate voltage on the current, and the more bent lines in Figure 4 are the source region including the first A plot of drain current versus gate voltage for a cold-source Schottky transistor with source region 1 and metal region 2; the line with relatively few bends is the source region for a Schottky transistor whose source region includes only metal region 2 A plot of drain current versus gate voltage. Among them, it can be seen from Figure 4 that the subthreshold swing is lower than 60Mv/dec near 0.6V, and the current changes by about 3 orders of magnitude between 0.6V-0.7V, which shows that the tunneling current rapid increase.

It should be noted that due to the presence of Schottky barriers, the drain current is dominated by tunneling current rather than thermal current. At this time, the on-state current is 1 to 2 orders of magnitude lower than that of traditional MOSFETs, but it can be passed Better on-state current characteristics are achieved by adjusting the work function of the gate contact, the work function of the metal at the source end, and the doping concentration of the first source region 1 .

The manufacturing process of the cold source Schottky transistor provided by the present invention is described below, and the manufacturing process of the cold source Schottky transistor described below and the cold source Schottky transistor described above can be referred to in correspondence.

As shown in Figure 5-Figure 78, the preparation process of a cold source Schottky transistor provided by the present invention includes:

forming a well region 103 on the substrate 101;

forming a channel region, a source terminal and a drain terminal on the well region 103;

forming a metal region on the source;

forming a first source region 1 on the source end, and forming a drain region on the drain end;

forming a gate dielectric in the channel region;

A gate is formed on the gate dielectric, a source is formed on the metal region and the first source region 1 and a drain is formed on the drain region.

Wherein, forming the metal region on the source end includes:

As shown in FIG. 31 and FIG. 32, step S20: forming a layer of hard mask on the channel region, source terminal and drain terminal;

As shown in FIG. 33 and FIG. 34, step S21: setting a pattern layer 117 on the hard mask;

As shown in FIG. 35 and FIG. 36 , step S22: etching the hard mask without the pattern layer 117 to expose the source terminal and part of the channel region;

As shown in Figure 37 and Figure 38, step S23: forming a layer of metal layer 118 on the entire device surface;

As shown in FIG. 39 and FIG. 40, step S24: etching the metal layer 118, removing the metal layer on the channel region and part of the metal layer at the source end, leaving a certain thickness of the channel region near the source end. a metal layer to form a metal region;

As shown in FIG. 41 and FIG. 42 , step S25 : removing the hard mask and the metal layer attached to the surface of the hard mask.

Specifically, a layer of second amorphous carbon 116 (Amorphous carbon) is grown on the channel region, the source terminal and the drain terminal as a hard mask, and the surface of the hard mask is polished by chemical mechanical polishing (CMP);

Then, a photoresist pattern layer 117 is provided on the hard mask by a photolithography process to expose the source end and part of the channel region;

Next, remove the second amorphous carbon 116 at the source end and part of the channel region by etching, and then remove the pattern layer 117;

growing a metal layer 118 by physical vapor deposition (PVD);

Etching the metal layer 118, removing the metal layer on the channel region and part of the metal layer at the source end, so that a certain thickness of the metal layer is left on the side of the channel region near the source end to form a metal region;

Finally, the hard mask and the metal layer attached to the surface of the hard mask are removed. Here, the metal layer on the surface of the hard mask refers to the redundant metal layer. When removing the hard mask, the redundant metal layer can be removed simultaneously, and no additional means are needed to remove the redundant metal layer. Therefore, when removing the redundant metal layer , will not affect the metal layer on the wall of the channel region.

In an optional embodiment of the present invention, forming the first source region 1 on the source end and forming the drain region on the drain end includes:

As shown in FIG. 43 and FIG. 44 , step S26: epitaxially grow silicon carbide 119 on the exposed source and drain ends of the well region 103 to form a first source region material layer and a drain region material layer;

As shown in FIG. 45 , step S27 : performing pre-amorphization implantation doping on the first source region material layer and the drain region material layer to form the first source region and the drain region.

Specifically, silicon carbide 119 (SiC) is epitaxially grown in the well region 103 (silicon region) exposed at the source end and the drain end, thereby forming a first source region material layer and a drain region material layer; then the first source region material layer Pre-amorphization and doping PAI (Silicon Pre-Amorphization Implant) is performed on the material layer of the drain region to form a layer of uniform, low-resistance silicon, that is, to form the first source region and the drain region. Alternatively, the first source region material layer and the drain region material layer may be implanted with ions to form a metal silicide to reduce the contact resistance of the first source region and the drain region.

Here, the doping method of the first source region and the drain region is not limited, and may be determined according to actual conditions.

In an optional embodiment of the present invention, forming the well region 103 on the substrate 101 includes:

As shown in Figure 5, step S1: grow a barrier oxide layer 102 on the silicon wafer (substrate 101); here, a barrier oxide layer can be grown on the silicon wafer by thermal oxidation or chemical vapor deposition 102.

As shown in FIG. 6, step S2: perform ion implantation on the silicon wafer by an ion implanter, and form a well region 103 on the silicon wafer;

Here, boron ions can be implanted into the silicon wafer by an ion implanter to form a P-well on the silicon wafer, and the peak of the implanted ion concentration can be controlled to be located in the middle region of the silicon wafer.

Then, as shown in FIG. 7 , step S3 : remove the shielding oxide layer 102 by etching, and then perform rapid annealing on the silicon wafer to repair the crystal lattice of the silicon wafer, thereby activating the well region 103 .

In an optional embodiment, forming a channel region, a source terminal and a drain terminal on the well region 103 includes:

forming shallow trench isolation in the substrate 101;

A channel region, a source terminal and a drain terminal are formed in the substrate 101 .

Specifically, forming shallow trench isolation in the substrate 101 includes:

As shown in FIG. 8, step S4: grow a pad oxide layer 104 (Pad Oxide) on the substrate 101;

Forming a layer of first silicon nitride 105 (Silicon Nitride, SiN) on the pad oxide layer 104 by chemical vapor deposition (CVD);

disposing a photoresist isolation pattern 106 on the first silicon nitride 105 through a photolithography process;

As shown in FIG. 9, step S5: etching the first silicon nitride 105 downward until the pad oxide layer 104 is exposed, and then removing the isolation pattern 106;

As shown in FIG. 10 , step S6: use the first silicon nitride 105 as a hard mask to continue etching downward until the well region 103 is etched to form shallow trenches and fin regions 108 (Fin);

As shown in FIG. 11 , step S7: filling the shallow groove with tetraethyl orthosilicate 107 (TEOS) by means of chemical vapor deposition (CVD);

As shown in FIG. 12 , step S8: grinding the tetraethyl orthosilicate 107 by chemical mechanical polishing (CMP) until the tetraethyl orthosilicate 107 is level with the first silicon nitride 105 in the fin region 108 (Fin) together;

As shown in FIG. 13 , step S9: use hot phosphoric acid solution to remove the remaining first silicon nitride 105, and then use etching to remove part of the orthosilicate around the fin region 108 (Fin), leaving The orthosilicate 107 in the region 103 serves as shallow trench isolation (STI, Shallow Trench Isolation).

Specifically, forming a channel region, a source terminal and a drain terminal in the substrate 101 includes:

As shown in FIG. 14 and FIG. 15 , step S10: growing an oxide layer as an etch stop layer 109 (ESL, etch stop layer) on the fin region 108 (Fin) by means of thermal oxidation;

As shown in FIG. 16, step S11: Deposit a thick layer of amorphous silicon 110 (Amorphous Silicon) by chemical vapor deposition, and smooth the layer of amorphous silicon 110 by chemical mechanical polishing (CMP);

As shown in FIG. 17, step S12: growing a layer of first amorphous carbon 111 as a hard mask;

As shown in FIG. 18 , step S13 : forming a gate pattern 112 on the first amorphous carbon 111 by photolithography; here, a layer of the first amorphous carbon 111 can be grown by chemical vapor deposition or physical vapor deposition.

As shown in FIG. 19 and FIG. 20, step S14: etching the hard mask formed by the first amorphous carbon 111 outside the gate pattern 112, continuing to etch downward the amorphous silicon 110 outside the gate pattern 112, removing the gate pattern 112 and the remaining first amorphous carbon 111;

As shown in FIG. 21 and FIG. 22, step S15: growing a layer of polyoxide 113 on the amorphous silicon 110 by means of thermal oxidation;

As shown in FIG. 23 and FIG. 24, step S16: depositing a layer of second silicon nitride 114;

As shown in FIG. 25 and FIG. 26, step S17: etching the second silicon nitride 114 to form a second silicon nitride 114 spacer on the side walls of the fin region 108 and the amorphous silicon 110 to form a channel region , source area, drain area;

As shown in FIG. 27 and FIG. 28, step S18: forming a masking pattern 115 covering the channel region by photolithography;

As shown in FIG. 29 and FIG. 30 , step S19: remove the exposed fin region 108 (Fin) of the source region and the drain region through spacer etching, and then remove the masking pattern 115 to form a channel region, source and sink.

In this embodiment, forming the gate dielectric in the channel region includes:

As shown in Figure 46, step S28: form a layer of silicon oxide 120 (Silicon Oxide) and a third silicon nitride 121 (Silicon Nitride) on the surface of the channel region, source region, drain region and amorphous silicon 110 as contacts Stop layer for hole etching;

As shown in Figure 47, step S29: deposit a thick first phospho-silicate glass 122 (PSG, Phospho-Silicate Glass) on the surface of the third silicon nitride 121, to serve as pre-metal medium (PMD, pre -Metal-Dielectric);

As shown in FIG. 48 and FIG. 49, step S30: use chemical mechanical polishing (CMP) to polish the pre-metal dielectric layer until the third silicon nitride 121, silicon oxide 120 and polyoxide 113 on the channel region Grinded away, exposing the amorphous silicon 110 inside;

As shown in FIGS. 50-52 , step S31 : removing the amorphous silicon 110 in the channel region by etching to expose the etch barrier layer 109 in the fin region 108 ;

As shown in FIGS. 53-55 , step S32 : continue to remove the etching barrier layer 109 by etching; here, the etching barrier layer 109 on the sidewall of the fin region 108 may be removed by etching.

As shown in FIGS. 56-58 , step S33: form an oxide layer on the surface of the fin region 108 through a low-temperature oxidation reaction as a bottom interface layer 123 (BIL, bottom interface layer), so that the high dielectric medium 124 is at the bottom interface Growth on layer 123;

As shown in FIG. 59 and FIG. 60 , step S34 : Deposit a layer of high-k HfO ₂ as the dielectric 124 by atomic layer deposition (ALD, Atomic Layer Deposition) process to form a gate dielectric. Here, a layer of high dielectric hafnium oxide can be deposited only on the upper surface of the bottom interface layer 123 as the gate dielectric.

In this embodiment, the gate is formed on the gate dielectric, the source is formed on the metal region and the first source region, and the drain is formed on the drain region, including:

As shown in Figure 61 and Figure 62, step S35: use atomic layer deposition (ALD, Atomic Layer Deposition) process to deposit a layer of work function metal TiAi base alloy 125 on the dielectric 124 layer as gate (gate TiAl); Here, work The functional metal can be selected according to device characteristics, and is not limited to TiAi-based alloy 125.

As shown in FIG. 63 and FIG. 64, step S36: deposit a thick layer of first metal tungsten 126 by means of physical vapor deposition (PVD), and the first metal tungsten 126 is filled in the cavity of the work function metal;

As shown in FIG. 65-FIG. 67, step S37: smoothen the metal tungsten by means of chemical mechanical polishing (CMP), so that the surface of the first metal tungsten 126 is flush with the surface of the first phosphosilicate glass 122 layer;

As shown in FIG. 68, step S38: depositing a second layer of phosphosilicate glass 127;

As shown in FIG. 69 and FIG. 70 , step S39: providing a source-drain contact pattern 128 on the second phosphosilicate glass 127 by photolithography to expose the corresponding positions of the first source region and the drain region;

As shown in FIG. 71 and FIG. 72, step S40: etch the second phosphosilicate glass 127 at the exposed parts corresponding to the source region and the drain region until the barrier layer of silicon nitride is exposed; and etch the corresponding part of the channel region The second phosphosilicate glass 127, until the first metal tungsten 126 in the channel region is exposed;

As shown in FIG. 73 and FIG. 74, step S41: removing the third silicon nitride 121 and silicon oxide 120 corresponding to the first source region and drain region, exposing the silicon carbide 119 in the first source region and drain region;

As shown in FIG. 75, step S42: Deposit a thick layer of second metal tungsten 129 by means of physical vapor deposition (PVD), and the second metal tungsten 129 will be filled in the cavities of the source contact and the drain contact;

As shown in Fig. 76-Fig. 78, step S43: Polish the second metal tungsten 129 through the process of chemical mechanical polishing (CMP), so that the second metal tungsten 129 forms the gate, source and drain, and completes the cold source Schott Fabrication of base transistors.

The device embodiments described above are only illustrative, and some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. It can be understood and implemented by those skilled in the art without any creative efforts.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims (13)

1. A cold source Schottky transistor, characterized in that it comprises:

   Substrate;

   a source region disposed on the substrate, the source region comprising a first source region and a metal region connected to the first source region, the first source region being a heavily doped region;

   a drain region disposed on the substrate, the drain region is a heavily doped region, and the doping type of the drain region is opposite to that of the first source region;

   a channel region, disposed on the substrate, the channel region is located between the metal region and the drain region, and a gate dielectric is provided on the upper side and/or lower side of the channel region;

   a source disposed on the source region;

   a drain disposed on the drain region;

   The gate is arranged on the gate dielectric.
2. The cold source Schottky transistor according to claim 1, wherein the channel region is an intrinsic region or a lightly doped region.
3. The cold source Schottky transistor according to claim 1, wherein the first source region is a P-type heavily doped region, and the drain region is an N-type heavily doped region.
4. The cold source Schottky transistor according to claim 1, wherein the first source region is an N-type heavily doped region, and the drain region is a P-type heavily doped region.
5. The cold source Schottky transistor according to claim 1, wherein the doping concentration of the first source region is 1e ¹⁹ cm ⁻³ to 1e ²² cm ⁻³ , and the length of the first source region is is 20nm, and the thickness of the first source region is 10nm.
6. The cold source Schottky transistor according to claim 1, wherein the doping concentration of the drain region is 1e ¹⁹ cm ⁻³ to 1e ²² cm ⁻³ , and the length of the drain region is 20 nm, so The thickness of the drain region is 10nm.
7. The cold source Schottky transistor according to claim 2, characterized in that, the doping concentration of the channel region is 1e ¹⁵ cm ^-3 , and the length of the channel region is 20nm, and the channel region The thickness is 10nm.
8. The cold source Schottky transistor according to claim 1, wherein the work function of the metal region is 5.0 eV, the length of the metal region is 10 nm, and the thickness of the metal region is 10 nm.
9. The cold source Schottky transistor according to claim 1, wherein the material of the first source region, the drain region and the channel region is silicon.
10. The cold source Schottky transistor according to claim 1, wherein the material of the gate dielectric is hafnium oxide, and the thickness of the gate dielectric is 1.5 nm.
11. A preparation process for the cold source Schottky transistor described in any one of claims 1-10, characterized in that it comprises:

    forming a well region on the substrate;

    forming a channel region, a source terminal and a drain terminal on the well region;

    forming a metal region on the source;

    forming a first source region on the source end and forming a drain region on the drain end;

    forming a gate dielectric in the channel region;

    A gate is formed on the gate dielectric, a source is formed on the metal region and the first source region, and a drain is formed on the drain region.
12. The manufacturing process of the cold source Schottky transistor according to claim 11, wherein said forming a metal region on the source terminal comprises:

    Form a layer of hard mask on the channel region, source terminal and drain terminal;

    providing a patterned layer on the hard mask;

    Etching the hard mask with no pattern layer, exposing the source end and part of the channel region;

    Generate a metal layer over the entire device surface;

    Etching the metal layer to remove the metal layer on the channel region and part of the metal layer at the source end;

    The hard mask and the metal layer on the surface of the hard mask are removed.
13. The manufacturing process of the cold source Schottky transistor according to claim 12, wherein said forming the first source region on the source end and forming the drain region on the drain end comprises:

    Epitaxially growing silicon carbide on the exposed source and drain ends of the well region to form a first source material layer and a drain material layer;

    Pre-amorphization implantation doping is performed on the first source region material layer and the drain region material layer to form the first source region and the drain region.

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