CN114512546A - Cold source Schottky transistor and preparation process thereof - Google Patents
Cold source Schottky transistor and preparation process thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66643—Lateral single gate silicon transistors with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7839—Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact
Abstract
The invention provides a cold source Schottky transistor and a preparation process thereof, wherein the cold source Schottky transistor comprises a substrate, a source region, a channel region, a source electrode, a drain electrode and a grid electrode; the source region is arranged on the substrate and comprises a first source region and a metal region connected with the first source region, and the first source region is a heavily doped region; the drain region is arranged on the substrate, is a heavily doped region and has the doping type opposite to that of the first source region; the channel region is arranged on the substrate, the channel region is positioned between the metal region and the drain region, and the upper side and/or the lower side of the channel region are/is provided with a grid medium; the source electrode is arranged on the source region; the drain electrode is arranged on the drain region; the gate is disposed on the gate dielectric. Under the condition of certain source-drain bias voltage, in the process of increasing the gate voltage, the Schottky barrier between the channel region and the metal region is pressed down, so that the Schottky barrier is thinned, when the Schottky barrier in the low-energy region is thin enough, the tunneling current can be rapidly increased, and electrons in the low-energy region of the source region tunnel through the Schottky barrier, so that the subthreshold swing amplitude is lower than 60 mV/dec.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a cold source Schottky transistor and a preparation process thereof.
Background
The miniaturization of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) under moore's law has led to the continued development of information technology over the past few decades, with switching speeds becoming faster, device densities becoming higher, and circuits becoming more powerful and efficient by reducing the channel length of the transistors. However, exponential growth in device performance cannot last forever as predicted by moore's law, and among the problems facing current transistor technology, power consumption is a significant issue due to the limitations imposed by the reduction in supply voltage. Particularly, under the device principle limitation of the MOSFET, the sub-threshold swing (SS) limit at room temperature is 60mV/dec regardless of the channel material and the device structure. This is a physical limitation of existing MOSFET designs, which prevents further reduction in the supply voltage and power consumption of MOSFET devices.
Disclosure of Invention
The invention provides a cold source Schottky transistor and a preparation process thereof, which are used for solving the defect that the sub-threshold swing of an MOSFET in the prior art cannot break through 60mV/dec, so that the power supply voltage and the power consumption of an MOSFET device cannot be further reduced.
The invention provides a cold source Schottky transistor, comprising:
a substrate;
the source region is arranged on the substrate and comprises a first source region and a metal region connected with the first source region, and the first source region is a heavily doped region;
the drain region is arranged on the substrate, is a heavily doped region and has the doping type opposite to that of the first source region;
the channel region is arranged on the substrate, the channel region is positioned between the metal region and the drain region, and the upper side and/or the lower side of the channel region are/is provided with a grid medium;
a source electrode disposed on the source region;
a drain electrode disposed on the drain region;
a gate disposed on the gate dielectric.
According to the cold source Schottky transistor provided by the invention, the channel region is an intrinsic region or a lightly doped region.
According to the cold source Schottky transistor provided by the invention, the first source region is a P-type heavily doped region, and the drain region is an N-type heavily doped region.
According to the cold source Schottky transistor provided by the invention, the first source region is an N-type heavily doped region, and the drain region is a P-type heavily doped region.
According to the Schottky transistor with the cold source provided by the invention, the doping concentration of the first source region is 1e19cm-3-1e22cm-3And the length of the first source region is 20nm, and the thickness of the first source region is 10 nm.
According to the Schottky transistor with the cold source, the doping concentration of the drain region is 1e19cm-3-1e22cm-3And the length of the drain region is 20nm, and the thickness of the drain region is 10 nm.
According to the Schottky transistor with the cold source, the doping concentration of the channel region is 1e15cm-3And the length of the channel region is 20nm, and the thickness of the channel region is 10 nm.
According to the Schottky transistor with the cold source, the work function of the metal region is 5.0eV, the length of the metal region is 10nm, and the thickness of the metal region is 10 nm.
According to the cold source Schottky transistor provided by the invention, the first source region, the drain region and the channel region are made of silicon.
The invention also provides a preparation process of the cold source Schottky transistor, which comprises the following steps:
forming a well region on a substrate;
forming a channel region, a source end and a drain end on the well region;
forming a metal area on the source end;
forming a first source region on the source end and a drain region on the drain end;
forming a gate dielectric in the channel region;
a gate electrode is formed on the gate dielectric, a source electrode is formed on the metal region and the first source region, and a drain electrode is formed on the drain region.
According to the manufacturing process of the cold source schottky transistor provided by the invention, the forming of the metal region on the source end comprises the following steps:
generating a layer of hard mask on the channel region, the source end and the drain end;
setting a pattern layer on the hard mask;
etching the hard mask without the pattern layer to expose the source end and part of the channel region;
generating a metal layer on the surface of the whole device;
etching the metal layer, and removing the metal layer on the channel region and part of the metal layer at the source end;
and removing the hard mask and the metal layer on the surface of the hard mask.
According to the preparation process of the cold source Schottky transistor, the first source region is formed on the source end, the drain region is formed on the drain end, and the preparation process comprises the following steps:
epitaxially growing silicon carbide on the exposed source end and the exposed drain end of the well region to form a first source region material layer and a first drain region material layer;
and carrying out pre-amorphization implantation doping on the first source region material layer and the drain region material layer to form a first source region and a drain region.
The source region of the cold source Schottky transistor is composed of a first heavily doped source region and a metal region, the metal region is in contact with a channel region, a Schottky barrier is formed between the metal region and the channel region, electrons in the source region are difficult to tunnel through the Schottky barrier due to the fact that the Schottky barrier is wide under the condition that grid voltage is not applied, and hot current is greatly reduced within the energy range of the forbidden band of the first source region due to the fact that the forbidden band of the first source region filters electrons injected by an external electrode, and therefore corresponding off-state current is low. Under the condition of certain source-drain bias voltage, in the process of increasing the gate voltage, the Schottky barrier between the channel region and the metal region is pressed down, so that the Schottky barrier is thinned, when the Schottky barrier in the low-energy region is thin enough, the tunneling current can be rapidly increased, and electrons in the low-energy region of the source region tunnel through the Schottky barrier, so that the subthreshold swing amplitude is lower than 60 mV/dec.
Drawings
In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a Schottky transistor with a heat sink according to the present invention;
FIG. 2 is a diagram of the band structure of a Schottky transistor with no bias applied to the heat sink according to the present invention;
FIG. 3 is a diagram of the band structure of a Schottky transistor with a cold source under a positive bias condition provided by the present invention;
FIG. 4 is a graph of Id-Vg provided by the present invention;
FIG. 5 is a side view of the device resulting from step S1 provided by the present invention;
FIG. 6 is a side view of the device resulting from step S2 provided by the present invention;
FIG. 7 is a side view of the device resulting from step S3 provided by the present invention;
FIG. 8 is a side view of the device resulting from step S4 provided by the present invention;
FIG. 9 is a side view of the device resulting from step S5 provided by the present invention;
FIG. 10 is a side view of the device resulting from step S6 provided by the present invention;
FIG. 11 is a side view of the device resulting from step S7 provided by the present invention;
FIG. 12 is a side view of the device resulting from step S8 provided by the present invention;
FIG. 13 is a side view of the device resulting from step S9 provided by the present invention;
FIGS. 14 and 15 are top and side views, respectively, of the device resulting from step S10 provided by the present invention;
FIG. 16 is a side view of the device resulting from step S11 provided by the present invention;
FIG. 17 is a side view of the device resulting from step S12 provided by the present invention;
FIG. 18 is a side view of the device resulting from step S13 provided by the present invention;
FIGS. 19 and 20 are top and side views, respectively, of the device resulting from step S14 provided by the present invention;
FIGS. 21 and 22 are top and side views, respectively, of the device resulting from step S15 provided by the present invention;
FIGS. 23 and 24 are top and side views, respectively, of a device resulting from step S16 provided by the present invention;
FIGS. 25 and 26 are top and side views, respectively, of a device resulting from step S17 provided by the present invention;
FIGS. 27 and 28 are top and side views, respectively, of a device resulting from step S18 provided by the present invention;
FIGS. 29 and 30 are top and side views, respectively, of a device resulting from step S19 provided by the present invention;
FIGS. 31 and 32 are top and side views, respectively, of the device resulting from step S20 provided by the present invention;
FIGS. 33 and 34 are top and side views, respectively, of a device resulting from step S21 provided by the present invention;
FIGS. 35 and 36 are top and side views, respectively, of a device resulting from step S22 provided by the present invention;
FIGS. 37 and 38 are top and side views, respectively, of a device resulting from step S23 provided by the present invention;
FIGS. 39 and 40 are top and side views, respectively, of a device resulting from step S24 provided by the present invention;
FIGS. 41 and 42 are top and side views, respectively, of a device resulting from step S25 provided by the present invention;
FIGS. 43 and 44 are top and side views, respectively, of a device resulting from step S26 provided by the present invention;
FIG. 45 is a side view of the device resulting from step S27 provided by the present invention;
FIG. 46 is a side view of the device resulting from step S28 provided by the present invention;
FIG. 47 is a side view of the device resulting from step S29 provided by the present invention;
FIGS. 48 and 49 are top and side views, respectively, of the device resulting from step S30 provided by the present invention;
FIGS. 50-52 are top, side and cross-sectional views, respectively, of the device resulting from step S31 provided by the present invention;
FIGS. 53-55 are top, side and cross-sectional views, respectively, of the device resulting from step S32 provided by the present invention;
FIGS. 56-58 are top, side and cross-sectional views, respectively, of the device resulting from step S33 provided by the present invention;
FIGS. 59 and 60 are side and cross-sectional views, respectively, of a device resulting from step S34 provided by the present invention;
fig. 61 and 62 are a side view and a cross-sectional view, respectively, of the device resulting from step S35 provided by the present invention;
FIGS. 63 and 64 are side and cross-sectional views, respectively, of a device resulting from step S36 provided by the present invention;
FIGS. 65-67 are top, side and cross-sectional views, respectively, of the device resulting from step S37 provided by the present invention;
FIG. 68 is a side view of the device resulting from step S38 provided by the present invention;
FIGS. 69 and 70 are top and cross-sectional views, respectively, of a device resulting from step S39 provided by the present invention;
FIGS. 71 and 72 are top and cross-sectional views, respectively, of a device resulting from step S40 provided by the present invention;
FIGS. 73 and 74 are top and cross-sectional views, respectively, of the device resulting from step S41 provided by the present invention;
FIG. 75 is a cross-sectional view of the device resulting from step S42 provided by the present invention;
fig. 76-78 are top, side, and cross-sectional views, respectively, of the device resulting from step S43 provided by the present invention.
Reference numerals are as follows:
1: a first source region; 2: a metal region; 3: a channel region; 4: a drain region; 5: a gate dielectric;
101: a substrate; 102: shielding the oxide layer; 103: a well region; 104: pad oxide layer;
105: a first silicon nitride; 106: an isolation pattern; 107: ethyl orthosilicate;
108: a fin region; 109: etching the barrier layer; 110: amorphous silicon; 111: amorphous carbon;
112: a gate pattern; 113: a polyoxide; 114: a second silicon nitride;
115: covering the pattern; 116: a second amorphous carbon; 117: a pattern layer; 118: a metal layer;
119: silicon carbide; 120: silicon oxide; 121: a third silicon nitride;
122: a first phosphosilicate glass; 123: a bottom interface layer; 124: a dielectric;
125: a TiAi-based alloy; 126: a first metal tungsten; 127: a second phosphosilicate glass;
128: source drain contact patterns; 129: a second metal tungsten.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The schottky transistor with heat sink and the fabrication process thereof according to the present invention will be described with reference to fig. 1 to 78.
As shown in fig. 1, the schottky transistor with a heat sink provided by the present invention includes a substrate 101, a source region, a drain region 4, a channel region 3, a source, a drain, and a gate.
Specifically, a source region, a drain region 4 and a channel region 3 are all disposed on the substrate 101, wherein the source region includes a first source region 1 and a metal region 2, and the metal region 2 is connected to the first source region 1; the channel region 3 is located between the metal region 2 and the drain region 4, the upper side and/or the lower side of the channel region 3 is/are provided with a gate dielectric 5, the source is arranged on the source region, the drain is arranged on the drain region 4, and the gate is arranged on the gate dielectric 5, and the first source region 1 is a heavily doped region and the drain region 4 is a heavily doped region, so that the fermi levels of the first source region 1 and the drain region 4 are in the valence band. And the doping types of the first source region 1 and the drain region 4 are opposite.
The source region is composed of a first source region 1 and a metal region 2 which are heavily doped, the metal region 2 is in contact with a channel region 3, a Schottky barrier is formed between the metal region 2 and the channel region 3, electrons in the source region are difficult to tunnel through the Schottky barrier due to the wide Schottky barrier under the condition that no gate voltage is applied, and the band gap of the first source region 1 filters the electrons injected by an external electrode, so that the hot current is greatly reduced in the band gap energy range of the first source region 1, and the corresponding off-state current is low. Under the condition of certain source-drain bias voltage, in the process of increasing the gate voltage, the Schottky barrier between the channel region 3 and the metal region 2 is pressed down, so that the Schottky barrier is thinned, when the Schottky barrier of the low-energy region is thin enough, the tunneling current can be rapidly increased, and electrons in the low-energy region of the source region tunnel through the Schottky barrier, so that the subthreshold swing amplitude is lower than 60 mV/dec.
When a gate voltage is applied, electrons in the high-energy region of the schottky barrier are reduced, and no current is generated in the high-energy region; at this time, the low energy region of the schottky barrier becomes narrow, electrons in the low energy region of the source region tunnel through the schottky barrier, and the tunneling current rapidly increases, so that the subthreshold swing is lower than 60 mV/dec.
Also, it should be noted that since the schottky barrier formed between the metal region 2 and the first source region 1 (heavily doped region) is thin and is almost an ohmic contact, the schottky barrier between the metal region 2 and the first source region 1 has little influence on the current.
Here, the cold source is realized by the junction of the first source region 1 and the metal region 2.
By the arrangement, the cold source Schottky transistor can realize relatively large on-state current relative to tunneling field effect transistors (TFTs), can realize higher switching rate relative to negative capacitance field effect transistors (NC-FETs), and does not have a hysteresis phenomenon; the device main body adopts silicon as a material, and compared with the traditional MOSFET, the whole device structure is only subjected to some correction and adjustment in a source region, namely an original N (or P) type semiconductor is changed into a structure of a P (or N) type semiconductor plus Metal (Metal), so that the compatibility degree of the device main body and the existing MOSFET in the aspects of materials and processing technology is high, and the potential of practical application is increased; compared with a P-Metal-N cold source transistor, the Schottky transistor with the cold source has no influence of electro-phonon scattering brought by an N-type part of a source region, and can realize more effective cold source injection.
In an alternative embodiment of the present invention, the channel region 3 may be an intrinsic region or a lightly doped region, so that a schottky barrier formed between the channel region 3 and the metal region 2 is very wide, and electrons in the source region are difficult to tunnel through the schottky barrier without applying a gate voltage, thereby reducing a corresponding off-state current.
In an alternative embodiment of the present invention, the first source region 1 may be a P-type heavily doped region, and the drain region 4 may be an N-type heavily doped region, or the first source region 1 may be an N-type heavily doped region, and the drain region 4 may be a P-type heavily doped region.
And, the doping concentration of the first source region 1 may be 1e19cm-3-1e22cm-3The length of the first source region 1 is 20nm, and the thickness of the first source region 1 is 10 nm. The doping concentration of the drain region 4 is 1e19cm-3-1e22cm-3The length of the drain region 4 is 20nm, and the thickness of the drain region 4 is 10 nm.
Here, the doping concentration of the first source region 1 may be 1e21cm-3(i.e. 1 x 10)21Per cubic centimeter), the doping concentration of the drain region 4 may be 1e19cm-3Specifically, the doping concentration of the first source region 1 and the drain region 4 may be determined according to the material of the first source region and the drain region, the material of the substrate, and the like, and may be specifically determined according to the actual situation.
In this embodiment, the channel region 3 may be a lightly doped region, and the doping concentration of the channel region 3 is 1e15cm-3The length of the channel region 3 is 20nm, and the thickness of the channel region 3 is 10 nm. Specifically, the channel region 3 may employ N-type light doping or P-type light doping depending on the work function of the metal region.
In an alternative embodiment, the material of the gate dielectric 5 may be hafnium oxide, and the thickness of the gate dielectric 5 may be 1.5 nm. In addition, the cold source Schottky transistor can comprise two grids which are respectively arranged on the two grid electrode mediums 5, so that under the action of the double grids, the grid control capacity is effectively improved, and the device can be well turned on and off.
In this embodiment, the left end of the first source region 1 is a source contact, the right end of the drain region 4 is a drain contact, and the upper and lower sides of the gate dielectric 5 are gate contacts, wherein the work function of the gate contacts may be 4.5 eV.
In some embodiments, the work function of metal region 2 may be 5eV, and the length of metal region 2 may be 10nm and the thickness of the metal region may be 10 nm. Here, the work function, the length, and the thickness of the metal region are not specifically limited, and may be specifically determined according to the actually selected material.
In this embodiment, the first source region 1 and the metal region 2 may be in horizontal contact, and the first source region 1 and the metal region 2 may also be in vertical contact or in contact along other directions (i.e., in a double-pointed contact).
In this embodiment, the substrate may be made of silicon (Si) or germanium (Ge), or a iii-V material, and the first source region may also be made of silicon (Si) or germanium (Ge), or a iii-V material, where the iii-V material includes: InSb, GaSb, InAs, AlSb, AlAs, GaAs, InGaAs, InAlAs, InP, InGaP, or the like; the material of the metal region may be Au, Co, Cu, Pd, Pt, Ti, W, TiN, NiSi2, etc.
As shown in fig. 2, the first source region 1, the metal region 2, the channel region 3 and the drain region 4 have uniform fermi levels in the absence of applied bias; as shown in fig. 3, when a voltage of 0.2V is applied to the drain and a voltage of 1V is applied to the gate, the first source region 1, the metal region 2, the channel region 3, and the drain region 4 no longer have uniform fermi levels, and quasi-fermi levels of electrons and holes are generated, the height of the schottky barrier is reduced by applying a forward bias, the diffusion motion of carriers is larger than the drift motion, a certain concentration gradient is generated by recombination of carriers in the source region after being injected into the channel region 3, and a certain concentration gradient is generated by recombination of carriers in the channel region 3 after being injected into the drain region 4, so as to form a steady distribution.
As shown in fig. 4, fig. 4 is a graph of approximate Id-Vg obtained by simulation in Sentaurus TCAD, that is, a graph of influence of gate voltage on current, and a line bent more in fig. 4 is a graph of drain current and gate voltage of a cold source schottky transistor whose source region includes a first source region 1 and a metal region 2; the relatively less bent line is a plot of source drain current versus gate voltage for a schottky transistor having a source region comprising only metal region 2. As can be seen from fig. 4, the subthreshold swing is lower than 60Mv/dec at around 0.6V, and about 3 orders of magnitude current change is achieved between 0.6V-0.7V, indicating a rapid increase in tunneling current.
It should be noted that, due to the existence of the schottky barrier, the drain current is dominated by the tunneling current rather than the thermal current, and the on-state current is lower than that of the conventional MOSFET by 1 to 2 orders of magnitude, but a better on-state current characteristic can be realized by adjusting the gate contact work function, the metal work function of the source end, the doping concentration of the first source region 1, and the like.
The manufacturing process of the schottky transistor with the heat sink provided by the present invention is described below, and the manufacturing process of the schottky transistor with the heat sink described below and the schottky transistor with the heat sink described above may be referred to in correspondence.
As shown in fig. 5 to fig. 78, the manufacturing process of the schottky transistor with a heat sink provided by the present invention includes:
forming a well region 103 on a substrate 101;
forming a channel region, a source terminal and a drain terminal on the well region 103;
forming a metal area on the source end;
forming a first source region 1 on the source end and a drain region on the drain end;
forming a gate dielectric in the channel region;
a gate electrode is formed on the gate dielectric, a source electrode is formed on the metal region and the first source region 1 and a drain electrode is formed on the drain region.
Wherein, in forming the metal region on the source end, including:
as shown in fig. 31 and 32, step S20: generating a layer of hard mask on the channel region, the source end and the drain end;
as shown in fig. 33 and 34, step S21: disposing a pattern layer 117 on the hard mask;
as shown in fig. 35 and 36, step S22: etching the hard mask without the pattern layer 117 to expose the source end and part of the channel region;
as shown in fig. 37 and 38, step S23: generating a metal layer 118 on the whole device surface;
as shown in fig. 39 and 40, step S24: etching the metal layer 118, removing the metal layer on the channel region and a part of the metal layer at the source end, and leaving a metal layer with a certain thickness on one side of the channel region close to the source end to form a metal region;
as shown in fig. 41 and 42, step S25: and removing the hard mask and the metal layer attached to the surface of the hard mask.
Specifically, a layer of second Amorphous carbon 116 (Amorphous carbon) is grown on the channel region, the source terminal and the drain terminal to serve as a hard mask, and the surface of the hard mask is polished to be flat by means of Chemical Mechanical Polishing (CMP);
then, a photoresist pattern layer 117 is arranged on the hard mask through a photoetching process, and the source end and a part of the channel region are exposed;
removing the second amorphous carbon 116 of the source end and a part of the channel region by etching, and then removing the pattern layer 117;
growing a metal layer 118 by means of Physical Vapor Deposition (PVD);
etching the metal layer 118, removing the metal layer on the channel region and a part of the metal layer at the source end, and leaving a metal layer with a certain thickness on one side of the channel region close to the source end to form a metal region;
and finally, removing the hard mask and the metal layer attached to the surface of the hard mask. The metal layer on the surface of the hard mask refers to an excess metal layer, the excess metal layer can be removed simultaneously when the hard mask is removed, and an extra means is not needed to remove the excess metal layer, so that the metal layer on the wall of the channel region is not influenced when the excess metal layer is removed.
In an alternative embodiment of the present invention, forming the first source region 1 on the source terminal and forming the drain region on the drain terminal includes:
as shown in fig. 43 and 44, step S26: epitaxially growing silicon carbide 119 on the exposed source end and the exposed drain end of the well region 103 to form a first source region material layer and a first drain region material layer;
as shown in fig. 45, step S27: and carrying out pre-amorphization implantation doping on the first source region material layer and the drain region material layer to form a first source region and a drain region.
Specifically, silicon carbide 119(SiC) is epitaxially grown in the well region 103 (silicon region) partially exposed at the source and drain terminals, thereby forming first source and drain region material layers; and performing Pre-Amorphization PAI (Silicon Pre-annealing implantation) on the first source region material layer and the first drain region material layer to form a uniform and low-resistance Silicon layer, namely forming a first source region and a first drain region. Alternatively, the first source region material layer and the drain region material layer may be subjected to ion implantation, metal silicide formation, or the like to reduce contact resistance of the first source region and the drain region.
Here, the doping manner of the first source region and the drain region is not limited, and may be determined according to actual conditions.
In an alternative embodiment of the present invention, forming well region 103 on substrate 101 includes:
as shown in fig. 5, step S1: growing a shielding oxide layer 102 on a silicon wafer (substrate 101); here, a screen oxide layer 102 may be grown on the silicon wafer by thermal oxidation or chemical vapor deposition.
As shown in fig. 6, step S2: performing ion implantation on the silicon wafer through an ion implanter to form a well region 103 on the silicon wafer;
here, boron ions may be implanted into the silicon wafer by an ion implanter to form a P-well on the silicon wafer, and a peak of the concentration of the implanted ions may be controlled to be located at a central region of the silicon wafer.
Then, as shown in fig. 7, step S3: the shielding oxide layer 102 is removed by etching, and then the silicon wafer is subjected to rapid annealing treatment to repair the crystal lattice of the silicon wafer, thereby activating the well region 103.
In an alternative embodiment, forming a channel region, a source terminal and a drain terminal on the well region 103 includes:
forming shallow trench isolation in the substrate 101;
a channel region, a source terminal, and a drain terminal are formed in the substrate 101.
Specifically, forming shallow trench isolations in the substrate 101 includes:
as shown in fig. 8, step S4: growing a Pad Oxide layer 104(Pad Oxide) on the substrate 101;
forming a layer of first Silicon Nitride 105 (SiN) on the pad oxide layer 104 by Chemical Vapor Deposition (CVD);
providing a photoresist isolation pattern 106 on the first silicon nitride 105 through a photolithography process;
as shown in fig. 9, step S5: etching the first silicon nitride 105 down until the pad oxide layer 104 is exposed, and then removing the isolation pattern 106;
as shown in fig. 10, step S6: continuing to etch downwards by taking the first silicon nitride 105 as a hard mask until reaching the well region 103 to form a shallow groove and a Fin region 108 (Fin);
as shown in fig. 11, step S7: filling tetraethoxysilane 107(TEOS) in the shallow groove by means of Chemical Vapor Deposition (CVD);
as shown in fig. 12, step S8: grinding the tetraethoxysilane 107 by means of Chemical Mechanical Polishing (CMP) until the tetraethoxysilane 107 is flush with the first silicon nitride 105 of the Fin region 108 (Fin);
as shown in fig. 13, step S9: the remaining first silicon nitride 105 is removed by hot phosphoric acid solution, and then a portion of the tetraethoxysilane around the Fin region 108(Fin) is removed by etching, leaving the tetraethoxysilane 107 located in the well region 103 portion as Shallow Trench Isolation (STI).
Specifically, forming a channel region, a source terminal, and a drain terminal in the substrate 101 includes:
as shown in fig. 14 and 15, step S10: growing an oxide layer as an etch stop layer 109 (ESL) on the Fin region 108(Fin) by thermal oxidation;
as shown in fig. 16, step S11: depositing a thick Amorphous Silicon 110 layer (Amorphous Silicon) by means of chemical vapor deposition, and polishing the Amorphous Silicon 110 layer by means of Chemical Mechanical Polishing (CMP);
as shown in fig. 17, step S12: growing a layer of first amorphous carbon 111 as a hard mask;
as shown in fig. 18, step S13: forming a gate pattern 112 on the first amorphous carbon 111 by photolithography; here, a layer of the first amorphous carbon 111 may be grown by means of chemical vapor deposition or physical vapor deposition.
As shown in fig. 19 and 20, step S14: etching the hard mask formed by the first amorphous carbon 111 outside the gate pattern 112, continuously etching the amorphous silicon 110 outside the gate pattern 112 downwards, and removing the gate pattern 112 and the remaining first amorphous carbon 111;
as shown in fig. 21 and 22, step S15: growing a layer of polyoxide 113 on the amorphous silicon 110 by means of thermal oxidation;
as shown in fig. 23 and 24, step S16: depositing a layer of second silicon nitride 114;
as shown in fig. 25 and 26, step S17: etching the second silicon nitride 114 to generate a layer of second silicon nitride 114 gasket on the side walls of the fin region 108 and the amorphous silicon 110, and forming a channel region, a source terminal region and a drain terminal region;
as shown in fig. 27 and 28, step S18: forming a capping pattern 115 capping the channel region through a photolithography process;
as shown in fig. 29 and 30, step S19: the exposed Fin region 108(Fin) of the source region and the drain region is removed by spacer etching, and then the mask pattern 115 is removed to form a channel region, a source region, and a drain region on the substrate.
In this embodiment, the forming of the gate dielectric in the channel region includes:
as shown in fig. 46, step S28: forming a layer of Silicon Oxide 120(Silicon Oxide) and a layer of third Silicon Nitride 121(Silicon Nitride) on the surface of the amorphous Silicon 110 and the channel region, the source region and the drain region as a stop layer for etching the contact hole;
as shown in fig. 47, step S29: depositing a thick layer of first phosphosilicate Glass (PSG) 122 on the surface of the third silicon nitride 121 to act as a pre-Metal-Dielectric (PMD);
as shown in fig. 48 and 49, step S30: grinding the pre-metal dielectric layer in a Chemical Mechanical Polishing (CMP) mode until the third silicon nitride 121, the silicon oxide 120 and the polyoxide 113 on the channel region are ground off to expose the amorphous silicon 110 inside;
as shown in fig. 50 to 52, step S31: removing the amorphous silicon 110 in the channel region by etching to expose the etch stop layer 109 in the fin region 108;
as shown in fig. 53-55, step S32: continuously removing the etching barrier layer 109 in an etching mode; here, the etch stopper 109 on the sidewall of the fin region 108 may be removed by etching.
As shown in fig. 56 to 58, step S33: forming an oxide layer on the surface of the fin region 108 by low temperature oxidation reaction as a bottom interface layer 123 (BIL) to grow the high dielectric medium 124 on the bottom interface layer 123;
as shown in fig. 59 and 60, step S34: depositing a Layer of High-k hafnium oxide (High-k HfO) by an Atomic Layer Deposition (ALD) process2) As dielectric 124, a gate dielectric is formed. Here, a layer of high dielectric hafnium oxide may be deposited only on the top surface of the bottom interfacial layer 123 to serve as the gate dielectric.
In this embodiment, forming a gate on the gate dielectric, forming a source on the metal region and the first source region, and forming a drain on the drain region, includes:
as shown in fig. 61 and 62, step S35: depositing a Layer of work function metal, TiAi-based alloy 125, as a gate (gate TiAl) on the dielectric 124 Layer using an Atomic Layer Deposition (ALD) process; here, the work function metal may be selected according to device characteristics, and is not limited to the TiAi-based alloy 125.
As shown in fig. 63 and 64, step S36: depositing a thick layer of first metal tungsten 126 by means of Physical Vapor Deposition (PVD), wherein the first metal tungsten 126 is filled in the cavity of the work function metal;
as shown in fig. 65 to 67, step S37: polishing the tungsten metal by Chemical Mechanical Polishing (CMP) to make the first tungsten metal 126 flush with the surface of the first phosphosilicate glass 122 layer;
as shown in fig. 68, step S38: a layer of second phosphosilicate glass 127 is deposited;
as shown in fig. 69 and 70, step S39: a source-drain contact pattern 128 is arranged on the second phosphosilicate glass 127 in a photoetching mode, and positions corresponding to the first source region and the drain region are exposed;
as shown in fig. 71 and 72, step S40: etching the second phosphosilicate glass 127 at the exposed parts corresponding to the source region and the drain region until the barrier layer of the silicon nitride is exposed; etching the second phosphosilicate glass 127 corresponding to the channel region until the first metal tungsten 126 of the channel region is exposed;
as shown in fig. 73 and 74, step S41: removing the third silicon nitride 121 and the third silicon oxide 120 corresponding to the first source region and the first drain region to expose the silicon carbide 119 of the first source region and the first drain region;
as shown in fig. 75, step S42: depositing a thick layer of second metal tungsten 129 by means of Physical Vapor Deposition (PVD), wherein the second metal tungsten 129 fills the cavities of the source contact and the drain contact;
as shown in fig. 76 to 78, step S43: the second metal tungsten 129 is polished by a Chemical Mechanical Polishing (CMP) process, so that the second metal tungsten 129 forms a gate, a source and a drain, and the preparation of the heat sink schottky transistor is completed.
The above-described embodiments of the apparatus are merely illustrative, and some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (13)
1. A cold-source schottky transistor, comprising:
a substrate;
the source region is arranged on the substrate and comprises a first source region and a metal region connected with the first source region, and the first source region is a heavily doped region;
the drain region is arranged on the substrate, is a heavily doped region and has the doping type opposite to that of the first source region;
the channel region is arranged on the substrate, the channel region is positioned between the metal region and the drain region, and the upper side and/or the lower side of the channel region are/is provided with a grid medium;
a source electrode disposed on the source region;
a drain electrode disposed on the drain region;
a gate disposed on the gate dielectric.
2. The cold source schottky transistor of claim 1 wherein the channel region is an intrinsic region or a lightly doped region.
3. The cold source schottky transistor of claim 1 wherein the first source region is a heavily P-doped region and the drain region is a heavily N-doped region.
4. The cold source schottky transistor of claim 1 wherein the first source region is a heavily N-doped region and the drain region is a heavily P-doped region.
5. The cold-source schottky transistor of claim 1 wherein the first source region has a doping concentration of 1e19cm-3-1e22cm-3And the length of the first source region is 20nm, and the thickness of the first source region is 10 nm.
6. The refrigerator as claimed in claim 1A source Schottky transistor wherein said drain region has a doping concentration of 1e19cm-3-1e22cm-3And the length of the drain region is 20nm, and the thickness of the drain region is 10 nm.
7. The cold-source schottky transistor of claim 2 wherein the channel region has a doping concentration of 1e15cm-3And the length of the channel region is 20nm, and the thickness of the channel region is 10 nm.
8. The cold source schottky transistor of claim 1, wherein the metal region has a work function of 5.0eV, a length of 10nm, and a thickness of 10 nm.
9. The cold-source schottky transistor of claim 1 wherein the first source region, the drain region and the channel region are made of silicon.
10. The cold-source schottky transistor of claim 1 wherein the gate dielectric is hafnium oxide and has a thickness of 1.5 nm.
11. A process for preparing a cold source schottky transistor according to any one of claims 1 to 10, comprising:
forming a well region on a substrate;
forming a channel region, a source end and a drain end on the well region;
forming a metal area on the source end;
forming a first source region on the source end and a drain region on the drain end;
forming a gate dielectric in the channel region;
a gate electrode is formed on the gate dielectric, a source electrode is formed on the metal region and the first source region, and a drain electrode is formed on the drain region.
12. The process of claim 11, wherein the forming a metal region on the source terminal comprises:
generating a layer of hard mask on the channel region, the source end and the drain end;
setting a pattern layer on the hard mask;
etching the hard mask without the pattern layer to expose the source end and part of the channel region;
generating a metal layer on the surface of the whole device;
etching the metal layer, and removing the metal layer on the channel region and part of the metal layer at the source end;
and removing the hard mask and the metal layer on the surface of the hard mask.
13. The process for manufacturing a cold source schottky transistor according to claim 12, wherein the forming a first source region on a source terminal and a drain region on a drain terminal comprises:
epitaxially growing silicon carbide on the exposed source end and the exposed drain end of the well region to form a first source region material layer and a first drain region material layer;
and carrying out pre-amorphization implantation doping on the first source region material layer and the drain region material layer to form a first source region and a drain region.
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| PCT/CN2022/143750 WO2023125894A1 (en) | 2021-12-31 | 2022-12-30 | Cold-source schottky transistor and preparation process therefor |
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| WO2023125894A1 (en) * | 2021-12-31 | 2023-07-06 | 北京大学 | Cold-source schottky transistor and preparation process therefor |
| WO2023221552A1 (en) * | 2022-05-18 | 2023-11-23 | 北京大学 | Schottky transistor, diode, and cold source semiconductor structure and preparation method therefor |
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| WO2019233481A1 (en) * | 2018-06-06 | 2019-12-12 | Versitech Limited | Metal-oxide-semiconductor field-effect transistor with cold source |
| CN109560128B (en) * | 2018-11-07 | 2022-03-11 | 南通大学 | Tunneling field effect transistor |
| CN114512546A (en) * | 2021-12-31 | 2022-05-17 | 北京大学 | Cold source Schottky transistor and preparation process thereof |
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| WO2023125894A1 (en) * | 2021-12-31 | 2023-07-06 | 北京大学 | Cold-source schottky transistor and preparation process therefor |
| WO2023221552A1 (en) * | 2022-05-18 | 2023-11-23 | 北京大学 | Schottky transistor, diode, and cold source semiconductor structure and preparation method therefor |
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