CN116247099A - Mixed conduction mechanism surrounding grid transistor and manufacturing method thereof - Google Patents

Mixed conduction mechanism surrounding grid transistor and manufacturing method thereof Download PDF

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Publication number
CN116247099A
CN116247099A CN202211730768.5A CN202211730768A CN116247099A CN 116247099 A CN116247099 A CN 116247099A CN 202211730768 A CN202211730768 A CN 202211730768A CN 116247099 A CN116247099 A CN 116247099A
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source region
drain region
region
layer
gate
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吴春蕾
许煜民
沈伯佥
赵斐
杨子辰
张卫
徐敏
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Fudan University
Shanghai IC Manufacturing Innovation Center Co Ltd
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Fudan University
Shanghai IC Manufacturing Innovation Center Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

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Abstract

The invention provides a mixed conduction mechanism surrounding gate transistor, which comprises a surrounding gate MOSFET device, a second source region and a second drain region; the gate-all MOSFET device comprises a substrate, a first source region and a first drain region; first ions are doped in the first source region and the first drain region; the second source region is formed between the substrate and the first source region, the second drain region is formed between the substrate and the first drain region, and the heights of the second source region and the second drain region are not lower than the height of the substrate between the first source region and the first drain region; the second drain region is doped with first ions, and the second source region is doped with second ions. According to the technical scheme, the problem of current leakage of a parasitic channel at the bottom of the surrounding gate MOSFET device is solved, and the second source region and the second drain region are additionally arranged, so that the structure of the TFET device is equivalent to that of a tunneling field effect transistor connected in parallel at the bottom of the traditional surrounding gate MOSFET device, and the mixed conduction of the surrounding gate channel diffusion drift current and the tunneling current of a bottom channel band can be realized, so that the better ultra-steep switching characteristic is obtained.

Description

Mixed conduction mechanism surrounding grid transistor and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductors, in particular to a fence transistor with a mixed conduction mechanism and a manufacturing method thereof.
Background
Microelectronic integration technology has been continuously developed according to moore's law since the advent of integrated circuits. With the reduction in the size of Complementary Metal Oxide Semiconductor (CMOS) Field Effect Transistors (FETs), microprocessors have significantly increased in switching speed, density, functionality, and cost. Device power consumption remains one of the important challenges in device size scaling. The main technical approach to reduce the power consumption of the device is to enhance the gate control capability of the device, and after the fin-shaped transistor, the surrounding gate nanowire/nano-chip field effect transistor becomes the next generation mainstream logic device structure due to the superior channel gate control capability. Due to process fluctuations, the existence of severe bottom parasitic channel leakage paths in the wrap-around nanowire devices, how to suppress off-state leakage currents, becomes one of the key challenges in the optimization of the wrap-around devices.
Another effective way to reduce the power consumption of the device is to reduce the supply voltage VDD, and the subthreshold swing of conventional MOSFET devices is limited by kT/q thermodynamic distribution, and there is a theoretical limit of 60mV/dec at room temperature, which makes ULSI chips based on conventional MOSFET devices unable to continuously reduce the supply voltage. The tunneling field effect transistor (TFET, tunnelingField-effect transistor) is one of the devices with great potential in the future ultra-low power integrated circuit application due to excellent subthreshold characteristics, small off-state leakage current, low switching power consumption and other excellent electrical characteristics. The conduction mechanism of the tunneling transistor is quantum mechanical band tunneling, so that the tunneling transistor is not limited by thermodynamic temperature, and the limit of 60mV/dec can be broken through at the room temperature of the subthreshold swing. Thus, developing a transistor that can effectively suppress the bottom leakage current while significantly improving the subthreshold characteristics of the device is a technical focus to be addressed by those skilled in the art.
Disclosure of Invention
The invention provides a fence transistor with a mixed conduction mechanism and a manufacturing method thereof, which are used for solving the problem of current leakage of a parasitic channel at the bottom of a fence MOSFET device.
According to a first aspect of the present invention there is provided a mixed conduction mechanism wrap gate transistor comprising:
the gate-all MOSFET device comprises a substrate, a first source region and a first drain region; the first source region and the first drain region are arranged along a first direction; wherein, the first source region and the first drain region are doped with first ions; wherein the first direction characterizes a direction parallel to the substrate;
a second source region and a second drain region, the second source region is formed between the substrate and the first source region, the second drain region is formed between the substrate and the first drain region, and the heights of the second source region and the second drain region are not lower than the height of the substrate between the first source region and the first drain region;
wherein the second drain region is doped with a first ion, the second source region is doped with a second ion, and the type of the first ion is different from the type of the second ion.
Optionally, the thickness of the second source region and/or the second drain region is 5nm-50nm.
Optionally, the first ion is a P-type ion or an N-type ion.
Optionally, the second ion is a P-type ion or an N-type ion.
Optionally, the concentration of doped ions in the second source region and/or the second drain region is 1E16cm < -3 > to 1E22cm < -3 >.
Optionally, the material of the second source region and the material of the second drain region are: binary or ternary compounds of groups II-VI, III-V or IV-IV.
Optionally, the material of the second source region and the material of the second drain region are Si, siGe or Ge.
Optionally, the boom MOSFET device further includes:
a channel layer formed between the first source region and the first drain region and arranged at intervals in a direction away from the substrate;
the gate dielectric layer wraps part of the surface of the channel layer; the control gate wraps the surface of the gate dielectric layer;
the inner side wall is formed between the first source region and the gate dielectric layer and on the surface of the channel layer between the first drain region and the gate dielectric layer;
a source metal layer, a gate metal layer and a drain metal layer; the source electrode metal layer and the drain electrode metal layer are respectively formed on the surfaces of the first source region and the first drain region, and respectively fully wrap the first source region and the second source region and the first drain region and the second drain region; the grid metal layer is formed on the top end of the control grid;
an interlayer dielectric layer covering the source metal layer, the gate metal layer, the drain metal layer and the surface of the inner side wall;
and the metal contact layer penetrates through the interlayer dielectric layer and is respectively connected with the source electrode metal layer, the gate electrode metal layer and the drain electrode metal layer.
According to a second aspect of the present invention, there is provided a method of manufacturing a mixed conduction mode peripheral gate transistor for manufacturing a mixed conduction mode peripheral gate transistor according to any one of the first aspect of the present invention, comprising:
forming the surrounding gate MOSFET device, the second source region and the second drain region; the surrounding grid MOSFET device comprises a substrate, a first source region and a first drain region; the first source region and the first drain region are doped with the first ions; the second source region and the second drain region are respectively formed between the substrate and the first source region and between the substrate and the first drain region, and the heights of the second source region and the second drain region are not lower than the height of the substrate between the first source region and the first drain region;
the second drain region is doped with the first ions, and the second source region is doped with the second ions.
Optionally, forming the surrounding gate MOSFET device and the second source region and the second drain region specifically includes:
providing the substrate;
forming a sacrificial layer and the channel layer; the sacrificial layer and the channel layer are stacked on the substrate at intervals;
etching the sacrificial layer and the channel layer to form a fin structure, and over-etching the substrate on two sides of the fin structure along the first direction to form a first cavity and a second cavity; the first cavity and the second cavity are sequentially arranged along the first direction;
forming a dummy gate structure, and etching two ends of the sacrificial layer along the first direction to form an inner side wall cavity;
forming the inner side wall; the inner side wall is formed in the inner side wall cavity;
forming the second source region and the second drain region; the second source region is formed in the first cavity, and the second drain region is formed in the second cavity;
forming the first source region and the first drain region; the first source region and the first drain region are respectively formed at the top ends of the second source region and the second drain region;
removing the dummy gate structure and releasing the channel layer;
and forming the gate dielectric layer, the control gate, the source metal layer, the gate metal layer, the drain metal layer, the interlayer dielectric layer and the metal contact layer.
Optionally, forming the second source region and the second drain region specifically includes:
forming a patterned first mask layer; the patterned first mask layer covers the second cavity, the dummy gate structure and the surface of the inner side wall;
filling the material of the second source region in the first cavity to form the second source region, and removing the patterned first mask layer;
forming a patterned second mask layer; the patterned second mask layer covers the second source region, the dummy gate structure and the surface of the inner side wall;
and forming a second drain region by depositing and filling the material of the second drain region in the second cavity, and removing the patterned second mask layer.
According to a third aspect of the present invention there is provided an electronic device comprising a mixed turn-on mechanism wrap gate transistor according to any one of the first aspects of the present invention.
According to a fourth aspect of the present invention, there is provided a method for manufacturing an electronic device, including a method for manufacturing a mixed conduction gate transistor according to any one of the second aspect of the present invention.
According to the mixed conduction mechanism gird-gate transistor, the second source region and the second drain region are respectively arranged between the first source region and the substrate and between the first drain region and the substrate, the first ions are doped in the second drain region, the second ions are doped in the second source region, the types of the first ions are different from those of the second ions, so that a reverse bias P-I-N channel is formed at the bottom, and the structure can obviously inhibit the bottom parasitic channel leakage current of a traditional gird-gate MOSFET device, thereby enhancing the current switching ratio of the device.
Furthermore, in the structure of the mixed conduction mechanism surrounding gate transistor, the second source region and the second drain region are additionally arranged, so that the structure is equivalent to the structure of a TFET device connected in parallel with the bottom of a traditional surrounding gate MOSFET device, and the mixed conduction of surrounding gate channel diffusion drift current and bottom channel quantum mechanical band tunneling current can be realized, thereby obtaining the ultra-steep switching characteristic lower than 60 mV/dec. Meanwhile, the surrounding grid MOSFET devices connected in parallel above are conducted, and high current can be provided for the devices.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a mixed turn-on mechanism surrounding gate transistor according to an embodiment of the present invention;
FIG. 2 is a schematic flow chart of a method for manufacturing a hybrid turn-on mechanism surrounding gate transistor according to an embodiment of the present invention;
fig. 3-6 are schematic views of a device structure at different process stages according to a method for manufacturing a hybrid turn-on mechanism surrounding gate transistor according to an embodiment of the present invention;
reference numerals illustrate:
101-a substrate;
102-a first source region;
103-a first drain region;
104-a second source region;
105-a second drain region;
106-a channel layer;
107-gate dielectric layer;
108-a control gate;
109-a drain metal layer;
110-a gate metal layer;
111-source metal layer;
112-an interlayer dielectric layer;
113-a metal interconnect layer;
114-an inner wall;
115-dummy gate structure;
116-photoresist.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Microelectronic integration technology has been continuously developed according to moore's law since the advent of integrated circuits. With the reduction in the size of Complementary Metal Oxide Semiconductor (CMOS) Field Effect Transistors (FETs), microprocessors have significantly increased in switching speed, density, functionality, and cost. Device power consumption remains one of the important challenges in device size scaling. The main technical approach to reduce the power consumption of the device is to enhance the gate control capability of the device, and after the fin-shaped transistor, the surrounding gate nanowire/nano-chip field effect transistor becomes the next generation mainstream logic device structure due to the superior channel gate control capability. Due to process fluctuations, the existence of severe bottom parasitic channel leakage paths in the wrap-around nanowire devices, how to suppress off-state leakage currents, becomes one of the key challenges in the optimization of the wrap-around devices.
Another effective way to reduce the power consumption of the device is to reduce the supply voltage VDD, and the subthreshold swing of conventional MOSFET devices is limited by kT/q thermodynamic distribution, and there is a theoretical limit of 60mV/dec at room temperature, which makes ULSI chips based on conventional MOSFET devices unable to continuously reduce the supply voltage. The tunneling field effect transistor (TFET, tunnelingField-effect transistor) is one of the devices with great potential in the future ultra-low power integrated circuit application due to excellent subthreshold characteristics, small off-state leakage current, low switching power consumption and other excellent electrical characteristics. The conduction mechanism of the tunneling transistor is quantum mechanical band tunneling, so that the tunneling transistor is not limited by thermodynamic temperature, and the limit of 60mV/dec can be broken through at the room temperature of the subthreshold swing.
In view of the inventor of the present application, a source region and a drain region are additionally arranged on a bottom parasitic channel to form a structure similar to a tunneling transistor at the bottom of the surrounding gate nanowire/nanoflake field effect transistor; the novel structure combined by the tunneling transistor and the surrounding gate nanowire/nano sheet field effect transistor has the advantages that the surrounding gate field effect transistor with the mixed conduction mechanism can effectively inhibit bottom leakage current and simultaneously obviously improve the subthreshold characteristic of the device.
The technical scheme of the invention is described in detail below by specific examples. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.
Referring to fig. 1-6, according to an embodiment of the present invention, there is provided a mixed turn-on mechanism surrounding gate transistor, including:
a wrap-gate MOSFET device comprising a substrate 101, a first source region 102, and a first drain region 103; the first source region 102 and the first drain region 103 are arranged along a first direction; wherein, first ions are doped in the first source region 102 and the first drain region 103; wherein the first direction characterizes a direction parallel to the substrate 101;
a second source region 104 and a second drain region 105, the second source region 104 being formed between the substrate 101 and the first source region 102, the second drain region 105 being formed between the substrate 101 and the first drain region 103, and a height of the second source region 104, the second drain region 105 being not lower than a height of the substrate 101 between the first source region 102 and the first drain region 103;
wherein the second drain region 105 is doped with a first ion, the second source region 104 is doped with a second ion, and the type of the first ion is different from the type of the second ion, as shown in fig. 1.
The second source region and the second drain region may be a structural layer, or may be a multi-layer structural layer, which is not limited in sequence.
Compared with the prior art, the surrounding gate transistor with the mixed conduction mechanism is provided with the second source region and the second drain region between the first source region and the substrate and between the first drain region and the substrate, wherein the second drain region is doped with first ions, the second source region is doped with second ions, the types of the first ions are different from those of the second ions, and a reverse bias P-I-N channel is formed at the bottom in an off state.
Furthermore, in the structure of the mixed conduction mechanism surrounding gate transistor, the second source region and the second drain region are additionally arranged, so that the structure is equivalent to that of a TFET device of a traditional surrounding gate MOSFET device which is connected in parallel with a tunneling field effect transistor, and the mixed conduction of the surrounding gate channel diffusion drift current and the bottom channel quantum mechanical band tunneling current can be realized when the device is in an on state, so that the whole device has the ultra-steep switching characteristic lower than 60 mV/dec. Meanwhile, in the on state, the surrounding grid MOSFET devices connected in parallel above are conducted, so that high current can be provided for the devices.
In one embodiment, the first ion is a P-type ion or an N-type ion.
In one embodiment, the second ion is a P-type ion or an N-type ion.
Specifically, the P-type ions are: the hydride, fluoride or chloride of boron is one or a combination of the following materials: B2H6, B4H10, B6H10, B10H14, B18H22, BF3 or BCl3; the N-type ions are as follows: the hydride and fluoride of phosphorus and arsenic are one or a combination of the following materials: phosphane, arsine, phosphorus pentafluoride, phosphorus trifluoride, arsenic pentafluoride or arsenic trifluoride.
The channel region and the bottom Fin region (i.e., the substrate 101 between the second source region 104 and the second drain region 105) are undoped or lightly doped i regions;
wherein, for N-type devices, the first source region 102 is N-type doped with a doping concentration of about 1E18cm-3 to about 1E22cm-3, and the first drain region 103 is N-type doped with a doping concentration of about
1E18cm-3-1E22cm-3, the second source region 104 being P-type doped with a doping concentration of about 1E18cm-3-1E22cm-3, the second drain region 105 being N-type doped with a doping concentration of about 1E16cm-3-1E21cm-3;
for P-type devices, the first source region 102 is P-type doped with a doping concentration of about 1E18cm-3 to about 1E22cm-3, the first drain region 103 is P-type doped with a doping concentration of about 1E18cm-3 to about 1E20cm-3, the second source region 104 is N-type doped with a doping concentration of about 1E18cm-3 to about 1E22cm-3, and the second drain region 105 is P-type doped with a doping concentration of about 1E16cm-3 to about 1E21cm-3.
In the mixed conduction mechanism surrounding gate transistor, the thickness of the second source region and the second drain region and the doping concentration of the second source region are important parameters for device design. The thickness of the second source region or the second drain region is too thin, so that the influence of the bottom tunneling field effect transistor on the total current is small, and the subthreshold swing characteristic of the device is limited; too thick a second source or drain region may increase process difficulty, resulting in reduced device uniformity and reliability. The doping concentration of the second source region cannot be too low, the resistance of the second source region is increased due to the fact that the doping concentration is too low, meanwhile, the tunneling probability of the bottom tunneling transistor is reduced due to the fact that the tunneling of the band is more difficult to occur due to the fact that the doping concentration is low, and the current is reduced. The doping concentration of the second drain region also needs to be controlled in a certain range, and the doping concentration is too low, so that the resistance of the bottom drain region is increased, and the current is reduced; too high doping concentration results in more significant channel bipolar effect of the TFET device. Thus: in a preferred embodiment, the thickness of the second source region 104 and/or the second drain region 105 is 5nm-50nm. In a preferred embodiment, the concentration of doped ions in the second source region 104 and/or the second drain region 105 is 1E16cm-3 to 1E22cm-3.
In one embodiment, the material of the second source region 104 and the material of the second drain region 105 are: binary or ternary compounds of groups II-VI, III-V or IV-IV.
In one embodiment, the material of the second source region 104 and the material of the second drain region 105 is Si, siGe, or Ge.
In one embodiment, the wrap gate MOSFET device further comprises:
a channel layer 106 formed between the first source region 102 and the first drain region 103 and arranged at intervals in a direction away from the substrate 101;
a gate dielectric layer 107 and a control gate 108, wherein the gate dielectric layer 107 wraps part of the surface of the channel layer 106; the control gate 108 wraps the surface of the gate dielectric layer 107;
an inner sidewall 114 formed between the first source region 102 and the gate dielectric layer 107, and on the surface of the channel layer 106 between the first drain region 103 and the gate dielectric layer 107;
a source metal layer 111, a gate metal layer 110, and a drain metal layer 109;
in one embodiment, the source metal layer 111 and the drain metal layer 109 are formed on the surfaces of the first source region 102 and the first drain region 103, respectively, and completely encapsulate the first source region 102 and the first drain region 103, respectively; the gate metal layer 110 is formed on top of the control gate 108;
because the second source-drain region lead-out may have an additional parasitic resistance, which is unfavorable for the steep subthreshold swing characteristic of the device, in a preferred embodiment, the source metal layer 111 and the drain metal layer 109 are formed on the surfaces of the first source region 102 and the first drain region 103, respectively, and completely encapsulate the first source region 102 and the second source region 104 and the first drain region 103 and the second drain region 105, respectively; the gate metal layer 110 is formed on top of the control gate 108; an interlayer dielectric layer 112 covering the source metal layer 111, the gate metal layer 110, the drain metal layer 109, and the inner sidewall 114;
the metal contact layer 113 penetrates through the interlayer dielectric layer 112 and is connected to the source metal layer 111, the gate metal layer 110 and the drain metal layer 109, respectively.
According to other embodiments of the present invention, there is further provided a method for manufacturing a mixed conduction mode peripheral gate transistor, for manufacturing a mixed conduction mode peripheral gate transistor according to any one of the preceding embodiments of the present invention, including:
forming the wrap-gate MOSFET device and the second source 104 and drain 105 regions; wherein the wrap-gate MOSFET device comprises the substrate 101, the first source region 102, and the first drain region 103; wherein the first source region 102 and the first drain region 103 are doped with the first ions; the second source region 104 and the second drain region 105 are respectively formed between the substrate 101 and the first source region 102, and between the substrate 101 and the first drain region 103, and the heights of the second source region 104 and the second drain region 105 are not lower than the height of the substrate 101 between the first source region 102 and the first drain region 103;
wherein the second drain region 105 is doped with the first ions, and the second source region 104 is doped with the second ions.
In one embodiment, a flow chart of a method for manufacturing the gate-all-around MOSFET device and the second source region 104 and the second drain region 105, and a method for manufacturing the gate-all-around MOSFET device with a hybrid turn-on mechanism is shown in fig. 2, the method specifically includes:
s11: providing the substrate 101;
s12: forming a sacrificial layer and the channel layer 106; the sacrificial layer is stacked on the substrate 101 at intervals from the channel layer 106; specifically, the material of the sacrificial layer is SiGe, and the material of the channel layer 106 is Si; in one embodiment, the sacrificial layer and the channel layer 106 are: a Si/SiGe stack having a crystal orientation <100>, each layer having a thickness of about 10-20nm;
in one embodiment, the sacrificial layer is lightly doped with the channel layer 106; specifically, the range of light doping of the Si/SiGe stack is: 1E13cm-3-1E15cm-3.
In other embodiments, the sacrificial layer and the channel layer 106 are undoped with ions;
s13: etching the sacrificial layer and the channel layer 106 to form a fin structure, controlling the length of a device channel to be about 50nm-100nm, and over-etching the substrate 101 on both sides of the fin structure along the first direction to form a first cavity and a second cavity; the first cavity and the second cavity are sequentially arranged along the first direction;
step S13, after forming the fin structure, further includes: forming an STI structure by using photolithography to perform STI isolation patterning; wherein the depth of photoetching is about 5nm-50nm, and the material of the STI structure is SiO2;
s14: forming a dummy gate structure 115, and etching two ends of the sacrificial layer along the first direction to form a cavity of the inner side wall 114; specifically, the material of the dummy gate structure 115 is polysilicon; the dummy gate structure 115 is formed by: atomic layer deposition, chemical vapor deposition or physical vapor deposition; the thickness of the dummy gate structure 115 is 50nm;
s15: forming the inner side wall 114; the inner side wall 114 is formed in the inner side wall 114 cavity; specifically, the material of the inner sidewall 114 is selected from SiO2, si3N4 or other low K dielectric material; the method for forming the inner sidewall 114 is similar to the method for forming the dummy gate structure 115, and is not described herein, as shown in fig. 3;
in one embodiment, step S16, the second source region 104 and the second drain region 105 specifically include:
s161: forming a patterned first mask layer; the patterned first mask layer covers the second cavity, the dummy gate structure 115, and the surface of the inner sidewall 114;
s162: filling the material of the second source region 104 in the first cavity to form the second source region 104, and removing the patterned first mask layer, as shown in fig. 4;
in one embodiment, the second source region 104 is doped with B ions at a concentration of about 1E21cm -3 ；
S163: forming a patterned second mask layer; the patterned second mask layer covers the second source region 104, the dummy gate structure 115, and the surfaces of the inner sidewalls 114; the second patterned masking layer and the first patterned masking layer are photoresist 116;
s164: depositing a material filling the second drain region 105 in the second cavity to form the second drain region 105, and removing the patterned second mask layer, as shown in fig. 5;
in one embodiment, the materials of the second source region 104 and the second drain region 105 are: siGe and Si are C;
wherein, the second source region 104 and the second drain region 105 of the device adopt SiGe/Si:C epitaxy, which is beneficial to increasing the band-to-band tunneling probability of channel materials.
In one embodiment, the second drain region 105 is doped with As ions at a concentration of about 1E18cm -3 。
In one embodiment, when forming the second source region 104 or the second drain region 105, the following method is adopted: in-situ epitaxy, atomic layer deposition or chemical vapor deposition.
In one embodiment, the method of highly doping the first source region 102 or the second source region 104 is selected from one of the following methods: an in-situ doping method, an ion implantation method or a solid source doping method.
S16: forming the second source region 104 and the second drain region 105; the second source region 104 is formed in the first cavity, and the second drain region 105 is formed in the second cavity;
s17: forming the first source region 102 and the first drain region 103; the first source region 102 and the first drain region 103 are formed on top of the second source region 104 and the second drain region 105, respectively;
in one embodiment, the materials of the first source region 102 and the first drain region 103 are: siGe and Si.
Because the first source region 102 and the first drain region 103 of the device adopt SiGe/Si: C epitaxy, stress is further applied to the surrounding gate nanowire/nanosheet channel, and carrier mobility of channel materials is increased. In one embodiment, the first source region 102 and the first drain region 103 are doped with As ions in situ at a concentration of about 1E21cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping ions further comprise: performing a rapid high temperature anneal and activating the implanted impurity (1050 ℃ C., 10 s)
S18: removing the dummy gate structure 115 and releasing the channel layer 106, as shown in fig. 6;
s19: the gate dielectric layer 107, the control gate 108, the source metal layer 111, the gate metal layer 110, the drain metal layer 109, the interlayer dielectric layer 112, and the metal contact layer 113 are formed. Specifically, the gate dielectric layer 107 is made of: siO2, si3N4 or high-K gate dielectric material; the material of the control gate 108 is selected from doped polysilicon, metallic cobalt, nickel, and other metals or metal silicides.
The gate dielectric layer 107 is grown by: conventional thermal oxidation, nitrogen-doped thermal oxidation, atomic layer deposition or chemical vapor deposition.
In one embodiment, the gate dielectric layer 107 is made of HfO2 and has a thickness of 1-5 nm; the gate material is TiN layer with the thickness of 50-200 nm;
next, according to an embodiment of the present invention, there is also provided an electronic device including the hybrid-on-mechanism boom transistor according to any one of the preceding embodiments of the present invention.
In addition, according to an embodiment of the present invention, a method for manufacturing an electronic device is provided, including a method for manufacturing a hybrid turn-on mechanism surrounding gate transistor according to any one of the foregoing embodiments of the present invention.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims (13)

1. A hybrid turn-on mechanism wrap gate transistor, comprising:
the gate-all MOSFET device comprises a substrate, a first source region and a first drain region; the first source region and the first drain region are arranged along a first direction; wherein, the first source region and the first drain region are doped with first ions; wherein the first direction characterizes a direction parallel to the substrate;
a second source region and a second drain region, the second source region is formed between the substrate and the first source region, the second drain region is formed between the substrate and the first drain region, and the heights of the second source region and the second drain region are not lower than the height of the substrate between the first source region and the first drain region;
wherein the second drain region is doped with a first ion, the second source region is doped with a second ion, and the type of the first ion is different from the type of the second ion.
2. The hybrid turn-on mechanism peripheral gate transistor of claim 1, wherein the thickness of the second source region and/or the second drain region is in the range of 5nm to 50nm.
3. The hybrid turn-on mechanism peripheral gate transistor of claim 1, wherein the first ions are P-type ions or N-type ions.
4. The hybrid turn-on mechanism peripheral gate transistor of claim 1, wherein the second ions are P-type ions or N-type ions.
5. The mixing guide of claim 1The on-cell peripheral gate transistor is characterized in that the ion concentration doped in the second source region and/or the second drain region is 1E16cm -3 -1E22cm -3 。
6. The hybrid turn-on mechanism surrounding gate transistor of claim 1, wherein the material of the second source region and the material of the second drain region are: binary or ternary compounds of groups II-VI, III-V or IV-IV.
7. The hybrid turn-on mechanism peripheral gate transistor of claim 6, wherein the material of the second source region and the material of the second drain region are Si, siGe or Ge.
8. The hybrid turn-on mechanism boom transistor of claim 1, wherein said boom MOSFET device further comprises:
a channel layer formed between the first source region and the first drain region and arranged at intervals in a direction away from the substrate;
the gate dielectric layer wraps part of the surface of the channel layer; the control gate wraps the surface of the gate dielectric layer;
the inner side wall is formed between the first source region and the gate dielectric layer and on the surface of the channel layer between the first drain region and the gate dielectric layer;
a source metal layer, a gate metal layer and a drain metal layer; the source electrode metal layer and the drain electrode metal layer are respectively formed on the surfaces of the first source region and the first drain region, and respectively fully wrap the first source region and the second source region and the first drain region and the second drain region; the grid metal layer is formed on the top end of the control grid;
an interlayer dielectric layer covering the source metal layer, the gate metal layer, the drain metal layer and the surface of the inner side wall;
and the metal contact layer penetrates through the interlayer dielectric layer and is respectively connected with the source electrode metal layer, the gate electrode metal layer and the drain electrode metal layer.
9. A method for manufacturing a mixed conduction mode peripheral gate transistor, for manufacturing a mixed conduction mode peripheral gate transistor according to any one of claims 1 to 8, comprising:
forming the surrounding gate MOSFET device, the second source region and the second drain region; the surrounding grid MOSFET device comprises a substrate, a first source region and a first drain region; the first source region and the first drain region are doped with the first ions; the second source region and the second drain region are respectively formed between the substrate and the first source region and between the substrate and the first drain region, and the heights of the second source region and the second drain region are not lower than the height of the substrate between the first source region and the first drain region;
the second drain region is doped with the first ions, and the second source region is doped with the second ions.
10. The method for manufacturing the mixed turn-on mechanism surrounding gate transistor of claim 9, wherein forming the surrounding gate MOSFET device and the second source region and the second drain region, in particular comprises:
providing the substrate;
forming a sacrificial layer and the channel layer; the sacrificial layer and the channel layer are stacked on the substrate at intervals;
etching the sacrificial layer and the channel layer to form a fin structure, and over-etching the substrate on two sides of the fin structure along the first direction to form a first cavity and a second cavity; the first cavity and the second cavity are sequentially arranged along the first direction;
forming a dummy gate structure, and etching two ends of the sacrificial layer along the first direction to form an inner side wall cavity;
forming the inner side wall; the inner side wall is formed in the inner side wall cavity;
forming the second source region and the second drain region; the second source region is formed in the first cavity, and the second drain region is formed in the second cavity;
forming the first source region and the first drain region; the first source region and the first drain region are respectively formed at the top ends of the second source region and the second drain region;
removing the dummy gate structure and releasing the channel layer;
and forming the gate dielectric layer, the control gate, the source metal layer, the gate metal layer, the drain metal layer, the interlayer dielectric layer and the metal contact layer.
11. The method for manufacturing the mixed turn-on mechanism surrounding gate transistor of claim 10, wherein forming the second source region and the second drain region specifically comprises:
forming a patterned first mask layer; the patterned first mask layer covers the second cavity, the dummy gate structure and the surface of the inner side wall;
filling the material of the second source region in the first cavity to form the second source region, and removing the patterned first mask layer;
forming a patterned second mask layer; the patterned second mask layer covers the second source region, the dummy gate structure and the surface of the inner side wall;
and forming a second drain region by depositing and filling the material of the second drain region in the second cavity, and removing the patterned second mask layer.
12. An electronic device comprising a hybrid turn-on mechanism peripheral gate transistor according to any one of claims 1-8.
13. A method for manufacturing an electronic device, comprising the method for manufacturing a mixed conduction mechanism wrap gate transistor according to any one of claims 9 to 11.
CN202211730768.5A 2022-12-30 2022-12-30 Mixed conduction mechanism surrounding grid transistor and manufacturing method thereof Pending CN116247099A (en)

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