WO2023125894A1 - Transistor schottky à source froide et son procédé de préparation - Google Patents

Transistor schottky à source froide et son procédé de préparation Download PDF

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Publication number
WO2023125894A1
WO2023125894A1 PCT/CN2022/143750 CN2022143750W WO2023125894A1 WO 2023125894 A1 WO2023125894 A1 WO 2023125894A1 CN 2022143750 W CN2022143750 W CN 2022143750W WO 2023125894 A1 WO2023125894 A1 WO 2023125894A1
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region
source
drain
metal
layer
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PCT/CN2022/143750
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English (en)
Chinese (zh)
Inventor
刘飞
谢晓鑫
刘晓彦
康晋锋
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北京大学
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66643—Lateral single gate silicon transistors with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7839—Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact

Definitions

  • the invention relates to the technical field of semiconductors, in particular to a cold source Schottky transistor and a preparation process thereof.
  • MOSFETs metal-oxide-semiconductor field-effect transistors
  • SS sub-threshold swing
  • the invention provides a cold-source Schottky transistor and its preparation process, which are used to solve the defect that the sub-threshold swing of the MOSFET cannot exceed 60mV/dec in the prior art, so that the power supply voltage and power consumption of the MOSFET device cannot be further reduced.
  • the invention provides a cold source Schottky transistor, comprising:
  • the source region comprising a first source region and a metal region connected to the first source region, the first source region being a heavily doped region;
  • drain region disposed on the substrate, the drain region is a heavily doped region, and the doping type of the drain region is opposite to that of the first source region;
  • a channel region disposed on the substrate, the channel region is located between the metal region and the drain region, and a gate dielectric is provided on the upper side and/or lower side of the channel region;
  • the gate is arranged on the gate dielectric.
  • the channel region is an intrinsic region or a lightly doped region.
  • the first source region is a P-type heavily doped region
  • the drain region is an N-type heavily doped region
  • the first source region is an N-type heavily doped region
  • the drain region is a P-type heavily doped region
  • the doping concentration of the first source region is 1e 19 cm -3 -1e 22 cm -3 , and the length of the first source region is 20 nm, so The thickness of the first source region is 10 nm.
  • the doping concentration of the drain region is 1e 19 cm -3 -1e 22 cm -3 , and the length of the drain region is 20 nm, and the drain region The thickness is 10nm.
  • the doping concentration of the channel region is 1e 15 cm -3 , the length of the channel region is 20nm, and the thickness of the channel region is 10nm .
  • the work function of the metal region is 5.0 eV
  • the length of the metal region is 10 nm
  • the thickness of the metal region is 10 nm.
  • the material of the first source region, the drain region and the channel region is silicon.
  • the present invention also provides a preparation process of a cold source Schottky transistor, comprising:
  • a gate is formed on the gate dielectric, a source is formed on the metal region and the first source region, and a drain is formed on the drain region.
  • the formation of a metal region on the source terminal includes:
  • Etching the metal layer to remove the metal layer on the channel region and part of the metal layer at the source end;
  • the hard mask and the metal layer on the surface of the hard mask are removed.
  • the formation of the first source region on the source end and the drain region on the drain end includes:
  • Pre-amorphization implantation doping is performed on the first source region material layer and the drain region material layer to form the first source region and the drain region.
  • the source region of the cold source Schottky transistor is composed of a heavily doped first source region and a metal region, and the metal region is in contact with the channel region, and the metal region is in contact with the channel region.
  • a Schottky barrier is formed between the channel regions. In the case of no gate voltage, because the Schottky barrier is very wide, it is difficult for electrons in the source region to tunnel through the Schottky barrier.
  • the forbidden band filters the electrons injected by the external electrodes, and the thermal current is greatly reduced in the forbidden band energy range of the first source region, so that the corresponding off-state current will be very low.
  • the Schottky barrier between the channel region and the metal region is lowered, making the Schottky barrier thinner until the low-energy region
  • the tunneling current will increase rapidly, and the electrons in the low-energy region of the source region tunnel through the Schottky barrier, so that the subthreshold swing can be lower than 60mV/dec.
  • Fig. 1 is the structural representation of the cold source Schottky transistor provided by the present invention
  • Fig. 2 is the energy band structure diagram of the cold source Schottky transistor provided by the present invention without applying a bias voltage
  • Fig. 3 is the energy band structure diagram of the cold source Schottky transistor under the condition of applying positive bias provided by the present invention
  • Fig. 4 is the graph of Id-Vg provided by the present invention.
  • Fig. 5 is a side view of the device generated in step S1 provided by the present invention.
  • Fig. 6 is a side view of the device generated in step S2 provided by the present invention.
  • Fig. 7 is a side view of the device generated in step S3 provided by the present invention.
  • Fig. 8 is a side view of the device generated in step S4 provided by the present invention.
  • Fig. 9 is a side view of the device generated in step S5 provided by the present invention.
  • Fig. 10 is a side view of the device generated in step S6 provided by the present invention.
  • Fig. 11 is a side view of the device generated in step S7 provided by the present invention.
  • Fig. 12 is a side view of the device generated in step S8 provided by the present invention.
  • Fig. 13 is a side view of the device generated in step S9 provided by the present invention.
  • FIG. 14 and FIG. 15 are respectively a top view and a side view of the device generated in step S10 provided by the present invention.
  • Fig. 16 is a side view of the device generated in step S11 provided by the present invention.
  • Fig. 17 is a side view of the device generated in step S12 provided by the present invention.
  • Fig. 18 is a side view of the device generated in step S13 provided by the present invention.
  • FIG. 19 and FIG. 20 are respectively a top view and a side view of the device generated in step S14 provided by the present invention.
  • FIG. 21 and FIG. 22 are respectively a top view and a side view of the device generated in step S15 provided by the present invention.
  • Figure 23 and Figure 24 are the top view and side view of the device generated in step S16 provided by the present invention, respectively;
  • Figure 25 and Figure 26 are the top view and side view of the device generated in step S17 provided by the present invention, respectively;
  • FIG. 27 and FIG. 28 are respectively a top view and a side view of the device generated in step S18 provided by the present invention.
  • FIG. 29 and FIG. 30 are respectively a top view and a side view of the device generated in step S19 provided by the present invention.
  • FIG. 31 and FIG. 32 are respectively a top view and a side view of the device generated in step S20 provided by the present invention.
  • Figure 33 and Figure 34 are respectively the top view and the side view of the device generated in step S21 provided by the present invention.
  • Figure 35 and Figure 36 are the top view and side view of the device generated in step S22 provided by the present invention, respectively;
  • Figure 37 and Figure 38 are the top view and side view of the device generated in step S23 provided by the present invention, respectively;
  • FIG. 39 and FIG. 40 are respectively a top view and a side view of the device generated in step S24 provided by the present invention.
  • Figure 41 and Figure 42 are the top view and side view of the device generated in step S25 provided by the present invention, respectively;
  • Figure 43 and Figure 44 are respectively the top view and the side view of the device generated in step S26 provided by the present invention.
  • Fig. 45 is a side view of the device generated in step S27 provided by the present invention.
  • Fig. 46 is a side view of the device generated in step S28 provided by the present invention.
  • Fig. 47 is a side view of the device generated in step S29 provided by the present invention.
  • FIG. 48 and FIG. 49 are respectively a top view and a side view of the device generated in step S30 provided by the present invention.
  • Figures 50-52 are respectively the top view, side view and cross-sectional view of the device generated in step S31 provided by the present invention.
  • 53-55 are the top view, side view and cross-sectional view of the device generated in step S32 provided by the present invention.
  • 56-58 are the top view, side view and cross-sectional view of the device generated in step S33 provided by the present invention.
  • Figure 59 and Figure 60 are respectively a side view and a cross-sectional view of the device generated in step S34 provided by the present invention.
  • Figure 61 and Figure 62 are respectively a side view and a cross-sectional view of the device generated in step S35 provided by the present invention.
  • Figure 63 and Figure 64 are respectively a side view and a cross-sectional view of the device generated in step S36 provided by the present invention.
  • Figure 65- Figure 67 are respectively the top view, side view and cross-sectional view of the device generated in step S37 provided by the present invention.
  • Fig. 68 is a side view of the device generated in step S38 provided by the present invention.
  • FIG. 69 and FIG. 70 are respectively a top view and a cross-sectional view of the device generated in step S39 provided by the present invention.
  • Fig. 71 and Fig. 72 are respectively the top view and the sectional view of the device that step S40 provided by the present invention generates;
  • FIG. 73 and FIG. 74 are respectively a top view and a cross-sectional view of the device generated in step S41 provided by the present invention.
  • Fig. 75 is a cross-sectional view of the device generated in step S42 provided by the present invention.
  • 76-78 are respectively the top view, side view and cross-sectional view of the device generated in step S43 provided by the present invention.
  • 101 substrate; 102: shielding oxide layer; 103: well region; 104: pad oxide layer;
  • 108 fin region; 109: etch barrier layer; 110: amorphous silicon; 111: amorphous carbon;
  • 112 gate pattern; 113: polyoxide; 114: second silicon nitride;
  • 125 TiAi-based alloy
  • 126 the first metal tungsten
  • 127 the second phosphosilicate glass
  • the cold source Schottky transistor and its manufacturing process of the present invention will be described below with reference to FIGS. 1 to 78 .
  • a cold source Schottky transistor provided by the present invention includes a substrate 101 , a source region, a drain region 4 , a channel region 3 , a source electrode, a drain electrode and a gate electrode.
  • the source region, the drain region 4 and the channel region 3 are all arranged on the substrate 101, wherein the source region includes a first source region 1 and a metal region 2, and the metal region 2 is connected to the first source region 1;
  • the channel region 3 is located between the metal region 2 and the drain region 4, and the upper and/or lower sides of the channel region 3 are provided with a gate dielectric 5, the source is arranged on the source region, and the drain is arranged on the drain region 4 , the gate is arranged on the gate dielectric 5, and the first source region 1 is a heavily doped region, and the drain region 4 is a heavily doped region, so that the Fermi level of the first source region 1 and the drain region 4 in the price band. And the doping types of the first source region 1 and the drain region 4 are opposite.
  • the source region is composed of a heavily doped first source region 1 and a metal region 2, and the metal region 2 is in contact with the channel region 3, a Schottky barrier is formed between the metal region 2 and the channel region 3, and the gate is not applied.
  • a Schottky barrier is formed between the metal region 2 and the channel region 3, and the gate is not applied.
  • the Schottky barrier is very wide, it is difficult for the electrons in the source region to tunnel through the Schottky barrier, and because the forbidden band of the first source region 1 filters the electrons injected by the external electrode, in the first
  • the thermal current is greatly reduced in the forbidden band energy range of the source region 1, so that the corresponding off-state current will be very low.
  • the Schottky barrier between the channel region 3 and the metal region 2 is lowered, making the Schottky barrier thinner until When the Schottky barrier in the low-energy region is thin enough, the tunneling current will increase rapidly, and the electrons in the low-energy region of the source region tunnel through the Schottky barrier, so that the subthreshold swing can be lower than 60mV/dec.
  • the gate voltage when the gate voltage is applied, the electrons in the high-energy region of the Schottky barrier decrease, and no current will be generated in the high-energy region; at this time, the low-energy region of the Schottky barrier becomes narrower, and the electrons in the low-energy region of the source region Tunneling the Schottky barrier, the tunneling current increases rapidly, and the subthreshold swing is lower than 60mV/dec.
  • the Schottky barrier formed between the metal region 2 and the first source region 1 is very thin, it is almost an ohmic contact, so the metal region 2 and the first source region The Schottky barrier between 1 has little effect on the current flow.
  • the cold source is realized by the junction formed by the first source region 1 and the metal region 2 .
  • the cold source Schottky transistor can achieve a relatively large on-state current compared with the tunneling field effect transistor TFETs, and can achieve a higher switching rate than the negative capacitance field effect transistor NC-FETs, and there is no hysteresis;
  • the main body of the device uses silicon as the material.
  • the entire device structure has only been modified and adjusted in the source area, that is, the original N (or P) type semiconductor is replaced by a P (or N) type semiconductor + metal (Metal)
  • the structure is highly compatible with existing MOSFETs in terms of materials and processing technology, which increases the potential for practical applications; and, compared with P-Metal-N cold source transistors, this cold source Schottky transistor has no source The effect of electric phonon scattering brought by the N-type part of the region can realize more efficient cold source injection.
  • the channel region 3 can be an intrinsic region or a lightly doped region, so that the Schottky barrier formed between the channel region 3 and the metal region 2 is very wide, and when no gate voltage is applied In the case of , it is difficult for the electrons in the source region to tunnel through the Schottky barrier, thereby reducing the corresponding off-state current.
  • the first source region 1 can be a P-type heavily doped region
  • the drain region 4 can be an N-type heavily doped region, or the first source region 1 can be an N-type heavily doped region , the drain region 4 may be a P-type heavily doped region.
  • the doping concentration of the first source region 1 may be 1e 19 cm ⁇ 3 to 1e 22 cm ⁇ 3 , the length of the first source region 1 is 20 nm, and the thickness of the first source region 1 is 10 nm.
  • the doping concentration of the drain region 4 is 1e 19 cm -3 -1e 22 cm -3 , the length of the drain region 4 is 20nm, and the thickness of the drain region 4 is 10nm.
  • the doping concentration of the first source region 1 may be 1e 21 cm -3 (that is, 1*1021 per cubic centimeter), and the doping concentration of the drain region 4 may be 1e 19 cm -3 , specifically, the first source region
  • the doping concentration of the drain region 1 and the drain region 4 can be determined according to the material of the first source region and the drain region and the material of the substrate, and can be specifically determined according to the actual situation.
  • the channel region 3 may be a lightly doped region, and the doping concentration of the channel region 3 is 1e 15 cm ⁇ 3 , the length of the channel region 3 is 20 nm, and the thickness of the channel region 3 is 10 nm.
  • the channel region 3 may be lightly doped with N-type or lightly P-type according to the work function of the metal region.
  • the material of the gate dielectric 5 may be hafnium oxide, and the thickness of the gate dielectric 5 may be 1.5 nm.
  • the cold source Schottky transistor may include two gates, and the two gates are respectively arranged on the two gate dielectrics 5, so that under the action of the double gates, the gate control capability is effectively improved, and the device can be more efficient. well turned on and off.
  • the left end of the first source region 1 is a source contact
  • the right end of the drain region 4 is a drain contact
  • the upper and lower sides of the gate dielectric 5 are gate contacts, wherein the work function of the gate contact can be 4.5 eV.
  • the work function of the metal region 2 may be 5eV
  • the length of the metal region 2 may be 10 nm
  • the thickness of the metal region may be 10 nm.
  • the work function, length and thickness of the metal region are not specifically limited, but may be determined according to the actual material selected.
  • first source region 1 and the metal region 2 may be in contact horizontally, and the first source region 1 and the metal region 2 may also be in contact vertically or along other directions (that is, contact at an angle).
  • the material of the substrate can be silicon (Si) or germanium (Ge), or a III-V group material
  • the first source region can also be silicon (Si) or germanium (Ge), a III-V group material
  • III-V materials include: InSb, GaSb, InAs, AlSb, AlAs, GaAs, InGaAs, InAlAs, InP, InGaP, etc.
  • the material of the metal region can be Au, Co, Cu, Pd, Pt, Ti, W , TiN, NiSi 2 and so on.
  • the first source region 1, metal region 2, channel region 3 and drain region 4 have a uniform Fermi level; as shown in Figure 3, when the drain is applied When a voltage of 0.2V is applied to the gate and a voltage of 1V is applied to the gate, the first source region 1, metal region 2, channel region 3 and drain region 4 no longer have a uniform Fermi level, resulting in the formation of electrons and holes.
  • the applied forward bias reduces the height of the Schottky barrier
  • the diffusion movement of the carriers is greater than the drift movement
  • the carriers in the source region are injected into the channel region 3 and recombined while diffusing
  • the carriers in the channel region 3 are injected into the drain region 4 and diffused while recombining to generate a certain concentration gradient, forming a steady state distribution.
  • Figure 4 is the approximate Id-Vg curve obtained by simulation in Sentaurus TCAD, that is, the influence diagram of the gate voltage on the current, and the more bent lines in Figure 4 are the source region including the first A plot of drain current versus gate voltage for a cold-source Schottky transistor with source region 1 and metal region 2; the line with relatively few bends is the source region for a Schottky transistor whose source region includes only metal region 2 A plot of drain current versus gate voltage.
  • the subthreshold swing is lower than 60Mv/dec near 0.6V, and the current changes by about 3 orders of magnitude between 0.6V-0.7V, which shows that the tunneling current rapid increase.
  • the drain current is dominated by tunneling current rather than thermal current.
  • the on-state current is 1 to 2 orders of magnitude lower than that of traditional MOSFETs, but it can be passed Better on-state current characteristics are achieved by adjusting the work function of the gate contact, the work function of the metal at the source end, and the doping concentration of the first source region 1 .
  • the manufacturing process of the cold source Schottky transistor provided by the present invention is described below, and the manufacturing process of the cold source Schottky transistor described below and the cold source Schottky transistor described above can be referred to in correspondence.
  • the preparation process of a cold source Schottky transistor provided by the present invention includes:
  • a gate is formed on the gate dielectric, a source is formed on the metal region and the first source region 1 and a drain is formed on the drain region.
  • forming the metal region on the source end includes:
  • step S20 forming a layer of hard mask on the channel region, source terminal and drain terminal;
  • step S21 setting a pattern layer 117 on the hard mask
  • step S22 etching the hard mask without the pattern layer 117 to expose the source terminal and part of the channel region;
  • step S23 forming a layer of metal layer 118 on the entire device surface
  • step S24 etching the metal layer 118, removing the metal layer on the channel region and part of the metal layer at the source end, leaving a certain thickness of the channel region near the source end. a metal layer to form a metal region;
  • step S25 removing the hard mask and the metal layer attached to the surface of the hard mask.
  • a layer of second amorphous carbon 116 (Amorphous carbon) is grown on the channel region, the source terminal and the drain terminal as a hard mask, and the surface of the hard mask is polished by chemical mechanical polishing (CMP);
  • a photoresist pattern layer 117 is provided on the hard mask by a photolithography process to expose the source end and part of the channel region;
  • PVD physical vapor deposition
  • Etching the metal layer 118 removing the metal layer on the channel region and part of the metal layer at the source end, so that a certain thickness of the metal layer is left on the side of the channel region near the source end to form a metal region;
  • the metal layer on the surface of the hard mask refers to the redundant metal layer.
  • the redundant metal layer can be removed simultaneously, and no additional means are needed to remove the redundant metal layer. Therefore, when removing the redundant metal layer , will not affect the metal layer on the wall of the channel region.
  • forming the first source region 1 on the source end and forming the drain region on the drain end includes:
  • step S26 epitaxially grow silicon carbide 119 on the exposed source and drain ends of the well region 103 to form a first source region material layer and a drain region material layer;
  • step S27 performing pre-amorphization implantation doping on the first source region material layer and the drain region material layer to form the first source region and the drain region.
  • silicon carbide 119 (SiC) is epitaxially grown in the well region 103 (silicon region) exposed at the source end and the drain end, thereby forming a first source region material layer and a drain region material layer; then the first source region material layer Pre-amorphization and doping PAI (Silicon Pre-Amorphization Implant) is performed on the material layer of the drain region to form a layer of uniform, low-resistance silicon, that is, to form the first source region and the drain region.
  • the first source region material layer and the drain region material layer may be implanted with ions to form a metal silicide to reduce the contact resistance of the first source region and the drain region.
  • the doping method of the first source region and the drain region is not limited, and may be determined according to actual conditions.
  • forming the well region 103 on the substrate 101 includes:
  • step S1 grow a barrier oxide layer 102 on the silicon wafer (substrate 101); here, a barrier oxide layer can be grown on the silicon wafer by thermal oxidation or chemical vapor deposition 102.
  • step S2 perform ion implantation on the silicon wafer by an ion implanter, and form a well region 103 on the silicon wafer;
  • boron ions can be implanted into the silicon wafer by an ion implanter to form a P-well on the silicon wafer, and the peak of the implanted ion concentration can be controlled to be located in the middle region of the silicon wafer.
  • step S3 remove the shielding oxide layer 102 by etching, and then perform rapid annealing on the silicon wafer to repair the crystal lattice of the silicon wafer, thereby activating the well region 103 .
  • forming a channel region, a source terminal and a drain terminal on the well region 103 includes:
  • a channel region, a source terminal and a drain terminal are formed in the substrate 101 .
  • forming shallow trench isolation in the substrate 101 includes:
  • step S4 grow a pad oxide layer 104 (Pad Oxide) on the substrate 101;
  • first silicon nitride 105 Silicon Nitride, SiN
  • CVD chemical vapor deposition
  • step S5 etching the first silicon nitride 105 downward until the pad oxide layer 104 is exposed, and then removing the isolation pattern 106;
  • step S6 use the first silicon nitride 105 as a hard mask to continue etching downward until the well region 103 is etched to form shallow trenches and fin regions 108 (Fin);
  • step S7 filling the shallow groove with tetraethyl orthosilicate 107 (TEOS) by means of chemical vapor deposition (CVD);
  • TEOS tetraethyl orthosilicate 107
  • CVD chemical vapor deposition
  • step S8 grinding the tetraethyl orthosilicate 107 by chemical mechanical polishing (CMP) until the tetraethyl orthosilicate 107 is level with the first silicon nitride 105 in the fin region 108 (Fin) together;
  • CMP chemical mechanical polishing
  • step S9 use hot phosphoric acid solution to remove the remaining first silicon nitride 105, and then use etching to remove part of the orthosilicate around the fin region 108 (Fin), leaving The orthosilicate 107 in the region 103 serves as shallow trench isolation (STI, Shallow Trench Isolation).
  • STI shallow trench isolation
  • forming a channel region, a source terminal and a drain terminal in the substrate 101 includes:
  • step S10 growing an oxide layer as an etch stop layer 109 (ESL, etch stop layer) on the fin region 108 (Fin) by means of thermal oxidation;
  • ESL etch stop layer
  • step S11 Deposit a thick layer of amorphous silicon 110 (Amorphous Silicon) by chemical vapor deposition, and smooth the layer of amorphous silicon 110 by chemical mechanical polishing (CMP);
  • CMP chemical mechanical polishing
  • step S12 growing a layer of first amorphous carbon 111 as a hard mask
  • step S13 forming a gate pattern 112 on the first amorphous carbon 111 by photolithography; here, a layer of the first amorphous carbon 111 can be grown by chemical vapor deposition or physical vapor deposition.
  • step S14 etching the hard mask formed by the first amorphous carbon 111 outside the gate pattern 112, continuing to etch downward the amorphous silicon 110 outside the gate pattern 112, removing the gate pattern 112 and the remaining first amorphous carbon 111;
  • step S15 growing a layer of polyoxide 113 on the amorphous silicon 110 by means of thermal oxidation;
  • step S16 depositing a layer of second silicon nitride 114;
  • step S17 etching the second silicon nitride 114 to form a second silicon nitride 114 spacer on the side walls of the fin region 108 and the amorphous silicon 110 to form a channel region , source area, drain area;
  • step S18 forming a masking pattern 115 covering the channel region by photolithography
  • step S19 remove the exposed fin region 108 (Fin) of the source region and the drain region through spacer etching, and then remove the masking pattern 115 to form a channel region, source and sink.
  • forming the gate dielectric in the channel region includes:
  • step S28 form a layer of silicon oxide 120 (Silicon Oxide) and a third silicon nitride 121 (Silicon Nitride) on the surface of the channel region, source region, drain region and amorphous silicon 110 as contacts Stop layer for hole etching;
  • step S29 deposit a thick first phospho-silicate glass 122 (PSG, Phospho-Silicate Glass) on the surface of the third silicon nitride 121, to serve as pre-metal medium (PMD, pre -Metal-Dielectric);
  • PSG Phospho-Silicate Glass
  • step S30 use chemical mechanical polishing (CMP) to polish the pre-metal dielectric layer until the third silicon nitride 121, silicon oxide 120 and polyoxide 113 on the channel region Grinded away, exposing the amorphous silicon 110 inside;
  • CMP chemical mechanical polishing
  • step S31 removing the amorphous silicon 110 in the channel region by etching to expose the etch barrier layer 109 in the fin region 108 ;
  • step S32 continue to remove the etching barrier layer 109 by etching; here, the etching barrier layer 109 on the sidewall of the fin region 108 may be removed by etching.
  • step S33 form an oxide layer on the surface of the fin region 108 through a low-temperature oxidation reaction as a bottom interface layer 123 (BIL, bottom interface layer), so that the high dielectric medium 124 is at the bottom interface Growth on layer 123;
  • BIL bottom interface layer
  • step S34 Deposit a layer of high-k HfO 2 as the dielectric 124 by atomic layer deposition (ALD, Atomic Layer Deposition) process to form a gate dielectric.
  • ALD Atomic Layer Deposition
  • a layer of high dielectric hafnium oxide can be deposited only on the upper surface of the bottom interface layer 123 as the gate dielectric.
  • the gate is formed on the gate dielectric
  • the source is formed on the metal region and the first source region
  • the drain is formed on the drain region, including:
  • step S35 use atomic layer deposition (ALD, Atomic Layer Deposition) process to deposit a layer of work function metal TiAi base alloy 125 on the dielectric 124 layer as gate (gate TiAl);
  • ALD Atomic Layer Deposition
  • work The functional metal can be selected according to device characteristics, and is not limited to TiAi-based alloy 125.
  • step S36 deposit a thick layer of first metal tungsten 126 by means of physical vapor deposition (PVD), and the first metal tungsten 126 is filled in the cavity of the work function metal;
  • PVD physical vapor deposition
  • step S37 smoothen the metal tungsten by means of chemical mechanical polishing (CMP), so that the surface of the first metal tungsten 126 is flush with the surface of the first phosphosilicate glass 122 layer;
  • CMP chemical mechanical polishing
  • step S38 depositing a second layer of phosphosilicate glass 127;
  • step S39 providing a source-drain contact pattern 128 on the second phosphosilicate glass 127 by photolithography to expose the corresponding positions of the first source region and the drain region;
  • step S40 etch the second phosphosilicate glass 127 at the exposed parts corresponding to the source region and the drain region until the barrier layer of silicon nitride is exposed; and etch the corresponding part of the channel region The second phosphosilicate glass 127, until the first metal tungsten 126 in the channel region is exposed;
  • step S41 removing the third silicon nitride 121 and silicon oxide 120 corresponding to the first source region and drain region, exposing the silicon carbide 119 in the first source region and drain region;
  • step S42 Deposit a thick layer of second metal tungsten 129 by means of physical vapor deposition (PVD), and the second metal tungsten 129 will be filled in the cavities of the source contact and the drain contact;
  • PVD physical vapor deposition
  • step S43 Polish the second metal tungsten 129 through the process of chemical mechanical polishing (CMP), so that the second metal tungsten 129 forms the gate, source and drain, and completes the cold source Schott Fabrication of base transistors.
  • CMP chemical mechanical polishing

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

La présente invention concerne un transistor Schottky à source froide et son procédé de préparation. Le transistor Schottky à source froide comprend un substrat (101), une région de source, une région de drain (4), une région de canal (3), une électrode de source, une électrode de drain et une électrode de grille, la région de source étant disposée sur le substrat (101), la région de source comprenant une première région de source (1) et une région métallique (2) connectée à la première région de source (1), et la première région de source (1) étant une région fortement dopée ; la région de drain (4) est disposée sur le substrat (101), la région de drain (4) est une région fortement dopée, et le type de dopage de la région de drain (4) est opposé à celui de la première région de source (1) ; la région de canal (3) est disposée sur le substrat (101), la région de canal (3) est située entre la région métallique (2) et la région de drain (4), et un diélectrique d'électrode de grille (5) est disposé sur le côté supérieur et/ou le côté inférieur de la région de canal (3) ; l'électrode de source est disposée sur la région de source ; l'électrode de drain est disposée sur la région de drain (4) ; et l'électrode de grille est disposée sur le diélectrique d'électrode de grille (5).
PCT/CN2022/143750 2021-12-31 2022-12-30 Transistor schottky à source froide et son procédé de préparation WO2023125894A1 (fr)

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CN114512546A (zh) * 2021-12-31 2022-05-17 北京大学 冷源肖特基晶体管及其制备工艺
CN115101599A (zh) * 2022-05-18 2022-09-23 北京大学 肖特基晶体管、二极管、冷源半导体结构及其制备方法

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CN109560128A (zh) * 2018-11-07 2019-04-02 南通大学 隧穿场效应晶体管
CN112424917A (zh) * 2018-06-06 2021-02-26 港大科桥有限公司 具有冷源极的金属氧化物半导体场效应晶体管
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