TW202416508A - 具有低漏電流且預留閘極長度的金氧半場效電晶體結構 - Google Patents

具有低漏電流且預留閘極長度的金氧半場效電晶體結構 Download PDF

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TW202416508A
TW202416508A TW112121378A TW112121378A TW202416508A TW 202416508 A TW202416508 A TW 202416508A TW 112121378 A TW112121378 A TW 112121378A TW 112121378 A TW112121378 A TW 112121378A TW 202416508 A TW202416508 A TW 202416508A
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盧超群
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新加坡商發明創新暨合作實驗室有限公司
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Abstract

金氧半場效電晶體結構包含一半導體基底、一閘極結構、一通道區、一溝槽、一隔離區、一第一導電區及一P-N接面。該半導體基底具有一半導體表面。該閘極結構位於該半導體表面上方。該通道區位於該閘極結構下方。該溝槽形成於該半導體表面下方且鄰近該通道區。該隔離區位於該溝槽中。該第一導電區具有一第一摻雜類型，其中該第一導電區位於該隔離層上方並電耦接至該通道區。該P-N接面從該隔離區沿著該第一導電區的邊緣向上延伸。

Description

具有低漏電流且預留閘極長度的金氧半場效電晶體結構
本發明是有關於一種金氧半場效電晶體(metal-oxide-semiconductor field-effect transistor)結構，尤指一種具有垂直屏蔽層的金氧半場效電晶體結構，其中該垂直屏蔽層可阻擋漏電流從而減少穿隧效應(punch through effect)的可能性。
低功耗積體電路(low power integrated circuit)產業的成功主要歸功於互補金氧半(complementary metal-oxide-semiconductor, CMOS)技術，其中積體電路的主要元件是金氧半場效電晶體(metal-oxide-semiconductor field-effect transistor, MOSFET)。雖然鰭式場效電晶體(FinFET)的先進技術節點(例如3-10奈米(nm))經常用於高效能運算應用(例如人工智慧(artificial intelligence, AI)、中央處理器(central processing unit, CPU)、圖形處理器(graphics processing unit, GPU)等)，但平面金氧半場效電晶體的成熟技術節點(例如12-30nm)仍然廣泛應用在許多積體電路(integrated circuit, IC)應用(如電源管理IC、動態隨機存取記憶體(DRAM)和微控制器單元(microcontroller unit, MCU)晶片)中。
圖1是說明現有技術中的互補金氧半電晶體100的示意圖，其包含一p型金氧半(PMOS)電晶體102和一n型金氧半(NMOS)電晶體104。在絕緣體(例如氧化物、氧化物/氮化物或某些高介電(high-k)材料等)上使用某種導電材料(如金屬、多晶矽或金屬化矽(polyside)等)的電晶體閘極結構形成在矽表面的頂部上，並且互補金氧半電晶體100通過使用絕緣材料(例如氧化物、氧化物/氮化物或其他高介電材料)與其他電晶體隔離。n型金氧半電晶體104有源極/汲極區1042、1044，其中n型金氧半電晶體104的源極/汲極區1042、1044是通過離子植入加上熱退火技術將n型摻雜劑注入一p井106(或p型基板)中形成，也就是在p井106中形成兩個分離的n+/ p 接面區(junction area)。另外，p型金氧半電晶體102也有源極/汲極區1022、1024，其中p型金氧半電晶體102的源極/汲極區1022、1024都也是通過離子植入加上熱退火技術將p型摻雜劑離子植入一n井108中形成，也就是在n井108中形成兩個分離的n+/ p 接面區。另外，如圖1所示，P-SSRW為P型超陡後退井(super-steep retrograde well)，N-SSRW為N型超陡後退井，LDD為輕摻雜汲極(lightly doped drain)，以及STI為淺溝槽隔離(shallow trench isolation)。
然而，在前述提到的熱退火製程中，注入的n型摻雜劑或p型摻雜劑將不可避免地向不同方向擴散而擴大源極區和汲極區的面積。源極區和汲極區由於熱退火製程擴大的面積越大，則源極區和汲極區之間的有效通道長度Leff就越短，而有效通道長度Leff的減少會產生短通道效應(short channel effect, SCE)。當有效通道長度Leff與源極/汲極接面空乏寬度(depletion width)相當時，金氧半電晶體可視為短路。當有效通道長度Leff進一步降低時，汲極電流最終無法關閉以及閘極無法控制電荷，此時所謂的穿隧效應(punch-through effect)給小型化設備帶來了嚴重的問題。因此，為了減少短通道效應的影響，通常會保留較長的閘極長度以因應熱退火製程所引起的n型摻雜劑或p型摻雜劑的擴散。以25nm(Lambda或λ)的技術節點為例，預留的閘極長度為60-100nm。因此，金氧半電晶體的尺寸無法按比例縮小。
目前使用12-30nm成熟技術節點製造的平面金氧半場效電晶體也引入了其他或變得更加嚴重的問題：(1)所有接面漏電流(junction leakage)都是由接面形成製程所引起的，例如因為離子植入產生的晶格缺陷，所以源極/汲極區中額外的損壞(例如電洞和電子的捕獲)將較難緩解，導致漏電流會通過源極/汲極區的週邊和底部區發生，也就是說在基底或井中形成輕摻雜汲極(lightly doped drain, LDD)，在p型基底中形成n+源極/汲極區，以及在n井中形成p+源極/汲極區都變得越來越難以控制；(2)另外，由於離子植入形成輕摻雜汲極(或形成N型金氧半中的n+/p接面，或形成P型金氧半中的p+/n接面)的工作原理類似於轟擊以便從基底的頂部向下插入離子到基底，所以很難創建從源極/汲極區到通道區/基底本體區的具有較少缺陷的均勻材料接面，如此將導致摻雜劑濃度在垂直方向上的分佈不均勻，也就是說摻雜劑濃度將從具有較高的摻雜濃度的頂面逐漸過渡到具有摻雜濃度較低的到接面；(3)僅使用傳統的閘極、間隔層和離子植入形成的自對準方法，越來越困難將輕摻雜汲極的邊緣與閘極的邊緣完美的對準。另外，去除離子植入損傷的熱退火製程必須依靠高溫加工技術，例如利用各種能源的快速熱退火方法或其他熱製程。而由此產生的一個問題是由於閘極至源極/汲極區中形成的閘極二極體結構而引起閘極感應汲極洩漏(gate-induced drain leakage, GIDL)電流變得難以控制，導致漏電流很難減少(儘管事實上應將閘極感應汲極洩漏電流最小化以減少漏電流)；而由此產生的另一個問題是有效通道長度Leff難以控制，導致很難最小化短通道效應。
因此，本發明提供實現新型平面電晶體結構的幾個新概念，其大大改善甚至解決了上述大部分問題，例如最小化漏電流、提高通道導通性能和控制、優化源極/汲極區的功能(例如通過無縫有序晶格匹配改善其與金屬互連的傳導性以及與通道區最接近的物理完整性)。
本發明的一實施例提供一種金氧半場效電晶體(metal-oxide-semiconductor field-effect transistor, MOSFET)結構。該金氧半場效電晶體結構包含一半導體基底、一閘極結構、一通道區、一溝槽、一隔離區、一第一導電區及一P-N接面(P-N junction)。該半導體基底具有一半導體表面。該閘極結構位於該半導體表面上方。該通道區位於該閘極結構下方。該溝槽形成於該半導體表面下方且鄰近該通道區。該隔離區位於該溝槽中。該第一導電區具有一第一摻雜類型，其中該第一導電區位於該隔離層上方並電耦接至該通道區。該P-N接面從該隔離區沿著該第一導電區的邊緣向上延伸。
在本發明的一實施例中，該金氧半場效電晶體結構另包含一垂直屏蔽層(vertical screening layer)，其中該垂直屏蔽層與該第一導電區接觸，且該垂直屏蔽層的摻雜類型與該第一導電區的第一摻雜類型不同。
在本發明的一實施例中，該第一導電區和該垂直屏蔽層均獨立於該半導體基底，且該P-N接面位於該第一導電區和該垂直屏蔽層之間。
在本發明的一實施例中，該金氧半場效電晶體結構為一平面n型金氧半(n-type metal-oxide-semiconductor, NMOS)電晶體，該垂直屏蔽層為一p型垂直屏蔽層，該第一導電區域包含一n型輕摻雜汲極(lightly doped drain, LDD)區和一n型重摻雜區，該n型輕摻雜汲極區與該p型垂直屏蔽層接觸，以及該n型重摻雜區與該n型輕摻雜汲極區接觸。
在本發明的一實施例中，該p型垂直屏蔽層的摻雜濃度與該通道區的摻雜濃度相同或實質上相同。
在本發明的一實施例中，該n型輕摻雜汲極區的邊緣與該閘極結構的邊緣對齊或實質上對齊。
在本發明的一實施例中，該第一導電區域包含一含金屬區，且該含金屬區位於該溝槽內並緊鄰該n型重摻雜區域。
在本發明的一實施例中，該隔離區包含一垂直氧化層、一水平氧化層和一絕緣插銷。該垂直氧化層覆蓋該溝槽的一側壁，以及該水平氧化層覆蓋該溝槽的底部。該絕緣插銷位於該溝槽內和該水平氧化層上方。
在本發明的一實施例中，該垂直氧化層的邊緣位於該閘極結構的下方，且該垂直氧化層的邊緣與該閘極結構的邊緣之間的距離為該閘極結構的長度的1/10～1/4。
在本發明的一實施例中，該金氧半場效電晶體結構另包含一淺溝槽隔離區(shallow trench isolation region)，其中該淺溝槽隔離區圍繞該第一導電區的側壁，且該第一導電區的底部通過該隔離區與該半導體基底隔離。
本發明的另一實施例提供一種金氧半場效電晶體結構。該金氧半場效電晶體結構包含一半導體基底、一第一溝槽、一第二溝槽、一第一隔離區、一第二隔離區、一閘極結構、一通道區、一汲極區及一源極區。該半導體基底具有一半導體表面。該第一溝槽和該第二溝槽形成在該半導體表面下方。該第一隔離區位於該第一溝槽中以及該第二隔離區位於該第二溝槽中。該閘極結構位於該半導體表面上方，其中該閘極結構包含一閘極隔離層和一閘極導電層，該閘極隔離層位於該半導體表面上方，以及該閘極導電層位於該閘極隔離層上方。該通道區位於該閘極結構下方。該汲極區具有一第一摻雜類型且在該第一隔離區上方。該源極區具有該第一摻雜類型且在該第二隔離區上方。該第一隔離區的邊緣與該第二隔離區的邊緣之間的距離小於該閘極結構的長度。
在本發明的一實施例中，該第一隔離區的邊緣與該第二隔離區的邊緣之間的距離為該閘極結構的長度的1/2～4/5。
在本發明的一實施例中，該金氧半場效電晶體結構另包含一垂直屏蔽層，其中該垂直屏蔽層與該汲極區接觸，且該第一垂直屏蔽層的摻雜類型不同於該汲極區的第一摻雜類型。
在本發明的一實施例中，該第一垂直屏蔽層的摻雜濃度與該通道區的摻雜濃度相同或實質上相同。
在本發明的一實施例中，該第一垂直屏蔽層和該汲極區之間具有P-N接面，以及該P-N接面從該第一隔離區向上延伸且與該閘極結構的邊緣對齊或實質上對齊。
在本發明的一實施例中，該通道區、該第一垂直屏蔽層和該汲極區獨立於該半導體基底。
本發明的另一實施例提供一種被淺溝槽隔離區包圍的金氧半場效電晶體結構。該金氧半場效電晶體結構包含一半導體基底、一第一溝槽、一第二溝槽、一第一隔離區、一第二隔離區、一閘極結構、一通道區、一汲極區、一源極區及一第一垂直屏蔽層。該半導體基底具有一半導體表面。該第一溝槽和該第二溝槽形成在該半導體表面下方。該第一隔離區位於該第一溝槽中以及該第二隔離區位於該第二溝槽中。該閘極結構位於該半導體表面上方。該通道區位於該閘極結構下方。該汲極區具有一第一摻雜類型且在該第一隔離區上方。該源極區具有該第一摻雜類型且在該第二隔離區上方。該第一垂直屏蔽層介於該汲極區和該通道區之間，其中該第一垂直屏蔽層的摻雜類型不同於該汲極區的第一摻雜類型，且該第一垂直屏蔽層和該汲極區獨立於該半導體基底。
在本發明的一實施例中，該第一垂直屏蔽層的水平厚度為2～5奈米(nm)。
在本發明的一實施例中，該汲極區的三個側壁通過該淺溝槽隔離區與該半導體基底隔離，且該第一導電區的底部通過該第一隔離區與該半導體基底隔離。
在本發明的一實施例中，該金氧半場效電晶體結構是由製程節點λ形成，且當該λ介於12nm～30nm之間時，該閘極結構的長度在1.2λ～2.4λ之間。
請參照圖2A，圖2B，圖2C，圖2D，圖3，圖4，圖5，圖6，圖7，圖8，圖9，圖10，圖11，圖12，圖13，圖14，圖15，圖16，其中圖2A是本發明的一實施例所公開的一種具有低漏電流且預留閘極長度(reserved gate length)的金氧半場效電晶體(metal-oxide-semiconductor field-effect transistor, MOSFET)結構的製造方法的流程圖。該製造方法的詳細步驟如下：
步驟10：     開始；
步驟20：     在一p型基底(或一p型井)200的基礎上，定義該金氧半場效電晶體的主動區；
步驟30：     形成該金氧半場效電晶體的閘極區(或閘極結構)；
步驟40：     形成該金氧半場效電晶體的源極區和汲極區，其中一垂直屏蔽層是靠著該源極區(或該汲極區)形成；
步驟50：     結束。
請參照圖2B和圖3，步驟20包含：
步驟102：   生長一襯墊氧化層204並沉積一襯墊氮化層206；
步驟104：   定義該金氧半場效電晶體的主動區，並移除對應於該主動區外的原始水平表面(original horizontal surface, OHS)的部分基底材料(例如矽)以形成溝槽；
步驟106：   沉積一氧化層並使用化學機械研磨(chemical mechanical polishing, CMP)技術移除多餘的氧化層以形成一淺溝槽隔離(STI) 402。
接著請參照圖2C和圖4，圖5，圖6，步驟30包含：
步驟108：   形成圖案化光阻403，以定義該閘極區的長度Lgate；
步驟110：   蝕刻掉對應該閘極區的襯墊氧化層204和襯墊氮化層206以形成一凹陷404並使得凹陷404對應的原始水平表面OHS露出來；
步驟112：   移除圖案化光阻403；
步驟114：   在凹陷404內形成一閘極介電材料502；
步驟116：   在凹陷404內沉積一閘極材料504，然後回蝕閘極材料504；
步驟118：   沉積一複合覆蓋層506，並通過該化學機械研磨技術拋光複合覆蓋層506。
最後請參照圖2D和圖7，圖8，圖9，圖10，圖11，步驟40包含：
步驟120：   移除淺溝槽隔離402與該閘極區之間的襯墊氧化層204和襯墊氮化層206；
步驟122：   在該閘極區的側壁上形成間隔層；
步驟124：   蝕刻露出的矽；
步驟126：   熱生長一氧化物-3層1002；
步驟128：   沉積一氮化物-3層1006並蝕刻氧化物-3層1002中的氧化物-3V層10022的部分；
步驟130：   生長矽區域。
上述製造方法的詳細說明如下：從良好設計的p型基底200開始，以簡單的平面n型金氧半電晶體(n-type metal-oxide-semiconductor, NMOS)為例來說明本發明的主要技術特徵，然而類似的製程和結構也可應用於平面p型金氧半電晶體(p-type metal-oxide-semiconductor, PMOS)，其中該平面p型金氧半電晶體是製作在p型基底200的n井203(如圖3(b)所示)。
在步驟102中，如圖3(a)所示，在原始水平表面OHS上長出具有良好設計厚度的襯墊氧化層204，以及在襯墊氧化層204的頂面沉積出具有良好設計厚度的襯墊氮化層206。
在步驟104中，如圖3(a)所示，利用一光刻光罩技術(photolithographic masking technique)通過一各向異性蝕刻技術(anisotropic etching technique)以定義出該N型金氧半電晶體的主動區，其中該各向異性刻蝕技術移除對應於該主動區外的原始水平表面OHS的部分矽材料爲未來的淺溝槽隔離(shallow trench isolation, STI)需求創建該溝槽。
在步驟106中，如圖3(a)所示，沉積厚的該氧化層以完全填充該溝槽並使用該化學機械研磨技術移除多餘的該氧化層以形成淺溝槽隔離402，其中淺溝槽隔離402的頂面與襯墊氮化層206的頂面平齊，以及淺溝槽隔離402環繞該主動區以防止當該N型金氧半電晶體為一鰭式結構電晶體時，在形成該N型金氧半電晶體的源極/汲極或閘極期間崩塌。另外，值得注意是淺溝槽隔離402的頂面高於原始水平表面OHS。另外，圖3(b)是對應圖3(a)的俯視圖，其中圖3(a)是沿著圖3(b)所示的X方向的切割綫的橫截面圖。
在步驟108中，如圖4(a)所示，然後利用該光刻光罩技術(例如形成圖案化光阻403)來定義該閘極區的長度Lgate。
在步驟110中，如圖4(a)所示，移除對應該閘極區的襯墊氧化層204和襯墊氮化層206(也就是說將未被圖案化光阻403覆蓋的襯墊氧化層204和襯墊氮化層206移除)以形成凹陷404。另外，圖4(b)是對應圖4(a)的俯視圖，其中圖4(a)是沿著圖4(b)所示的X方向的切割綫的橫截面圖。
在步驟114中，如圖5(a)所示，在步驟112中移除圖案化光阻403後，在凹處404內形成閘極介電材料502(例如熱氧化層或高介電材料層(例如HfO2))以作為原始水平表面OHS上方的閘極絕緣層。另外，圖5(b)是與圖5(a)對應的俯視圖，其中圖5(a)是沿著圖5(b)所示的X方向的剖切線的剖面圖。
在步驟116中，如圖6(a)所示，在閘極介電材料502上方沉積閘極材料504(例如包含n+多晶矽5041、n+多晶矽5041上方的鈦/氮化鈦5042、以及鈦/氮化鈦5042上方的鎢5044)。然後通過該化學機械研磨技術拋光閘極材料504以使閘極材料504的頂面與襯墊氮化物層206的頂面平齊，並回蝕閘極材料504以使閘極材料504的頂面低於襯墊氮化物層206的頂部。
在步驟118中，如圖6(a)所示，然後將由一氮化層5062和一氧化層5064組成的複合覆蓋層506沉積到閘極材料504頂面的凹陷404中，其中複合覆蓋層506是用於保護閘極材料504。然後通過該化學機械研磨技術對複合覆蓋層506進行拋光以使複合覆蓋層506的頂面與襯墊氮化層206的頂面平齊。如此，該N型金氧半電晶體的閘極區完成。另外，圖6(b)是對應圖6(a)的俯視圖，其中圖6(a)是沿著圖6(b)所示的X方向的切割綫的橫截面圖。
在步驟120中，如圖7(a)所示，蝕刻掉淺溝槽隔離402和該閘極區(包含閘極材料504和複合覆蓋層506)之間的襯墊氧化層204和襯墊氮化層206以露出p型基板200的原始水平表面OHS。
在步驟122中，如圖7(a)所示，該閘極區的側壁上的間隔層可包含一薄的氧化物-1層801、一薄的氮化物-1層802和一薄的氧化物-2層804，其中氧化物-1層801是熱生成在原始水平表面OHS上，氮化物-1層802是沉積在該閘極區的側壁上，氧化物-2層804是沉積在氮化物-1層802上，以及氮化物-1層802和氧化物-2層804位於氧化物-1層801上方。如此，介於淺溝槽隔離402和上述間隔層之間的該N型金氧半電晶體的源極區和汲極區可被明確的定義。另外，圖7(b)是對應圖7(a)的俯視圖，其中圖7(a)是沿著圖7(b)所示的X方向的切割綫的橫截面圖。
在步驟124中，如圖8(a)所示，然後利用該各向異性刻蝕技術蝕刻掉p型基板200露出的矽區域以創造出用於分別形成該N型金氧半電晶體的源極區和汲極區的源極溝槽902和汲極溝槽904。另外，如圖8(a)所示，源極溝槽902和汲極溝槽904的每個溝槽都包含p型基板200的曝露的垂直側壁，其中p型基板200的曝露的垂直側壁假設具有陡峭的結晶方向(110)且位於上述間隔層的正下方。 在本實施例中，源極溝槽902(或汲極溝槽904)的具有陡峭的結晶方向(110)的邊緣可以與該閘極結構的邊緣對齊(如圖8(a)所示)。但在另一實施例中，源極溝槽902(或汲極溝槽904)的具有陡峭的結晶方向(110)的邊緣可與氮化物-1層802或氧化物-2層804的邊緣對齊。另外，圖8(b)是對應圖8(a)的俯視圖，其中圖8(a)是沿著圖8(b)所示的X方向的切割綫的橫截面圖。
在步驟126中，如圖9(a)所示，首先在源極溝槽902和汲極溝槽904中使用一熱氧化製程(thermal oxidation process，稱為氧化物-3製程)長出氧化物-3層1002(包含穿透p型基板200的曝露的垂直側壁的氧化物-3V層10022(假設具有陡峭的結晶方向(110))，以及位於源極溝槽902和汲極溝槽904的底部的頂表面上的氧化物-3B層10024)。因為源極溝槽902和汲極溝槽904的大部分側壁都靠著淺溝槽隔離402，所以該氧化物-3製程僅可在源極溝槽902和汲極溝槽904中具有陡峭的結晶方向(110)的側壁上長出少量的氧化層以至於該N型金氧半電晶體的源極區/汲極區的寬度實際上不受該熱氧化製程的影響。
另外，如圖9(a)所示，氧化物-3V層10022和氧化物-3B層10024在圖9(a)和後續圖中的厚度僅是用以說明本發明，且氧化物-3V層10022和氧化物-3B層10024的幾何形狀與那些圖中所示的淺溝槽隔離402的尺寸並不成比例。例如，在本發明的一實施例中，氧化物-3V層10022和氧化物-3B層10024的厚度可為2~5nm左右，而淺溝槽隔離402的垂直高度可為200~400 nm左右。但非常重要的是在設計該氧化物-3製程時，在精確控制的熱氧化溫度、時間和生長速度的情況下，可以非常精確地控制氧化物-3V層10022的厚度。由於在定義明確的矽表面上進行該熱氧化製程會造成氧化物-3V層10022的厚度的40%被移除，所以在p型基板200的垂直壁上曝露的矽表面(具有陡峭的結晶方向(110))的厚度和氧化物-3B層10024其餘60%的厚度會被視為p型基板200的垂直壁外的附加物(因為氧化物-3V層10022上這種40%和60%的分佈的重要性將在下文中進一步闡明，所以在圖9(a)中，氧化物-3V層10022上這種40%和60%的分佈將特別用虛線畫出)。另外，圖9(b)是對應圖9(a)的俯視圖，其中圖9(a)是沿著圖9(b)所示的X方向的切割綫的橫截面圖。
在步驟128中，如圖10(a)所示，在晶圓表面上沉積足夠厚的氮化物-3層1006(例如絕緣層)以完全填充源極溝槽902和汲極溝槽904，然後蝕回以移除氮化物-3層1006中不需要的部分以至於僅在源極溝槽902和汲極溝槽904內留下適當厚度的氮化物-3層1006。如圖10(a)所示，氧化物-3V層10022、氧化物-3B層10024和氮化物-3層1006的組合可稱為矽基底局部隔離(localized isolation into silicon substrate, LISS)。這裡值得一提的是只要氧化物-3層1002被保留如設計的一樣多，則氮化物-3層1006可被任何合適的絕緣材料(例如氧化物層)取代。然後，利用良好設計的各向同性刻蝕技術移除氧化物-3V層10022高於氮化物-3層1006的部分，從而曝露出p型基底200的本體，其中該本體具有曝露的矽表面且該曝露的矽表面具有陡峭的結晶方向(110)。這裡值得注意的是該本體具有比該閘極區的邊緣向內凹陷適當厚度的垂直邊界。另外，圖10(b)是對應圖10(a)的俯視圖，其中圖10(a)是沿著圖10(b)所示的X方向的切割綫的橫截面圖。
在步驟130中，如圖11(a)所示，然後使用選擇性生長技術(或其他合適的技術，例如可以是原子層沉積(Atomic Layer Deposition, ALD)或選擇性生長原子層沉積(selective growth Atomic Layer Deposition, SALD))從該曝露的本體上跨越該矽基底局部隔離長出矽區域(也就是該N型金氧半電晶體的源極區/汲極區)，其中該曝露的本體是作為晶種，該長出的矽區域為具有陡峭的結晶方向(110)的晶格矽區域，且該矽基底局部隔離對改變該矽區域的(110)晶體結構沒有晶種效應。如圖11(a)所示，在本發明的一實施例中，該矽區域包含該N型金氧半電晶體的n-輕摻雜汲極(n- lightly doped drain, NLDD)1102、1104，n+摻雜源極區1106，以及n+摻雜汲極區1108。同樣地，當該N型金氧半電晶體替換為P型金氧半(PMOS)電晶體時，該矽區域可包含p-輕摻雜汲極和p+摻雜源/汲極區。另外，在本發明的另一實施例中，該矽區域可包含未摻雜區域、n-輕摻雜汲極和n+摻雜源/汲極區。如此，該N型金氧半電晶體的源極區和汲極區全部完成。另外，圖11(b)是對應圖11(a)的俯視圖，其中圖11(a)是沿著圖11(b)所示的X方向的切割綫的橫截面圖。
另外，如圖12(a)所示，在本發明的另一實施例中，可以增加氧化物-3V層10022和氧化物-3B層10024的厚度，從而使得氧化物-3V層10022位於該閘極區下方，而不是對齊或是實質上對齊該閘極區的邊緣。如圖12(a)所示，氧化物-3V層10022的邊緣與該閘極區的邊緣之間的距離可以是該閘極區的長度Lgate的1/10～1/4，其中氧化物-3V層10022的邊緣與該閘極區的邊緣之間的距離越大，越接近絕緣層上覆矽(Silicon On Insulator, SOI)的結構。如此，考慮到源極溝槽902和汲極溝槽904中的氧化物-3V層10022，其中一個氧化物-3V層10022的邊緣與另一氧化物-3V層10022的邊緣之間的距離可以為該閘極區的長度Lgate的1/ 2~ 4/5。另外，圖12(b)是對應圖12(a)的俯視圖，其中圖12(a)是沿著圖12(b)所示的X方向的切割綫的橫截面圖。
在圖12(a)的基礎上，如圖13(a)所示，執行圖10所介紹的製程以露出具有陡峭的結晶方向(110)的裸露矽表面，然後使用該選擇性生長(如選擇性外延生長(selective epitaxy growth, SEG)技術以長出該矽區域。在本實施例中，該矽區域包含該N型金氧半電晶體的p型區(或稱為p型垂直屏蔽層)1302、1304，n-輕摻雜汲極1306、1308，n+摻雜源極區1310，以及n+摻雜汲極區1312，其中該N型金氧半電晶體的源極區包含n-輕摻雜汲極1306和n+摻雜源極區1310，以及該N型金氧半電晶體的汲極區包含n-輕摻雜汲極1308和n+摻雜汲極區1312。另外，p型區1302、1304中的每個p型區就像一個再生長的矽本體以補償在氧化物-3V層10022的形成過程中損失的矽基底。同樣地，對於P型金氧半電晶體，將生長一個n型垂直屏蔽層以起到與該N型金氧半電晶體中的p型垂直屏蔽層相同的作用。如圖14(a)所示，熱退火後，即使n-輕摻雜汲極1306、1308有橫向擴散，p型區1302、1304也能有效屏蔽或阻擋n-輕摻雜汲極1306、1308的橫向擴散，從而使得擴散後的n-輕摻雜汲極1306、1308的邊緣與該閘極區的邊緣對齊或實質上對齊。
另外，p型區1302、1304的摻雜濃度可與通道區1314(或p型基板200)的摻雜濃度相同或相似。另外，如圖14(a)所示，在形成該閘極區之前，可以通過離子植入(未示出)在原始水平表面OHS下方且靠近原始水平表面OHS之處形成通道區1314。
然而，除了通過離子植入形成通道區1314之外，在本發明的另一個實施例中，還可以通過選擇性生長形成通道區。請參照圖15(a)，例如，在凹陷404中形成閘極介電材料502之前，可將凹陷404中露出的原始水平表面OHS蝕刻掉以形成深度為幾奈米(例如1.5-2nm)的淺溝槽1502。另外，圖15(b)是對應圖15(a)的俯視圖，其中圖15(a)是沿著圖15(b)所示的X方向的切割綫的橫截面圖。
然後，如圖16(a)所示，在淺溝槽1502中選擇性生長一通道區1602，並在通道區1602上形成閘極介電材料502。另外，圖16(b)是對應圖16(a)的俯視圖，其中圖16(a)是沿著圖16(b)所示的X方向的切割綫的橫截面圖。之後，圖 6、圖7、圖8、圖9、圖10、圖11、圖12、圖13、圖14 所示的用於形成該閘極區、該源極區和該汲極區的製程可同樣被採用於形成另一個平面N 型金氧半電晶體(或另一個平面 P型金氧半電晶體)。
另外，請再次參照圖14，如圖14所示，在p型區1302、1304的幫助下，即使n-輕摻雜汲極1306、1308因熱退火製程而發生橫向擴散，n-輕摻雜汲極1306、1308擴散的邊緣仍可與該閘極區的邊緣對齊或實質上對齊。也就是說在擴散的p型區1302、1304與擴散的源/汲極之間的P-N接面(P-N junction)可以與該閘極區的邊緣對齊。另外，由於p型區1302、1304的摻雜濃度可以與通道區1314的摻雜濃度相同或相似，所以該N型金氧半電晶體的有效通道長度仍然接近該閘極區的長度Lgate。值得注意的是這種P-N接面向上延伸且P-N接面的邊緣位於該矽基底局部隔離上，例如位於氧化物-3V層10022上。另外，p型區1302、1304可以有效阻擋空乏區從汲極區到源極區的延伸，從而減少穿隧效應(punch through effect)的可能性。
圖17是說明本發明所提出的具有p型垂直屏蔽層的平面N型金氧半電晶體的示意圖，其中閘極區的長度Lgate為30nm，氧化物-3B層的厚度為90nm，氧化物-3V層的邊緣與該閘極區的邊緣之間的距離為5nm，p型垂直屏蔽層的摻雜濃度為3e16和具有橫向寬度5nm，通道區的表面的摻雜濃度為3e16，通道區的下半部的摻雜濃度為3e18，半導體基底的摻雜濃度為8e17，n-輕摻雜汲極的摻雜濃度為1e19，以及 n+摻雜區的摻雜濃度為4e20。如圖18所示，圖18為圖17中平面N型金氧半電晶體結構的Vgs-Ids曲線的電腦輔助設計(Technology Computer-Aided Design, TCAD)模擬結果的示意圖，其中該平面N型金氧半電晶體的臨界電壓Vth為225mV，開啟電流Ion為539uA/um，以及關閉電流Ioff為5nA/um。
另外，圖19是說明本發明所提出的另一種具有p型垂直屏蔽層的平面N型金氧半電晶體的示意圖，其中圖17與圖19的唯一差異在於如圖19所示，p型垂直屏蔽層的摻雜濃度3e18與通道區的下半部的摻雜濃度相同。如圖20所示，圖20是圖19中平面N型金氧半電晶體的Vgs-Ids曲線的電腦輔助設計模擬結果的示意圖，其中該平面N型金氧半電晶體的臨界電壓Vth為300(mV)，開啟電流Ion為468(uA/um)，以及關閉電流Ioff為490(pA/um)。與圖18中的電腦輔助設計模擬結果相比，p型垂直屏蔽層的摻雜濃度越高，臨界電壓Vth也越高以及關閉電流Ioff也越低。
總結，本發明具有下列優點：
(1)因為源極/汲極區全由具有晶格方向(110)的矽晶形成，所以可改善從兩個不同晶種區長出源極/汲極區的傳統方法，其中如所解釋的該兩個晶種區將導致晶格方向(100)的矽晶和晶格方向(110)的矽晶混合。
(2)新長出的矽結構中良好定義的晶格方向(110)的結晶與有效通道長度緊密無縫且完好無損，從而精確控制了該N 型金氧半電晶體的寬度。
(3)新生長的矽區域可以用原位摻雜(in-situ doped)的摻雜劑生長，其中該摻雜劑可以是該N型金氧半電晶體的磷/砷原子，或是該P型金氧半電晶體的硼原子。通過這種原位摻雜矽生長技術，源極/汲極區可以很好地設計為包含具有可控橫向距離的輕摻雜汲極和與其接觸的重摻雜區。
(4)因為無需使用離子植入來形成輕摻雜汲極，所以無需使用熱退火製程來減少缺陷。因此，即使採用熱退火製程，也不會産生難以完全消除的額外缺陷，從而大大減少了任何非預期的漏電流來源。
(5)相較於形成此類傳導通道的傳統方法必須處理晶格方向(100)的矽晶和晶格方向(110)的矽晶混合的問題，本發明僅須處理沿著通道區到源極/汲極區的晶格方向(110)的矽晶結構。因此，預計從具有精確可控選擇性外延生長(SEG)技術生成的電晶體本體和通道區生長的新矽區域可創建更好的高品質/高性能的源極/汲極區至通道區傳導機制；次臨界漏電流(sub-threshold leakage)可被減少；因為從通道通過輕摻雜汲極到重摻雜區的傳導機制可以具有整體設計(甚至包含通過將外來原子/離子均勻插入源極/汲極區中的一些應力通道遷移率增強技術可以具有增強導通性能的協同效應(synergistic effect))，所以通道傳導性能可被增強。
(6)本發明的另一大優勢是因為在熱氧化可控性的基礎上，閘極區的邊緣和新生長矽區域的邊緣之間的垂直邊界可以被很好的定義，所以相較於傳統上使用輕摻雜汲極植入作爲閘極區的邊緣與輕摻雜汲極的邊緣對齊的方式，本發明可減少閘極引起的汲極洩漏(gate-induced drain leakage, GIDL)效應。
(7)因為源極/汲極區的大部分都由絕緣材料隔離，其中該絕緣材料包含矽基底局部隔離(LISS)的底部結構，所以接面漏電流(junction leakage)只會發生在新生長的矽區到通道區的極小區域而可被顯著地降低。
(8)p型垂直屏蔽層不僅可補償在氧化物-3V層的形成過程中損失的矽基底以保持通道區合適的長度，且可有效阻擋空乏區(depletion region)的延伸，從而減少穿隧效應(punch through effect)的可能性。
當如前文所述和所示形成這樣的新生長的矽區域時，可繼續剩餘的電晶體形成步驟以根據需求填充具有精心設計的摻雜濃度分佈的整個源極/汲極區。 另外，完成源極/汲極區的另一種方式是可以形成鎢(或其他合適的金屬材料)插銷的部分與源極/汲極區的部分水平連接以完成整個源極/汲極區。也就是說鎢(或其他適當的金屬材料)插銷的部分位於溝槽902、904中以接觸n+摻雜源極區1310和n+摻雜汲極區1312的側壁，以及鎢(或其他適當的金屬材料)插銷的其餘部分位於溝槽902和904之上以接觸n+摻雜源極區1310和n+摻雜漏極區1312的頂面。另外，流向之後形成的金屬互連(例如金屬-1層(metal-1 layer))的通道電流會經過輕摻雜汲極、重摻雜源極/汲極區到鎢(或其他適當的金屬材料)插銷，其中鎢(或其他適當的金屬材料)插銷可通過一些良好的金屬到金屬歐姆接觸(metal-to-metal ohmic contact)直接連接到金屬-1層，而金屬到金屬歐姆接觸的電阻遠低於傳統的矽到金屬接觸(silicon-to-metal contact)的電阻。
綜上所述，本發明所提供的該金氧半場效電晶體具有下列優點：
A. 在電晶體通道傳導方面：
(a)由於源極/汲極區是直接從通道區和本體區的晶面長出，所以源極/汲極區和通道區/本體區之間的接面可無縫地形成且具有相同的晶格方向(110)，從而精確控制通道區的寬度；(b)由於在選擇性外延生長(SEG)過程中採用原位摻雜技術以使輕摻雜汲極從通道區和本體區水平向外生長，所以本發明沒有離子植入製程，其中植入製程只能從矽基底的頂部向下形成源極/汲極區以及熱退火製程會使接面的邊界難以定義和控制；(c)相反地，本發明可以更精確地定義源極/汲極區的邊界的邊緣到閘極區的邊緣以最小化短通道效應(short channel effect, SCE)、閘極引起的汲極洩漏(gate-induced drain leakage, GIDL)效應和接面漏電流。
B. 在形成源極 / 汲極區方面：
(a)除了面向電晶體通道區的矽開口外，源極/汲極區的周圍有絕緣層(例如，氧化物-3V層，氧化物-3B層，和矽基底局部隔離)包圍，且源極/汲極區的深度由矽基底局部隔離控制。(b)具有輕摻雜汲極到重摻雜區的矽電極的水平選擇性外延生長甚至包含各種非矽摻雜劑(例如鍺或碳原子)以增加應力從而增強通道遷移率。(c)另外，本發明提出了金屬插銷來填充半導體區域的空缺以完成矽基底局部隔離上方的整個源極/汲極區。(d)另外，在水平選擇性外延生長/原子層沉積形成源極/汲極區時摻雜濃度分佈是可控或可調的，特別是在平面N型金氧半電晶體的n-輕摻雜汲極形成之前先生長p型垂直屏蔽層(或是平面P型金氧半電晶體的p-輕摻雜汲極形成之前先生長n型垂直屏蔽層)，其中p型垂直屏蔽層不僅可補償在氧化物-3V層的形成過程中損失的矽基底以保持通道區合適的長度，且可有效阻擋空乏區的延伸，從而減少穿隧效應的可能性。
當然，本發明不僅可應用在平面金氧半場效電晶體，也可應用在非平面金氧半場效電晶體(例如鰭式場效電晶體(FinFET)、三閘極(Tri-gate)電晶體、全繞式(gate-all-around, GAA)電晶體等)。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
100:互補金氧半電晶體 102:p型金氧半電晶體 104:n型金氧半(PMOS)電晶體 106:p井 108、203:n井 1022、1024、1042、1044:源極/汲極區 200:p型基底 204:襯墊氧化層 206:襯墊氮化層 402、STI:淺溝槽隔離 403:圖案化光阻 404:凹陷 502:閘極介電材料 504:閘極材料 5041:n+多晶矽 5042:鈦/氮化鈦 5043:鎢 506:複合覆蓋層 5062:氮化層 5064:氧化層 801:氧化物-1層 802:氮化物-1層 804:氧化物-2層 902:源極溝槽 904:汲極溝槽 (110):晶格方向 1002:氧化物-3層 10022:氧化物-3V層 10024:氧化物-3B層 1006:氮化物-3層 1102、1104、LDD、1306、1308:輕摻雜汲極 1106、1310:n+摻雜源極區 1108、1312:n+摻雜汲極區 1302、1304:p型區 1314、1602:通道區 1502:淺溝槽 Lgate:長度 N-SSRW:N型超陡後退井 OHS:原始水平表面 P-SSRW:P型超陡後退井 10-50、102-130:步驟
圖1是說明現有技術中的互補金氧半電晶體的示意圖。 圖2A是本發明的一實施例所公開的一種具有低漏電流且預留閘極長度(reserved gate length)的金氧半場效電晶體結構的製造方法的流程圖。 圖2B、圖2C、圖2D是說明圖2A的流程圖。 圖3是說明長出襯墊氧化層、沉積襯墊氮化層以及形成溝槽的示意圖。 圖4是說明形成圖案化光阻以及蝕刻掉對應該閘極區的襯墊氧化層和襯墊氮化層以形成凹陷的示意圖。 圖5是說明移除圖案化光阻以及在凹陷內形成閘極介電材料的示意圖。 圖6是說明在凹陷內沉積閘極材料以及沉積複合覆蓋層的示意圖。 圖7是說明移除襯墊氧化層和襯墊氮化層以及在該閘極區的側壁上形成間隔層的示意圖。 圖8是說明蝕刻露出的矽以以創造出用於形成源極區和汲極區的溝槽的示意圖。 圖9是說明熱生長氧化物-3層的示意圖。 圖10是說明沉積氮化物-3層並蝕刻氧化物-3層中的氧化物-3V層的部分的示意圖。 圖11是說明生長矽區域的示意圖。 圖12是說明增加熱生長氧化物-3層厚度的示意圖。 圖13是說明在形成n-輕摻雜汲極前先形成p型垂直屏蔽層的示意圖。 圖14是說明在熱退火的過程中，n-輕摻雜汲極的邊緣仍可與該閘極區的邊緣對齊的示意圖。 圖15是說明在本發明的另一實施例中通過離子植入形成通道區的示意圖。 圖16是說明在淺溝槽中選擇性生長通道區並在通道區上形成閘極介電材料的示意圖。 圖17是說明本發明所提出的具有p型垂直屏蔽層的平面N型金氧半電晶體的示意圖。 圖18是說明圖17的科技電腦輔助設計(Technology Computer-Aided Design, TCAD)的模擬結果的示意圖。 圖19是說明本發明所提出的另一平面N型金氧半電晶體的示意圖。 圖20是說明圖19的科技電腦輔助設計的模擬結果的示意圖。
200:p型基底
203:n井
402:淺溝槽隔離
502:閘極介電材料
504:閘極材料
5041:n+多晶矽
5042:鈦/氮化鈦
5043:鎢
506:複合覆蓋層
5062:氮化層
5064:氧化層
802:氮化物-1層
804:氧化物-2層
1002:氧化物-3層
10022:氧化物-3V層
10024:氧化物-3B層
1006:氮化物-3層
1102、1104:輕摻雜汲極
1106:n+摻雜源極區
1108:n+摻雜汲極區
Lgate:長度
OHS:原始水平表面

Claims (20)

  1. 一種金氧半場效電晶體(metal-oxide-semiconductor field-effect transistor, MOSFET)結構，包含： 一半導體基底，具有一半導體表面； 一閘極結構，位於該半導體表面上方； 一通道區，位於該閘極結構下方； 一溝槽，形成於該半導體表面下方且鄰近該通道區； 一隔離區，位於該溝槽中； 一第一導電區，具有一第一摻雜類型，其中該第一導電區位於該隔離層上方並電耦接至該通道區；及 一P-N接面(P-N junction)，從該隔離區沿著該第一導電區的邊緣向上延伸。
  2. 如請求項1所述的金氧半場效電晶體結構，另包含一垂直屏蔽層(vertical screening layer)，其中該垂直屏蔽層與該第一導電區接觸，且該垂直屏蔽層的摻雜類型與該第一導電區的第一摻雜類型不同。
  3. 如請求項2所述的金氧半場效電晶體結構，其中該第一導電區和該垂直屏蔽層均獨立於該半導體基底，且該P-N接面位於該第一導電區和該垂直屏蔽層之間。
  4. 如請求項3所述的金氧半場效電晶體結構，其中該金氧半場效電晶體結構為一平面n型金氧半(n-type metal-oxide-semiconductor, NMOS)電晶體，該垂直屏蔽層為一p型垂直屏蔽層，該第一導電區域包含一n型輕摻雜汲極(lightly doped drain, LDD)區和一n型重摻雜區，該n型輕摻雜汲極區與該p型垂直屏蔽層接觸，以及該n型重摻雜區與該n型輕摻雜汲極區接觸。
  5. 如請求項4所述的金氧半場效電晶體結構，其中該p型垂直屏蔽層的摻雜濃度與該通道區的摻雜濃度相同或實質上相同。
  6. 如請求項4所述的金氧半場效電晶體結構，其中該n型輕摻雜汲極區的邊緣與該閘極結構的邊緣對齊或實質上對齊。
  7. 如請求項4所述的金氧半場效電晶體結構，其中該第一導電區域包含一含金屬區，且該含金屬區位於該溝槽內並緊鄰該n型重摻雜區域。
  8. 如請求項1所述的金氧半場效電晶體結構，其中該隔離區包含： 一垂直氧化層和一水平氧化層，其中該垂直氧化層覆蓋該溝槽的一側壁，以及該水平氧化層覆蓋該溝槽的底部；及 一絕緣插銷，位於該溝槽內和該水平氧化層上方。
  9. 如請求項8所述的金氧半場效電晶體結構，其中該垂直氧化層的邊緣位於該閘極結構的下方，且該垂直氧化層的邊緣與該閘極結構的邊緣之間的距離為該閘極結構的長度的1/10～1/4。
  10. 如請求項8所述的金氧半場效電晶體結構，另包含一淺溝槽隔離區(shallow trench isolation region)，其中該淺溝槽隔離區圍繞該第一導電區的側壁，且該第一導電區的底部通過該隔離區與該半導體基底隔離。
  11. 一種金氧半場效電晶體結構，包含： 一半導體基底，具有一半導體表面； 一第一溝槽和一第二溝槽，形成在該半導體表面下方； 一第一隔離區和一第二隔離區，其中該第一隔離區位於該第一溝槽中以及該第二隔離區位於該第二溝槽中； 一閘極結構，位於該半導體表面上方，其中該閘極結構包含一閘極隔離層和一閘極導電層，該閘極隔離層位於該半導體表面上方，以及該閘極導電層位於該閘極隔離層上方； 一通道區，位於該閘極結構下方； 一汲極區，具有一第一摻雜類型且在該第一隔離區上方；及 一源極區，具有該第一摻雜類型且在該第二隔離區上方； 其中該第一隔離區的邊緣與該第二隔離區的邊緣之間的距離小於該閘極結構的長度。
  12. 如請求項11所述的金氧半場效電晶體結構，其中該第一隔離區的邊緣與該第二隔離區的邊緣之間的距離為該閘極結構的長度的1/2～4/5。
  13. 如請求項11所述的金氧半場效電晶體結構，另包含一垂直屏蔽層，其中該垂直屏蔽層與該汲極區接觸，且該第一垂直屏蔽層的摻雜類型不同於該汲極區的第一摻雜類型。
  14. 如請求項13所述的金氧半場效電晶體結構，其中該第一垂直屏蔽層的摻雜濃度與該通道區的摻雜濃度相同或實質上相同。
  15. 如請求項13所述的金氧半場效電晶體結構，其中該第一垂直屏蔽層和該汲極區之間具有P-N接面，以及該P-N接面從該第一隔離區向上延伸且與該閘極結構的邊緣對齊或實質上對齊。
  16. 如請求項13所述的金氧半場效電晶體結構，其中該通道區、該第一垂直屏蔽層和該汲極區獨立於該半導體基底。
  17. 一種被淺溝槽隔離區包圍的金氧半場效電晶體結構，包含： 一半導體基底，具有一半導體表面； 一第一溝槽和一第二溝槽，形成在該半導體表面下方； 一第一隔離區和一第二隔離區，其中該第一隔離區位於該第一溝槽中以及該第二隔離區位於該第二溝槽中； 一閘極結構，位於該半導體表面上方； 一通道區，位於該閘極結構下方； 一汲極區，具有一第一摻雜類型且在該第一隔離區上方； 一源極區，具有該第一摻雜類型且在該第二隔離區上方；及 一第一垂直屏蔽層，介於該汲極區和該通道區之間，其中該第一垂直屏蔽層的摻雜類型不同於該汲極區的第一摻雜類型，且該第一垂直屏蔽層和該汲極區獨立於該半導體基底。
  18. 如請求項17所述的金氧半場效電晶體結構，其中該第一垂直屏蔽層的水平厚度為2～5奈米(nm)。
  19. 如請求項17所述的金氧半場效電晶體結構，其中該汲極區的三個側壁通過該淺溝槽隔離區與該半導體基底隔離，且該第一導電區的底部通過該第一隔離區與該半導體基底隔離。
  20. 如請求項17所述的金氧半場效電晶體結構，其中該金氧半場效電晶體結構是由製程節點λ形成，且當該λ介於12nm～30nm之間時，該閘極結構的長度在1.2λ～2.4λ之間。
TW112121378A 2022-06-09 2023-06-08 具有低漏電流且預留閘極長度的金氧半場效電晶體結構 TW202416508A (zh)

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