CN105633165B - Semiconductor device including heterojunction, electronic device and contact structure thereof - Google Patents

Semiconductor device including heterojunction, electronic device and contact structure thereof Download PDF

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CN105633165B
CN105633165B CN201510845580.9A CN201510845580A CN105633165B CN 105633165 B CN105633165 B CN 105633165B CN 201510845580 A CN201510845580 A CN 201510845580A CN 105633165 B CN105633165 B CN 105633165B
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semiconductor material
alloy
semiconductor
metal contact
channel region
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CN105633165A (en
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乔治·A·凯特尔
伯纳·乔司·奥勃特道威
罗伯特·克里斯图福·博文
马克·S·罗迪尔
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon

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Abstract

Semiconductor devices, electronic devices, and contact structures thereof are provided that include heterojunctions. The semiconductor device may include a metal contact and a channel region having a first semiconductor material for majority carriers in the channel region during operation (on-state) of the semiconductor device. The source/drain regions may include a semiconductor material alloy including a second semiconductor material and at least one heterojunction between the metal contact and the channel region, wherein the heterojunction forms a band edge offset for majority carriers that is less than or equal to about 0.2 eV.

Description

Semiconductor device including heterojunction, electronic device and contact structure thereof
This application claims priority to U.S. provisional patent application No. 62/085,092, filed on 26.11.2014 and U.S. patent application No. 14/942,193, filed on 16.11.2015, the entire disclosure of which is incorporated herein by reference.
Technical Field
The present invention relates generally to the field of integrated circuit devices, and more particularly, to integrated circuit devices utilizing materials configured to operate as semiconductors.
Background
As MOS devices continue to decrease in size, parasitic resistance can become a greater problem, i.e., a higher percentage of the total resistance may be caused at each new node than at previous nodes, and can be a factor in the performance of such devices. In addition, the particular material selected for the channel (e.g., the channel of a MOS device) may not always be suitable or compatible with low resistance contacts.
Parasitic resistances are further discussed in U.S. patent publication nos. 2006/0202266 and 2009/0166742, the disclosures of which are incorporated herein by reference in their entirety.
Disclosure of Invention
Embodiments according to the present invention may provide a device contact structure including a heterojunction for low contact resistance. In accordance with these embodiments, a semiconductor device may include a channel region having a first semiconductor material for majority carriers in the channel region during operation (on-state) of the semiconductor device and a metal contact. The source/drain regions may include a semiconductor material alloy including a second semiconductor material and at least one heterojunction between the metal contact and the channel region, wherein the heterojunction forms a band edge offset for majority carriers that is less than or equal to about 0.2 eV.
In some embodiments according to the inventive concept, the semiconductor material alloy may comprise a third semiconductor material and a graded composition of the second semiconductor material, wherein the third semiconductor material is not fully mixed with the first semiconductor material, i.e. the third semiconductor material cannot be obtained by continuously grading the alloy starting from the first semiconductor material.
In some embodiments according to the invention, the band edge offset of the heterojunction can be about 0.0 eV.
In some embodiments according to the invention, the band edge offset of the heterojunction may be less than 0.2eV, and the heterojunction region may be doped with a dopant having a conductivity type corresponding to that of the majority carriers.
In some embodiments according to the invention, the graded composition of the alloy of semiconductor materials may include a concentration rich in the second semiconductor material and a concentration lean in the third semiconductor material at an interface of the first semiconductor material of the channel region and progress to a concentration lean in the second semiconductor material and a concentration rich in the third semiconductor material at an interface of the metal contact.
In some embodiments according to the invention, the graded composition of the semiconductor material alloy may be represented by S2xS31-xWherein S3 is the third semiconductor material and S2 is the second semiconductor material. In some embodiments, x is 0 at the interface of the metal contact and x is 1 at the interface of the first semiconductor material.
In some embodiments according to the invention, the increment in the graded composition of the semiconductor material alloy may be configured to prevent an energy band offset between adjacent levels in the graded composition to be greater than about 0.2 eV.
In some embodiments according to the invention, an electronic device can include a metal contact and a channel region having a first material, the channel region for majority carriers in the channel region during operation of the semiconductor device. The source/drain regions may include a material alloy that includes at least one material composition and may be free of all of the composition of the first material such that compositional grading of the material alloy between the interface of the channel region and the metal contact avoids abrupt changes between increments in the compositional grading and at the band edge offset.
In some embodiments according to the invention, the first material has a first lattice structure and the alloy of materials may have a second lattice structure different from the first lattice structure to form a heterojunction having a band edge offset for the majority carriers that is less than or equal to about 0.2 eV.
In some embodiments, a semiconductor device may include a metal contact and a channel region having a first semiconductor material for majority carriers in the channel region during operation (on-state) of the semiconductor device. The source/drain region may include: a first portion located proximate to a channel comprising an alloy of semiconductor material including a second semiconductor material and a graded composition of a third semiconductor material and the second semiconductor material. The source/drain region may include: another portion proximate to the metal contact, the metal contact comprising a fourth semiconductor material, wherein an interface between the two portions of the source/drain region is a heterojunction having a band edge offset for the majority carriers, the band edge offset being less than or equal to about 0.2eV, the heterojunction being doped with a dopant type corresponding to the conductivity of the majority carriers. In some of these embodiments, a material may be selected that does not form a heterojunction between portions of the source/drain regions that are adjacent to the channel and the channel material. For example, in some embodiments, the semiconductor material alloy is selected such that the semiconductor material alloy can be graded to be substantially the first semiconductor material at the interface with the channel. In other embodiments, a second heterojunction having an energy band edge offset for majority carriers equal to or less than 0.2eV and doped with a dopant type corresponding to the conductivity of the majority carriers may be present at the interface of the semiconductor alloy and the first semiconductor material.
In some embodiments according to the invention, an electronic device contact structure may comprise: a metal contact and a graded composition layer including a first material (S1) and a second material (S2), the first material (S1) and the second material (S2) being separated by S according to de within the graded composition layer1xS21-xProviding a graded composition in combination with each other, wherein the composition of the graded composition layer is entirely the second material S2 at x-0 near the metal contact and entirely S1 at x-1 away from the metal contact, wherein the composition of the graded composition layer between x-0 and x-1 is sufficient to avoid a band edge offset of selected carriers for the electronic device within the graded composition layer of greater than 0.2 eV. A third material S3, which may be in contact with the graded composition layer at x ═ 1, the third material S3 being selected to form a heterojunction with the first material S1 of equal to or less than about 0.2eV, wherein the second material S2 is selected to provide a schottky barrier height to the metal contact of equal to or less than about 0.2 eV.
In some embodiments according to the invention, an electronic device contact structure may comprise: a metal contact and a graded composition layer including a first material (S1) and a second material (S2), the first material (S1) and the second material (S2) being separated by S according to de within the graded composition layer1xS21-xProviding a graded composition in combination with each other, wherein the composition of the graded composition layer is entirely the second material S2 at x-0 near the metal contact and entirely S1 at x-1 away from the metal contact, wherein the composition of the graded composition layer between x-0 and x-1 is sufficient to avoid a band edge offset of selected carriers for the electronic device within the graded composition layer of greater than 0.2 eV. The third material S3 may be disposed to separate the metal contact from the graded composition layer and adjacent to a location where the graded composition layer x is 0, the third material S3 being selected such that the second material S2 forms a heterojunction equal to or less than about 0.2eV and provides a schottky barrier height equal to or less than about 0.2eV to the metal contact.
Drawings
Figure 1 is a cross-sectional view of a channel region of a semiconductor material alloy having a smoothly graded composition between the channel region and a metal contact at an upper surface of the source/drain region included proximate to the source/drain region in some embodiments according to the invention.
Fig. 2 and 3 are cross-sectional views of alternative channel region and associated source/drain region geometries that include a smooth gradual transition between the channel region and a metal contact at the upper surface of the source/drain region corresponding to the semiconductor material alloy in some embodiments according to the present invention.
Figure 4 is a schematic illustration of a linear composition graded configuration of a semiconductor material alloy between a channel region material and a metal contact in some embodiments according to the invention.
Figure 5 is a schematic illustration of a graded configuration of a nonlinear component of a semiconductor material alloy between a channel region material and a metal in some embodiments according to the invention.
Figure 6 is a schematic illustration of a graded configuration of a step composition of a semiconductor material alloy between a channel region material and a metal contact in some embodiments according to the invention.
Figure 7 is a schematic illustration of a compositionally graded configuration of a semiconductor material alloy between a channel region material and an interface material adjacent to a metal in some embodiments according to the invention.
Figure 8 is a schematic illustration of a compositionally graded configuration of a first semiconductor material alloy and a second semiconductor material alloy between a channel region material and a metal contact in some embodiments according to the invention.
Detailed Description
Example embodiments are described below with reference to the drawings. Many different forms and embodiments are possible without departing from the spirit and teachings of the present disclosure, and should not be construed as limited to the example embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the disclosure to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
Embodiments of the present invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments and intermediate structures of example embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Accordingly, example embodiments of the inventive concepts should not be construed as limited to the particular shapes illustrated herein but are to include deviations in shapes that result, for example, from manufacturing.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present application and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be understood that when an element is referred to as being "connected," "coupled," or "responsive" to or on another element, it can be directly connected, coupled, or responsive to the other element or on the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected," "directly coupled," or "directly responsive" to another element or "directly on" another element, there are no intervening elements present. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element could be termed a second element without departing from the teachings of the present embodiments.
Spatially relative positional terms, such as "below," "lower," "above," "upper," and the like, may be used herein to describe one element or feature's relationship to another element (or other element) or component (or other component) as illustrated in the figures to facilitate description. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
It will be appreciated that although many of the embodiments described herein relate to semiconductor materials in transistors, the invention may utilize other types of materials, such as semi-metallic materials, degenerate semiconductor materials, and combinations thereof, which may be configured to operate as semiconductor materials in electronic devices.
Further, it will be understood that although many of the embodiments described herein describe fin field effect transistor (finFET) structures as channel regions, the invention may utilize other types of transistor structures, such as planar transistors, nanowire transistors, MOSFETs, etc.
As used herein, it will be understood that for materials referenced according to the conductivity type of charge carriers used during operation (on-state) of the device (i.e., pMOS device vs. nmos device), the term "band edge" in relation to a particular material refers to either the conduction band edge or the valence band edge. Thus, the term "band edge" may be used with reference to "associated carriers" without specifying the type of device. For a pMOS device, the relevant carriers are holes and the band edge refers to the valence band edge. For nMOS devices, the relevant carriers are electrons and the band edge refers to the band edge.
As used herein, it will be understood that the term "low contact resistivity" or similar terms refer to a value of about 1E-8 Ω -cm2Or less interfacial contact resistivity. In some embodiments, "low contact resistivity" may refer to a value of about 1E-7 Ω -cm2Or less interfacial contact resistivity. As used herein, it will be understood that the term "low schottky barrier height" (SBH) or "low barrier" for a metal in contact with a semiconductor material includes values of about 0.2eV or less. As used herein, it will be understood that when the term "small" (or similar terms) is used to refer to the band offset between the band edges of the associated carriers at a heterojunction between different materials, it includes a value of about 02.eV or less. As used herein, it will be understood that when the term "small" (or similar terms) is used to refer to an energy band offset formed by an increment or step in the compositional grading of a material, it includes values of about 0.2eV or less, and preferably about 0.1eV or less.
As used hereinIt will be understood that the expression format (e.g., S2)xS31-x) Meaning that the two materials (S2, S3) are alloyed with the relevant components such that there are 1-x units of S3 per x units of S2, wherein the index x may vary between 0 and 1. Alloy S2xS31-xMay be included in a region, such as a source/drain region, and the composition of the alloy (indicated by parameter x) may vary as a function of position in the region. The term 'lean' or 'rich' may be used to refer to the proportion of a particular material. For example, S2 of rich S2xS31-xAlloy is S2 with x close to 1xS31-xAnd (3) alloying. For example, S2 lean of S2xS31-xAlloy is S2 with x close to 0xS31-xAnd (3) alloying.
As used herein, the term semiconductor material may refer to a semiconductor material that includes only one single element or to a compound of a semiconductor material that includes more than one element. As used herein, the term semiconductor alloy material refers to a semiconductor material that includes at least two different elements.
As understood by the inventors, in some embodiments according to the invention, a low resistivity contact may be provided to the semiconductor material (S1) in the channel region by forming a semiconductor alloy (S2 and S3) between the channel region and the metal contact of the device, the composition of which is smoothly graded. For example, the compositional grading in the semiconductor alloy may be: the contributions of S2 and S3 in the alloy gradually change as a function of position within the source/drain regions. For example, the compositional grading of the alloy may be arranged to: the semiconductor alloy is substantially S2 near the channel region, whereas the semiconductor alloy is substantially S3 away from the metal contact of the channel region.
In addition, the semiconductor material included in the alloys (S2 and S3) may be selected to have a specific relationship with the semiconductor material (S1) in the channel. For example, semiconductor material S2 may be selected to have a band edge that is closer to the band edge of semiconductor material S1 (i.e., a low band edge offset) than the band edge of semiconductor material S3. However, semiconductor material S3 may be selected to have a greater band edge offset relative to the channel semiconductor material S1. Furthermore, the compositional grading of the semiconductor alloy (S2 and S3) in the source/drain regions should be smooth in order to avoid any abrupt changes in the band edges of the relevant carriers in the source/drain regions.
Thus, as understood by the inventors, the semiconductor material S3 and the semiconductor material S1 in the channel region are selected such that: one of which (e.g., S3) cannot be obtained from the other (e.g., S3) by using sequential compositional grading. In other words, the semiconductor material S2 may be used as an intermediate material that is closer to the band edge of S1 but may also be present in alloy with S3.
Thus, semiconductor material S1 may be selected that is significantly different from semiconductor material S2 but still has a relatively low band edge offset, and further, the compositional grading of the semiconductor alloy may be utilized to gradually increase the contribution of S3 and decrease the contribution of S2 as the grading progresses toward the metal contact away from the channel region. It will also be appreciated that the semiconductor material S3 present at the metal contacts may be selected to provide a relatively low schottky barrier height for the relevant carriers.
As understood by the present inventors, FIG. 3 of the reference "Novel contact structures for high mobility materials" (MRS Bulletin 36(2011), pages 112-120, published by Philip Wong and Krishhnas arastep, Doi:10.1557/mrs.2011.5 available online and incorporated by reference herein) and FIG. 4 of the reference "Current transport, Fermi L evolution marking, and Transmission Behavior of Group-III Nitride Schottky Barriers" (Journal of the Korea Physical Society volume 55, No. 3, No. 2009-1179, published by Hideki Hasgawa and Maswaami and incorporated herein by reference) show that the semiconductor materials that can be used in the present invention exhibit different levels of electrical contact and/or electrical Pinning at a moderate level of the semiconductor material, exhibit a strong level of metal Pinning at the interface, and exhibit a moderate level of electrical contact Pinning at the aforementioned metal-based interface/metal materials (Akfermi) when the metal material is not in the aforementioned electrical contact structure.
Still referring to fig. 3 of Hu and fig. 4 of Hasgawa, the electroneutral levels are shown for several semiconductor materials. In some embodiments, such semiconductor materials are selected to form metal contacts: the semiconductor material has fermi level pinning or strong fermi level pinning near the edges of the associated carrier band such that a low schottky barrier height is provided to the associated carrier when in contact with the metal.
It will also be appreciated that pinning of the InGaSb alloy may be near the valence band edge. It will also be appreciated that for InGaAs, InGaN, and AlGaN alloys, the absolute position of the electroneutral level may vary slightly from composition to composition. In some embodiments, InAs, indium rich In-Ga-As alloys, InN, and indium rich In-Ga-N alloys may be suitable for semiconductor materials used between alloy interfaces to metal contacts In nMOS devices. Because of its small bandgap, InSb can be suitable for nMOS devices and pMOS devices. For pMOS devices, Ge, InSb, and In-Ga-Sb alloys may be suitable for use as semiconductor materials used between the alloy interface to the metal contacts.
As understood by the present inventors, FIG. 1, "Empirical specific band semiconductors and barrier heights in III-V alloy systems," published by Sandip Tiwari and David J.Frank (appl. Phys. L et t.60(1992), page 630, dX. doi. org/10.1063/1.06575 available online and incorporated by reference herein) is a graph showing the lattice constants and band edge locations of different semiconductor materials in some embodiments according to the invention, and thus, the appropriate material combinations for use in the channel and source drain regions of a device can be selected using FIG. 1 of Tiwari. As further understood by the present inventors, "nanometer-scale electronics with III-Vcompound semiconductors diodes" (Nature 479, Nature 323(17 Nover 323), available online, Jdoi: 10.1038/JJ.f, incorporated by reference, and shown by several graphs showing that the appropriate material combinations for use in the devices, such as a graph 1.
The compositional grading of the semiconductor material alloy in the source/drain regions may be arranged based on the semiconductor material selected to interface with the metal contact and the semiconductor material used in the channel region. For example, In some embodiments according to the invention, a high germanium SiGe alloy or Ge for nMOS or pMOS, silicon for nMOS or pMOS, SiGe for pMOS, an In-Ga-As alloy for nMOS, an In-As alloy for nMOS, or an In-Ga-Sb alloy for nMOS or pMOS, or the like, may be used As the semiconductor material In the channel region. It will be appreciated that each of the above parameters (i.e., the semiconductor material used as the interface-to-metal contact and the semiconductor material used in the channel region) may be selected to satisfy two conditions: (1) the semiconductor material used in the channel region cannot smoothly be compositionally graded to reach the semiconductor material used between the interface to the metal contact; (2) the band edge offset (for the relevant carriers) between the semiconductor material used in the channel region and the semiconductor material selected for use at the interface to the metal contact is significant (i.e., greater than about 0.2 eV).
In summary, a smooth compositional grading of the semiconductor alloy in the source/drain regions between the channel region and the metal contact can be utilized to provide a low resistivity contact. In either case, the semiconductor material included in the alloy is selected to effectively eliminate the potential barrier to carriers transported in the source/drain regions despite the presence of, for example, a heterojunction formed either near the metal contact or near the channel region. In either case, the band edge offset provided at the heterojunction should be less than 0.2eV for the relevant carriers.
It will be appreciated that the formation of a smoothly graded alloy material may be performed using epitaxial growth of selected materials, wherein a desired compositional expression (such as S2) is utilized during the epitaxial growth processxS31-x) In addition, THE formation OF a smoothly GRADED alloy material may be performed using THE METHODS described in U.S. Pat. No. 14/226,518 entitled FINFET DEVICES INC L UDING HIGH MOBI L ITY CHANNE L MATERIA L S WITH MATERIA L S OF GRADED COMPOSITIONS IN RECESSED SOURCE/DRAINREGION AND METHOD OF FORMING THE SAME filed 3/26.2014.A. US Patent trademark office (attorney docket No. 1145-9); U.S. provisional patent application No. 61/859,932The title FINFET WITH RECESSEDAND GRADED SOURCE AND DRAIN MATERIA L FOR L OW TOTA L PARASITIC RESISTANCE, filed on 2013, 7, 30.months, to the United states patent and trademark office (attorney docket number 1145-9PR), the entire disclosure of which is incorporated herein by reference.
Fig. 1 is a cross-sectional view of a semiconductor device having a region 100 that includes a channel and that includes semiconductor channel semiconductor material (S1) adjacent to an alloy of semiconductor material 106 in source/drain regions 107. In some embodiments according to the invention, the semiconductor material alloy 106 further comprises a metal contact interface portion 105 in contact with the metal contact 101. Although fig. 1 and the associated description point to the use of such semiconductor materials, other types of materials may also be used in accordance with the present invention. For example, any material configured to operate like a semiconductor, such as a semi-metal or degenerate semiconductor, may be used. Further, fig. 2 and 3 illustrate alternative geometries for region 100 and source/drain regions 107 in some embodiments according to the invention. Thus, the geometry of the device in FIG. 1 is exemplary, and the invention is not limited in this regard.
Still referring to fig. 1, the alloy of semiconductor material 106 is compositionally graded in the source/drain regions 107 (e.g., from the interface 102 of the region 100 containing the channel to the metal contact interface portion 105). In other words, the composition of the semiconductor material alloy 106 changes as a function of location in the source/drain regions 107. In some embodiments, the composition of the semiconductor material alloy 106 changes in the source/drain regions 107 as a function of position to provide both a heterojunction with semiconductor material S1 and a relatively low schottky barrier height between the metal contact interface portion 105 and the metal contact 101. Specifically, the semiconductor material alloy 106 may be epitaxially grown such that the semiconductor material S2 is disposed substantially at the interface 102 and gradually decreases toward the metal contact interface portion 105, whereas the semiconductor material S3 gradually increases as the semiconductor material S2 decreases, such that the semiconductor material alloy 106 is substantially the semiconductor material S3 when the grading of the semiconductor material alloy 106 reaches the metal contact interface portion 105.
It will be understood that in some embodiments, the semiconductor material S1 in the region 100 forms a heterojunction with the second semiconductor material S2 at the interface 102. Thus, the semiconductor material S1 may be substantially different from the semiconductor material S2, and the band edge offset from S2 to S1 may be relatively small (e.g., less than or equal to about 0.2 eV). It will also be appreciated that in embodiments where the band edge offset is small, doping may be at the heterojunction (between the semiconductor material S1 in the channel-containing region 100 and the semiconductor material S2 in the semiconductor material alloy 106) such that no significant barrier to carrier flow occurs at the heterojunction interface during operation of the device.
It will be appreciated that the band alignment diagrams shown in fig. 4-8 are representative of the material properties of the layers described herein (such as S1, S2, S3, etc.), and are not representative of the specific band diagram of the device in a particular mode of operation. In fig. 4 and 6, CBE for example indicates the band edge, fig. 4 and 6 correspond to a possible embodiment shown as nMOS device. It will be appreciated that a similar approach may be applied to pMOS devices (in which case the illustrated band edges would correspond to valence band edges). In fig. 5, 7 and 8, VBE refers to the valence band edge, and fig. 5, 7 and 8 correspond to a possible embodiment shown as a pMOS device. It will be appreciated that a similar scheme may be applied to nMOS devices (in which case the illustrated energy band edge would correspond to the conduction band edge). Many other figures are possible within the scope of the invention.
Fig. 4 is a schematic illustration of a linear composition graded profile of semiconductor material alloy 106 in source/drain regions 107. It will be appreciated that the schematic illustration shown in fig. 4 may be applied to an embodiment in which the device shown in fig. 1 is an nMOS device. Referring to fig. 1 and 4, the location at x-1 refers to the interface 102 between the channel region 100 and the source/drain regions 107, where the alloy of semiconductor material 106 includes semiconductor material S2 but is devoid of semiconductor material S3. In some embodiments, at the interface 102, the semiconductor material alloy 106 includes the semiconductor material S2 and a small amount of S3 (i.e., S2-rich, S3-lean).
As shown in fig. 4, the composition of semiconductor material S2 and semiconductor material S3 in alloy 106 may vary linearly with position within source/drain regions 107. It will be appreciated that all materials S1-S3, as well as all intermediate materials expressed by the relationships shown above, are stable or metastable within the thermal budget used in the processing and application of the device. Further, the semiconductor material alloy 106 may be doped simultaneously during epitaxial growth of the semiconductor material alloy 106.
Further, the semiconductor material S3 present at the metal contact interface portion 105 to the metal contact 101 is selected to provide a relatively small schottky barrier height (e.g., equal to or less than about 0.2eV) for the relevant carriers at the metal contact 101. It will be appreciated that the compositional grading of the semiconductor material in the semiconductor material alloy 106 provides relatively small variations in composition throughout the source/drain regions 107. Furthermore, in some embodiments according to the invention, sufficient doping is applied throughout the structure so that the shield effectively eliminates any potential barrier to the transport of the associated carriers that would otherwise occur due to the change in band edge position caused by the compositional grading.
It will be appreciated that the above description relating to shielding the barrier to carrier transport with a smooth compositional grading may be provided by enabling the variation of the band edge to be maintained at a particular level for a certain distance in the source/drain regions. In some embodiments according to the invention, for about 1E18cm-3The smooth compositional grading is such that the position of the band edge of the associated carrier changes by about 0.1eV or more at about 6 nm. In some embodiments according to the invention, for about 1E19cm-3The smooth compositional grading is such that the position of the band edge of the associated carrier changes by about 0.1eV or more at about 2 nm. In some embodiments according to the invention, for about 1E20cm-3The smooth compositional grading is such that the position of the band edge of the associated carrier changes by about 0.1eV or more at about 0.6 nm.
It will also be appreciated that certain degrees of doping may be used in source/drain regions having a particular band edge variation over a particular distance when doping is provided such that the barrier to carrier transport is effectively shielded by compositional grading.
Referring to FIG. 1, in some implementations according to the inventionIn an example, it will be appreciated that the doping of layer 105 may be used to provide a low metal contact interface resistance as desired herein. For example, for contacts with very low schottky barrier heights and for materials in layer 105 with small tunneling effective mass, several times more than 1E19cm-3The doping concentration of (c) may be sufficient. In some embodiments, 1E20cm may be used in 105-3Or higher doping concentration. In most cases, a high doping concentration in 105 can produce low contact resistivity even for small schottky barrier heights (such as with InAs contact).
Thus, in some embodiments, the highest doping concentration that is practical may be used in 105.
Similarly, high doping can be used with small heterojunction band-edge shifts, where higher doping can provide smaller heterojunction interface resistance. In some embodiments, greater than 1E19cm may be used-3The degree of doping of (a). In some embodiments, about 1E20cm may be used-3Or a higher doping level.
In some embodiments, for example, the arrangement shown in fig. 4 is an nMOS device: s1 can be Si, SiGe alloy or Ge; s2 may be GaAs or In-Ga-N or In-Ga-As-N alloys or In-Al-Ga-As alloys or Al-Ga-As alloys having a composition selected to be In-Ga-N or In-Ga-As-N or In-Al-Ga-As or Al-Ga-As alloys such that the conduction band edge is within about 0.2eV or less of the conduction band edge of S1; s3 may be InAs, InN or an In-As-N alloy or an In-Al-As alloy or an In-Ga-As alloy (preferably having an indium rich composition In the case of an In-Al-As alloy or an In-Ga-As alloy). In some embodiments, if S2 is GaAs, S3 is substantially InAs. In some embodiments, S3 is doped to be greater than 1E19cm-3. In some embodiments, the doping of S3 is up to about 1E20cm-3Or higher. In some embodiments, metal contact 101 is formed from a refractory metal or transition metal such that metal contact 101 is a reactive transition metal-S3 alloy. The compositional grading of the alloy may be linear as shown in FIG. 4 or non-linear as shown in FIG. 5, or stepped as shown in FIG. 6.
The metal selected to contact the semiconductor material alloy 106 at the metal contact interface portion 105 (i.e., semiconductor material S3) is selected to provide a low schottky barrier height for the majority carriers (e.g., equal to or less than about 0.2 eV). In some embodiments according to the invention, the metal contacts 101 may be reactive metal contacts. In some embodiments according to the invention, metal contact interface portion 105 comprising semiconductor material S3 is implemented to provide a low interfacial contact resistivity.
It will be appreciated that fig. 5 and 6 show alternative profiles (profiles) for the compositional grading of the semiconductor material alloy 106. Specifically, fig. 5 shows a non-linear compositional graded profile of semiconductor material alloy 106, while fig. 6 shows a stepped compositional graded profile for semiconductor material alloy 106. It will be understood that the schematic diagrams of fig. 4 and 6 refer to nMOS devices. It will be appreciated that the schematic diagrams of figures 5, 7 and 8 refer to pMOS devices. However, it will also be appreciated that the same principles described above with reference to nMOS may be applied to pMOS devices and vice versa.
In some embodiments, for example, the arrangement shown in fig. 1 is an nMOS device: s1 can be Si, SiGe alloy or Ge; s2 may be GaAs or In-Ga-N or In-Ga-As-N alloys or In-Al-Ga-As alloys or Al-Ga-As alloys having a composition selected to be In-Ga-N or In-Ga-As-N or In-Al-Ga-As or Al-Ga-As alloys such that the conduction band edge is within about 0.2eV or less of the conduction band edge of S1; s3 may be InAs, InN or an In-As-N alloy or an In-Al-As alloy or an In-Ga-As alloy (preferably having an indium rich composition In the case of an In-Al-As alloy or an In-Ga-As alloy). In some embodiments, if S2 is GaAs, S3 is substantially InAs. In some embodiments, S3 is doped to be greater than 1E19cm-3. In some embodiments, the doping of S3 is up to about 1E20cm-3Or higher. In some embodiments, metal contact 101 is formed using a refractory metal or a transition metal, such that metal contact 101 is a reactive refractory metal-S3 alloy or a reactive transition metal-S3 alloy, respectively.
Referring to fig. 1 and 4-6, the semiconductor material alloy 106 has sufficient doping at the surface so that it can provide an interface to the metal contact 101 with a low contact resistivity. In some embodiments, the semiconductor metal alloy 106 has sufficient doping such that the carriers effectively find no barrier to the on state of the device. The profile of the graded composition of the semiconductor material alloy 106 may also be adjusted to optimize device function, e.g., reduce diffusion into the channel, etc. In some embodiments, lightly doped epitaxy may also be formed. In some embodiments, once a lightly doped epitaxy is achieved (from source/drain towards channel), the band edge position of the material used does not change significantly. In other words, the compositional grading may be contained entirely within the highly doped regions, and the interface to semiconductor material S1 should also be contained within the highly doped regions of the source/drain regions.
Figure 7 is a schematic illustration of a compositional graded profile from the channel region 100 to the semiconductor material alloy 106 as an intermediate semiconductor material to the interface of the metal contact 101 in some embodiments according to the invention. According to fig. 7, semiconductor material S2 is selected for the channel region 100 and is also selected for inclusion in the alloy 106 along with semiconductor material S3. Furthermore, according to the relation S2xS31-xTo provide a graded profile of the composition of the alloy comprising S2 and S3, where x is 1 at the interface 102 between the channel region 100 and the semiconductor material alloy 106 in the source/ drain region 107 and 0 at an intermediate position of the source/drain region 107 that provides an interface to the semiconductor material S4 shown.
It will be understood that all semiconductor materials (S2, S2)xS31-xAnd S3) is stable or metastable within the thermal budget used in the processing and application of the device. Furthermore, the semiconductor material may be doped corresponding to a pMOS device or an nMOS device during epitaxial growth of the semiconductor material alloy 106. It will be appreciated that while the compositional ramp shown in fig. 7 appears as a non-linear function, other types of ramps (such as other types of continuous ramps or stepped ramps) may also be used.
It will be appreciated that the compositional grading in the alloy 106 is provided smoothly (i.e., provides small variations in composition throughout the x value in the source/drain regions 107) and provides a degree of doping such that the shielding effectively eliminates any potential barrier to carrier transport that may arise due to the change in band edge position throughout the alloy 106 caused by the grading.
Semiconductor material S4 is substantially different from semiconductor material S3, forming a heterojunction therebetween, wherein the heterojunction has a relatively small offset (i.e., equal to or less than about 0.2eV) between the band edges of the majority carriers for the device. It will also be appreciated that where there is a small band offset at the heterojunction, sufficient doping can be applied to the heterojunction to shield any potential barriers to carriers flowing at the heterojunction.
It will also be understood that the semiconductor material S4 is also selected to provide a relatively small schottky barrier height to the metal contact 101 (e.g., equal to or less than about 0.2 eV). In some embodiments according to the invention, the metal contact 101 may be a reactive metal contact (i.e., a metal or metallic material resulting from a reaction between a metallic material and the semiconductor material S4). In some embodiments according to the invention, doping may be applied at the interface between the semiconductor material S4 and the metal contact 101 to provide low interfacial contact resistivity.
Figure 8 is a schematic illustration of two graded composition profiles of two alloys of semiconductor material within drain/source region 107 in some embodiments according to the invention. According to fig. 8, a first alloy may include semiconductor material S2 and semiconductor material S3, the first alloy having a composition that changes the alloy from S2 at the interface of the channel region 100 to semiconductor material S3 at the interface of the second graded composition alloy. As shown in fig. 8, the second graded composition alloy includes semiconductor material S4 and semiconductor material S5, and transitions from semiconductor material S4 at the interface of semiconductor material S3 to semiconductor material S5 providing metal contact interface portion 105 to metal contact 101. It will be appreciated that in the schematic shown in figure 8 the band offset at the heterojunction is small, preferably less than about 0.2eV, and doping may be employed throughout the heterojunction, wherever it exists. In some embodiments of nMOS devices with high germanium SiGe (e.g., 90% germanium or higher) or S1 with germanium, S2 ═ S1, S3 may be a low germanium content SiGe alloy (e.g., SiGe with 60% germanium), S4 may be GaAs, and S5 may be InAs. In some embodiments of nMOS devices with high germanium SiGe (e.g., 90% germanium or higher) or S1 with germanium, S2 ═ S1, S3 may be a low germanium content SiGe alloy (e.g., SiGe with 60% germanium), S4 may be GaAs, and S5 may be InAs. In some embodiments of pMOS devices In which S1 and S2 may be In-Ga-Sb alloys In the channel, S3 may be In-Ga-Sb alloys, S4 may be SiGe alloys, and S5 is a high germanium SiGe alloy or germanium.
As described herein, in some embodiments according to the invention, a low resistivity contact may be provided to the semiconductor material (S1) in the channel region by forming a semiconductor alloy (consisting of composition S2 and composition S3) having a smoothly graded composition between the channel region of the device and the metal contact. For example, the compositional grading in the semiconductor alloy may be: the contributions of S2 and S3 in the alloy vary gradually as a function of position within the source/drain regions. For example, the compositional grading of the alloy may be arranged such that the semiconductor alloy is substantially S2 proximate the channel region, whereas the semiconductor alloy is substantially S3 distal the metal contact of the channel region.
Further, each of the semiconductor materials included in the alloy (consisting of the composition S2 and the composition S3) may be selected to have a specific relationship with respect to the semiconductor material in the channel (S1). For example, semiconductor material S2 may be selected to have a band edge that is close to the band edge of semiconductor material S3 compared to the band edge of semiconductor material S1 (i.e., the low energy band edge is offset). However, the semiconductor material S3 may be selected to have a relatively large band edge offset relative to the channel semiconductor material S1. The semiconductor material S3 may be selected to have a low contact resistivity to metal (preferably 10-8 Ω -cm 2 or less, and in some embodiments 10-7 Ω -cm 2 or less). Furthermore, the compositional grading of the semiconductor alloy (consisting of composition S2 and composition S3) in the source/drain regions should be smooth in order to avoid any abrupt changes in the band edges of the relevant carriers in the source/drain regions.
Thus, as understood by the present inventors, the semiconductor material S3 and the semiconductor material S1 in the channel region are selected such that one (e.g., S3) cannot be obtained from the other (e.g., S1) by using a continuous compositional grading. In other words, the semiconductor material S2 may be used as an intermediate material that is relatively close to the energy band edge of S1 but may also be present in the alloy with S3.
The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the inventive concept. Thus, to the maximum extent allowed by law, the scope is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

Claims (16)

1. A semiconductor device, comprising:
a channel region comprising a first semiconductor material for majority carriers in the channel region during operation of the device;
a metal contact;
a source/drain region comprising an alloy of semiconductor material comprising a second semiconductor material; and
at least one heterojunction in the source/drain region between the metal contact and the channel region,
wherein the at least one heterojunction forms a band edge offset for majority carriers, the band edge offset being less than or equal to 0.2eV,
wherein the semiconductor material alloy comprises a graded composition of the second semiconductor material and a third semiconductor material,
wherein the second semiconductor material is not completely mixed with the first semiconductor material,
wherein the graded composition comprises a third semiconductor material rich concentration and a second semiconductor material lean concentration at an interface of the first semiconductor material of the channel region and progresses to the third semiconductor material lean concentration and the second semiconductor material rich concentration at an interface of the metal contact.
2. The semiconductor device of claim 1, wherein a region of the at least one heterojunction is doped with a dopant having a conductivity type corresponding to a conductivity type of the majority carriers.
3. The semiconductor device of claim 1, wherein the graded composition of the semiconductor material alloy is comprised of S3xS21-xWhere S3 is the third semiconductor material, S2 is the second semiconductor material, x is 0 at the interface of the metal contact, and x is 1 at the interface of the first semiconductor material.
4. The semiconductor device of claim 3, wherein the increment in the graded composition of the alloy of semiconductor material is configured to prevent an energy band offset between adjacent levels in the graded composition from being greater than 0.2 eV.
5. The semiconductor device of claim 1, wherein the source/drain region comprises one of the second semiconductor material and the semiconductor material alloy at the interface of the metal contact and wherein the respective materials of the one of the metal contact and the second semiconductor material and the semiconductor material alloy at the interface of the metal contact are selected to provide a schottky barrier height therebetween that is equal to 0.2eV or less.
6. The semiconductor device of claim 1, wherein the graded composition is a linear graded composition, a non-linear graded composition, a stepped graded composition, or a combination thereof.
7. The semiconductor device of claim 1, wherein the first semiconductor material comprises at least one group IV semiconductor element and the second semiconductor material comprises a group III-V semiconductor compound or a group III-V semiconductor alloy.
8. The semiconductor device of claim 1, wherein the semiconductor device comprises an NMOS device, the first semiconductor material comprises silicon, a silicon germanium alloy, or germanium, the second semiconductor material comprises InAs, InN, an In-As-N alloy, an In-Al-As alloy, or an In-Ga-As alloy, and the third semiconductor material comprises GaAs, an In-Ga-N, In-Ga-As-N alloy, an In-Al-Ga-As alloy, or an Al-Ga-As alloy.
9. A semiconductor device, comprising:
a channel region comprising a first semiconductor material for majority carriers in the channel region during operation of the device;
a metal contact;
a source/drain region comprising an alloy of semiconductor material comprising a second semiconductor material; and
at least one heterojunction in the source/drain region between the metal contact and the channel region, wherein the at least one heterojunction forms a band edge offset for majority carriers that is less than or equal to 0.2eV,
wherein the semiconductor material alloy comprises graded components of the first semiconductor material and the second semiconductor material,
wherein the graded composition comprises a first semiconductor material rich concentration and a second semiconductor material lean concentration at an interface of the first semiconductor material of the channel region and progresses away from the interface to the first semiconductor material lean concentration and the second semiconductor material rich concentration to form the at least one heterojunction with a third semiconductor material,
wherein the third semiconductor material is not completely mixed with the first semiconductor material.
10. A semiconductor device, comprising:
a channel region comprising a first semiconductor material for majority carriers in the channel region during operation of the device;
a metal contact;
a source/drain region comprising an alloy of semiconductor material comprising a second semiconductor material; and
at least one heterojunction in the source/drain region between the metal contact and the channel region, wherein the at least one heterojunction forms a band edge offset for majority carriers that is less than or equal to 0.2eV,
wherein the semiconductor material alloy comprises a first graded composition of the second semiconductor material and a third semiconductor material,
wherein the first graded composition comprises a second semiconductor material concentration that is lean at an interface of the first semiconductor material of the channel region and progresses away from the interface to a second semiconductor material concentration that is rich,
wherein the second semiconductor material is not completely mixed with the first semiconductor material,
wherein the semiconductor material alloy is a first graded composition alloy,
the semiconductor device further includes:
a second graded composition alloy located in the source/drain region between the channel region and the first graded composition, the second graded composition alloy comprising a second graded composition of a fourth semiconductor material and a fifth semiconductor material, the fifth semiconductor material not being completely mixed with the first semiconductor material.
11. An electronic device, comprising:
a channel region comprising a first semiconductor material for majority carriers in the channel region during operation of the device;
a metal contact; and
a source/drain region comprising a material alloy that includes at least one semiconductor material composition and is free of an entirety of the composition of the first semiconductor material such that compositional grading of the material alloy between interfaces of the channel region and the metal contact avoids abrupt changes in band edge offset between increments in the compositional grading and at any heterojunction,
wherein the material alloy comprises a graded component of the at least one semiconductor material component,
wherein the graded composition comprises a lean semiconductor concentration of the at least one semiconductor material composition at an interface of the first semiconductor material of the channel region and progresses to a rich semiconductor concentration of the at least one semiconductor material composition at the interface of the metal contact,
wherein the first semiconductor material and the material alloy at the interface of the first semiconductor material form a heterojunction having a band edge offset for the majority carriers that is less than or equal to 0.2 eV.
12. The electronic device of claim 11, wherein the band edge offset for majority carriers is less than or equal to 0.1 eV.
13. The electronic device of claim 12, wherein the material alloy is doped to 1E18cm-3To 1E20cm-3Within the range of (a).
14. The electronic device of claim 13, wherein the band edge shifts between increments are in a range between a 6nm increase of 0.1eV and a 0.6nm increase of 0.1 eV.
15. An electronic device termination structure comprising:
a metal contact;
a graded composition layer including a first material S1 and a second material S2, the first material S1 and the second material S2 being in accordance with a composition S1 within the graded composition layerxS21-xProviding a graded composition in combination with each other, wherein the composition of the graded composition layer is entirely the second material S2 at x-0 near the metal contact and the composition of the graded composition layer is entirely the first material S1 at x-1 away from the metal contact, wherein the composition of the graded composition layer between x-0 and x-1 is sufficient to avoid band edge offset of selected carriers of the electronic device within the graded composition layer of greater than 0.2 eV;
a third material S3 in contact with the graded composition layer at x ═ 1, the third material S3 being selected to form a heterojunction equal to or less than 0.2eV with the first material S1; and
wherein the second material S2 is selected to provide a schottky barrier height to the metal contact that is equal to or less than 0.2 eV.
16. The electronic device termination structure of claim 15 wherein S1, S2, and S3 are configured to each operate as a semiconductor material in the device.
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