KR20160063280A - Semiconductor device including heterojunctions for low contact resistance - Google Patents

Abstract

A semiconductor device includes: a channel region having a first semiconductor material for a plurality of carriers; and a metal contact. A source / drain region includes: a second semiconductor material; and at least one heterojunction between the metal contact and the channel region. The heterojunction forms a band-edge offset that is less than or equal to about 0.2 eV.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor device having low-resistance heterojunctions,

The present invention relates to integrated circuit devices, and more particularly to integrated circuit devices using materials configured to operate with a semiconductor.

As MOS devices become more highly integrated, parasitic resistance becomes more and more a problem. Parasitic resistance can make a significant contribution to the resistance at each new node compared to the previous nodes and can be a factor in the performance of such devices. In addition, for example, special materials selected for use in the channel of a MOS device may not always be suitable for low resistance contacts.

Parasitic resistances are described in detail in U. S. Patent Nos. 2006/020226 and 2009/0166742.

U.S. Patent Publication No. 2006/020226 U.S. Patent Publication No. 2009/0166742

Non-Patent Document 1: Jenny Hu, H.-S. Philip Wong and Krishna Saraswat " Novel contact structures for high mobility channel materials ", MRS Bulletin, Vol.36, 2011, pp 112-120 Non-Patent Document 2: Hideki Hasgawa and Masamichi Akazawa, "Current Transport, Fermi Level Pinning, and Transient Behavior of Group-III Nitride Schottky Barriers," Journal of the Korean Physical Society, Vol 55, No. 3, 1179 Non-Patent Document 3: Sandip Tiwari and David J. Frank, " Empirical fit to band discontinuities and barrier heights in III-V alloy systems ", Appl. Phys. Lett. 60, 630 (1992) Non-Patent Document 4: Jesus A. del Alamo, Nanometer-scale electronics with III-V compound semiconductors, Nature 479, 317-323 (17 November 2011)

The present invention is to provide a semiconductor device or electronic device having a low-resistance contact.

Embodiments in accordance with the present invention can provide a device contact structure having a low resistance heterojunction. According to these embodiments, the semiconductor device may include a channel region having a first semiconductor material for a majority carrier during operation of the semiconductor device, and a metal contact. The source / drain region may comprise a semiconductor material alloy comprising a second semiconductor material, and at least one heterojunction disposed between the metal contact and the channel region. Here, the heterojunction forms a band-edge offset of 0.2 eV or less of majority carriers.

In some embodiments according to the present invention, the semiconductor material alloy may have a spatially varying composition of the second semiconductor material and the third semiconductor material, and the third semiconductor material is not completely mixed with the first semiconductor material (fully miscible). That is, as the composition of the semiconductor material alloy continuously changes, it is not possible to obtain the third semiconductor material from the first semiconductor material.

In some embodiments according to the present invention, the band-edge offset of the heterojunction may be approximately 0.0 eV.

In some embodiments according to the present invention, the band-edge offset of the heterojunction is 0.2 eV or less, and the region of the heterojunction may be doped with a dopant related to the conductivity of the majority carriers.

In some embodiments according to the present invention, the change in the spatial composition of the semiconductor material alloy may result from a concentration of the second semiconductor material at the interface with the first semiconductor material of the channel region and a concentration of the third semiconductor material at the lean concentration Material, the second semiconductor material is depleted at the interface with the metal contact, and the third semiconductor material is changed to have a rich concentration.

In some embodiments according to the present invention, the spatial compositional change of the semiconductor material alloy can be denoted by S2 _x S3 _1-x . Here, S2 is the second semiconductor material and S3 is the third semiconductor material. In some embodiments, x = 0 at the interface with the metal contact and x = 1 at the interface with the first semiconductor material.

In some embodiments according to the present invention, an increment in the spatial compositional change of the semiconductor material alloy may be such that the band-edge offset between immediate adjacent portions in the spatially varying composition is prevented from exceeding 0.2 eV Lt; / RTI >

In some embodiments according to the present invention, the electronic device may include a channel region having a first material for a plurality of carriers during operation of the electronic device, and a metal contact. The source / drain region may comprise a material alloy having at least one material component, the source / drain region free of all components of the first material, the material between the interface with the metal contact and the channel region Edge offset between the increment in the composition where the spatial compositional change of the alloy is spatially varied can be prevented from changing abruptly.

In some embodiments according to the present invention, the first material may have a first lattice structure, and the material alloy may have a second lattice structure different from the first lattice structure. Hence, a heterojunction with a band-edge offset of 0.2 eV or less for a majority carrier can be formed.

In some embodiments according to the present invention, the semiconductor device may include a channel region having a first semiconductor material for a majority carrier during operation of the semiconductor device, and a metal contact. The source / drain region includes a first portion located adjacent a channel region having a second semiconductor material, a spatially varying composition of the second semiconductor material, and a semiconductor material alloy comprising a third semiconductor material can do. The source / drain region may comprise another portion adjacent the metal contact having the fourth semiconductor material. Here, the interface between the first and second portions of the source / drain regions is a heterojunction where the band-edge offsets of the majority carriers are 0.2 eV or less, and is doped with a dopant type associated with the majority carriers. In some such embodiments, materials may be selected such that no heterojunction is formed between the channel region and the portion of the source / drain region adjacent to the channel. For example, in some embodiments, the semiconductor material alloy may be spatially graded such that the semiconductor material alloy is substantially the first semiconductor material at the interface with the channel. In other embodiments, a second heterojunction doped with a dopant type that has a band-edge offset of 0.2 eV or less for a majority carrier and is associated with a majority carrier may be present between the semiconductor material alloy and the first semiconductor material.

In some embodiments according to the present invention, the electronic device comprises a metal contact, and a layer comprising a first material (S1) and a second material (S2) and having a spatially varying composition, denoted by S2 _x S3 _{1 -x} . ≪ / RTI > The composition of the layer is completely S2 adjacent to the metal contact with x = 0, completely away from the metal contact x = 1, and the composition between x = 0 and x = And a band edge offset of 0.2 eV or less. The third material S3 is in contact with the layer at a location remote from the metal contact x = 1 and the third material S3 has a band-edge offset of the heterojunction with the first material S1 of less than or equal to 0.2 eV And the second material S2 is selected so that the Schottky barrier height with the metal is 0.2 eV or less.

In some embodiments according to the present invention, the electronic device comprises a metal contact, and a layer comprising a first material (S1) and a second material (S2) and having a spatially varying composition, denoted by S2 _x S3 _{1 -x} . ≪ / RTI > The composition of the layer is completely S2 adjacent to the metal contact with x = 0, completely away from the metal contact x = 1, and the composition between x = 0 and x = And a band edge offset of 0.2 eV or less. The third material S3 is positioned to isolate the metal contact from the layer and is adjacent to the layer at a location x = 0 and the third material S3 is adjacent to the band-edge of the heterojunction with the second material S2 The offset is selected to be 0.2 eV or less, and the Schottky barrier height with the metal is selected to be 0.2 eV or less.

According to embodiments of the present invention, in a semiconductor device or an electronic device, a low-resistance contact can be obtained.

1 is a cross-sectional view of a channel region, in accordance with some embodiments in accordance with the present invention.
Figures 2 and 3 are cross-sectional views of a channel region, in accordance with some embodiments in accordance with the present invention.
Figure 4 schematically illustrates a linear compositional change profile of a semiconductor material alloy between a channel region material and a metal contact, in accordance with some embodiments in accordance with the present invention.
Figure 5 schematically illustrates a nonlinear compositional change profile of a semiconductor material alloy between a channel region material and a metal contact, in accordance with some embodiments in accordance with the present invention.
Figure 6 schematically depicts a stepped compositional change profile of a semiconductor material alloy between a channel region material and a metal contact, in accordance with some embodiments in accordance with the present invention.
Figure 7 schematically illustrates a compositional change profile of a semiconductor material alloy between an interfacial material and a channel region material adjacent to a metal, in accordance with some embodiments in accordance with the present invention.
Figure 8 schematically illustrates a compositional change profile of first and second semiconductor material alloys between a channel region material and a metal contact, according to some embodiments in accordance with the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present invention will become more readily apparent from the following description of preferred embodiments with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In this specification, when it is mentioned that a film (or layer) is on another film (or layer) or substrate, it may be formed directly on another film (or layer) or substrate, or a third film (Or layer) may be interposed. In the drawings, the sizes and thicknesses of the structures and the like are exaggerated for the sake of clarity. It should also be understood that although the terms first, second, third, etc. have been used in various embodiments herein to describe various regions, films (or layers), etc., It should not be. These terms are merely used to distinguish any given region or film (or layer) from another region or film (or layer). Each embodiment described and exemplified herein also includes its complementary embodiment. The expression " and / or " is used herein to mean including at least one of the elements listed before and after. Like numbers refer to like elements throughout the specification.

Hereinafter, embodiments according to the concept of the present invention will be described in detail with reference to the drawings.

Although the various embodiments described herein relate to semiconducting materials in transistors, it is to be understood that other types of materials (semi-metal materials, semi- A degenerate semiconductor material, and combinations thereof) may be used.

While the various embodiments described herein illustrate a finFET structure as a channel region, other types of transistor structures (planar transistors, nanowire transistors, MOSFET, etc.) may be used in the present invention .

The term "band-edge " in connection with a particular material refers to a conduction band in a reference material that depends on the conductivity type of the charge carrier used during the operation of the device (e.g., pMOS, nMOS) Will refer to a band-edge or a consumer-band-edge. Thus, the term "band-edge" may be used by referring to a "relevant carrier" without specifying the type of device. In a pMOS device, the associated carrier is a hole and the band edge is a valence band edge. In an nMOS device, the associated carriers are electrons and the band edge is the conduction band edge.

A "low contact resistivity" may be related to an interface contact resistance value of less than or equal to about 10 ^-8 ohm-cm 2. In some embodiments, it may be related to interface contact resistance values of about 10 ^-7 ohm-cm 2 or less. The term "low Schottky barrier height (SBH)" or "low barrier" of metals in contact with the semiconductor material will include a value of about 0.2 eV or less. Quot; or similar term will include a value of about 0.2 eV or less when used in connection with the band offset between the band edges of the relevant carrier at the heterojunction between two different materials. "Small" Or similar terms when used in connection with a band offset formed by an increment or step in the compositional grading of the composition of a material, a value of about 0.2 eV or less (preferably, about 0.1 eV or less) .

For example, a representation of the form S2 _x S3 _{1 -x} indicates that the second and third semiconductor materials S2 and S3 are formed such that the third semiconductor material S3 is 1-x and the second semiconductor material S2 is x Which is the relative composition of the alloy. Here, 0 < x < 1. The alloy S2 _x S3 _{1 -x} may be included in the same region as the source / drain region, and the composition of the alloy (denoted by variable x) may vary depending on the location in the region. The terms "lean" or "rich" can be used to refer to the ratio of a particular material. For example, S2 _x S3 _{1 -x} rich in second semiconductor material S2 is S2 _x S3 _{1 -x} alloy where _x is close to 1. For example, S2 _x S3 _{1 -x where} the second semiconductor material S2 is deficient is S2 _x S3 _{1 -x} alloy where _x is close to zero.

The term semiconductor material can refer to a semiconductor material that includes only one element, or a semiconductor material compound that includes one or more elements. The term semiconductor alloy material refers to a semiconductor material comprising at least two different elements.

In some embodiments according to the present invention, by forming semiconductor alloys (S2 and S3) with a smoothly graded composition between the channel region of the device and the metal contact, the first semiconductor material A low resistance contact may be provided in the step S1. For example, the compositional grading of the composition in the semiconductor alloy may be such that the ratio of the second semiconductor material S2 to the third semiconductor material S3 in the alloy gradually changes with the location in the source / Can be changed. For example, if the semiconductor alloy is close to the channel region and is substantially the second semiconductor material S2, then the spatial variation of the alloy composition is such that the metal contact remote from the channel region is substantially the third semiconductor material S3 Can be provided.

In addition, each of the semiconductor materials included in the alloy of the second semiconductor material S2 and the third semiconductor material S3 may be selected to have a specific relationship to the first semiconductor material S1 in the channel region. For example, the second semiconductor material S2 may have a band edge (e.g., a low band edge offset) that is relatively close to the band edge of the first semiconductor material S1 relative to the band edge of the third semiconductor material S3. Lt; / RTI &gt; However, the third semiconductor material S3 may be selected to have a relatively large band edge offset relative to the first semiconductor material S1 in the channel region. In addition, in order to avoid abrupt changes in the band edge in the source / drain regions for the associated carriers, the composition of the semiconductor alloy of the second semiconductor material S2 and the third semiconductor material S3 in the source / The composition grading should be smooth.

Therefore, the first semiconductor material S1 and the third semiconductor material S3 can be electrically connected to each other through a spatial grading of the continuous composition such that one (for example, the third semiconductor material S3) For example, the first semiconductor material S1). That is, the second semiconductor material S2 may be used as an intervening material, which is relatively close to the band edge of the first semiconductor material S1 but is present as an alloy with the third semiconductor material S3.

Thus, the first semiconductor material S1 can be selected to have a significantly lower band edge offset than the second semiconductor material S2. Further, the spatial variation of the composition of the semiconductor alloy from the channel region to the metal contact (spaced from the channel region) gradually increases the third semiconductor material S3 and is used to decrease the second semiconductor material S2 . The third semiconductor material S3 present in the metal contact may be selected to provide a relatively low Schottky barrier height of the relevant carrier.

3 of Non-Patent Documents 1 and 4 of Non-Patent Document 2 show respective band arrangements in other semiconductor materials / compounds / alloys that can be used in devices according to the present invention. According to these materials, some semiconductor materials are in contact with the metal to exhibit Fermi Level Pinning (in some cases, strong Fermi level pinning). In this case, the Schottky barrier formed on the metal semiconductor interface does not depend on the work function of the metal. The Fermi level pinning position is close to the charge neutrality level. 3 of Non-Patent Document 1 and FIG. 4 of Non-Patent Document 2 are combined as a part of the present invention.

Referring to FIG. 3 of Non-Patent Document 1 and FIG. 4 of Non-Patent Document 2, the charge neutrality level appears in some semiconductor materials. In some embodiments, the semiconductor material selected to form the metal contact has a Fermi level pinning or a strong Fermi level pinning at a location near the associated carrier band edge. Thereby contacting the metal to provide a low Schottky barrier height to the associated carriers.

Pinning in the InGaSb alloy may be close to the valence band edge. In InGaAs, InGaN and AlGaN alloys, the absolute position of the charge neutral level may vary little depending on the composition. In some embodiments, InAs, In-rich In-Ga-As alloys, InN, and In-rich-InGa-N alloys may be suitable for semiconductor materials used as an alloy interface with metal contacts in nMOS devices. Due to the low bandgap, InSb will be suitable for nMOS and PMOS devices. In pMOS devices, Ge, InSb, GaSb and In-Ga-Sb alloys may be suitable as semiconductor materials used as the alloy interface with metal contacts.

Figure 1 of Non-Patent Document 3 is a graph showing lattice constants and band edge positions of other semiconductor materials in some embodiments according to the present invention. Thus, Figure 1 of the non-patent document 3 can be used to select combinations of materials suitable for use in the channel and source drain regions of the device. Figure 1 of Non-Patent Document 3 is incorporated as part of the present invention. Figure 1 of the non-patent document 4 is a graph showing the mobilities of some semiconductor materials and can be used to select the appropriate channel material. Figure 1 of Non-Patent Document 4 is incorporated as part of the present invention.

The spatial variation of the composition of the semiconductor material in the source / drain regions can be provided based on the semiconductor material used for the channel region as well as the semiconductor material selected for the interface with the metal contact. For example, in some embodiments according to the present invention, a SiGe alloy or Ge with high Ge concentration for nMOS or PMOS, Si for nMOS or PMOS, SeGe with pMOS, In-Ga-As alloy for nMOS , an In-As alloy for nMOS, or an In-Ga-Sb alloy for nMOS or PMOS may be used as a semiconductor material in the channel region. Each of the aforementioned parameters (e.g., the semiconductor material used in the interface with the metal contact and the semiconductor material used in the channel region) may be selected to satisfy the following two conditions. (1) The semiconductor material used in the channel region has a smooth composition and can not reach the semiconductor material used at the interface with the metal contact. The band edge offsets (for the associated carriers) between the semiconductor material used in the channel region and the semiconductor material selected at the interface with the metal contact are of significant size (e.g., greater than 0.2 eV).

As described above, the low-resistance contact can be provided using a spatial variation of the soft composition of the semiconductor alloy in the source / drain regions between the channel region and the metal contact. In all cases, the semiconductor materials included in the alloy are selected to effectively remove the barriers to carrier movement in the source / drain regions, despite the presence of heterojunctions (e.g., formed near metal contacts or channel regions) do. In all cases, the band edge offset provided in the heterojunction should be 0.2 eV or less for the relevant carrier.

The formation of the spatially smoothly varying alloying material can be performed through epitaxial growth in the source / drain regions of the selected materials to have the desired composition (S2 _x S3 _{1 -x} ) during the epitaxy growth process. In addition, the formation of alloying materials with a spatial composition of a soft composition can be obtained through the approach described in U.S. Patent Application No. 14 / 226,518 and U.S. Provisional Patent Application No. 61 / 859,932. The contents described in these can be combined with the present invention.

1 is a cross-sectional view of a semiconductor device adjacent a semiconductor material alloy 106 of a source / drain region 107 and having a channel region 100 comprising a first semiconductor material S1. In some embodiments according to the present invention, the semiconductor material alloy 106 includes a metal contact interface portion 105 with a metal contact 101. Although FIG. 1 and related teachings refer to the use of semiconductor materials, other types of materials may be used in the present invention. For example, materials that can operate on semiconductors (such as semi-metal or recessed semiconductors) may be used. Further, in some embodiments according to the present invention, FIGS. 2 and 3 illustrate modified shapes of the channel region 100 and the source / drain region 107. Accordingly, the shape of the apparatus shown in Fig. 1 is exemplary, and the present invention is not limited thereto.

1, a semiconductor material alloy 106 is deposited in the source / drain region 107, for example, from the interface 102 with the channel region 100 to the metal contact interface portion 105, Change. In other words, the composition of the semiconductor material alloy 106 varies with the location in the source / drain region 107. In some embodiments, the composition of the semiconductor material alloy 106 varies with the location in the source / drain region 107, resulting in a relatively low Schottky barrier height between the metal contact interface portion 105 and the metal contact 101 As well as a heterojunction with the first semiconductor material S1. In particular, the semiconductor material alloy 106 is epitaxially grown such that the second semiconductor material S2 is provided at the interface 102 and progressively decreases toward the metal contact interface portion 105. On the other hand, as the second semiconductor material S2 decreases, the third semiconductor material S3 gradually increases to reach the metal contact interface portion 105 due to the spatial grading of the semiconductor material alloy 106 The semiconductor material alloy 106 becomes the third semiconductor material S3.

In some embodiments, the first semiconductor material S1 of the channel region 100 forms a heterojunction with the second semiconductor material S2 at the interface 102. In some embodiments, The first semiconductor material S1 may be substantially different from the second semiconductor material S2 and the band edge offset from the second semiconductor material S2 to the first semiconductor material S1 may be relatively small For example, 0.2 eV or less). In embodiments where there is a small band edge offset, a heterojunction (the first semiconductor material S1 in the channel region 100 and the semiconductor material alloy &lt; RTI ID = 0.0 &gt;Lt; RTI ID = 0.0 &gt; (S2) &lt; / RTI &gt;

The band diagrams shown in FIGS. 4-8 illustrate the material properties of the layers (such as S1, S2, S3, etc.) described herein and are not particular band diagrams of the device in a particular mode of operation. For example, in Figures 4 and 6, CBE represents the conduction band edge and the diagrams refer to possible embodiments in nMOS devices. Similar schemes can be applied to pMOS devices (in this case, the illustrated band edge will be associated with a valence band edge). In Figures 5, 7 and 8, VBE represents the valence band edge and the diagrams refer to possible embodiments in pMOS devices. Similar schemes can be applied to nMOS devices (in this case, the illustrated band edge will be associated with the conduction band edge). Many other diagrams will be possible within the scope of the present invention.

Figure 4 shows a linear compositional change profile of the semiconductor material alloy 106 in the source / drain region 107. [ 4 may be applied to embodiments in which the device shown in FIG. 1 is an nMOS device. 1 and 4, a location x = 1 refers to the interface 102 between the channel region 100 and the source / drain region 107. At the interface 102, the semiconductor material alloy 106 includes the second semiconductor material S2 but does not contain the third semiconductor material S3 at all. In some embodiments, at the interface 102, the semiconductor material alloy 106 comprises a second semiconductor material S2 and the third semiconductor material S3 is a bit (e.g., a second semiconductor material S2) And the third semiconductor material S3 is less).

The composition of the second semiconductor material S2 and the third semiconductor material S3 in the semiconductor material alloy 106 varies linearly with the location in the source / drain region 107, as shown in Fig. All of the semiconducting materials S1, S2, S3 as well as all of the intermediates represented by the relational expressions shown above are stable or metastable to the thermal budget in the fabrication processes and operations of the devices, to be. Further, it may be doped during epitaxial growth of the semiconductor material alloy 106.

Further, the third semiconductor material S3 present in the metal contact interface portion 105 with the metal contact 101 has a relatively low Schottky barrier height (for example, 0.2 &lt; RTI ID = 0.0 &gt; eV or less). The compositional grading of the composition of the semiconductor materials within the semiconductor material alloy 106 is provided relatively less throughout the source / drain region 107. In addition, in some embodiments according to the present invention, such structures are sufficiently doped so that screening can effectively remove the barriers of associated carrier transport. The barriers of the associated carrier transport may be due to changes in the band edge positions created by the spatial variation of the composition.

The previous discussion of screening of the barriers for carrier transport using a smooth change in composition can be obtained by keeping the variation of the band edge at a certain level within a certain distance in the source / drain region at a certain level. In some embodiments according to the present invention, by doping approximately 1E18 / cm3, a smooth change in composition is the band edge position of the relevant carriers is a change of approximately 0.1 eV at about 6 nm. In some embodiments, by doping approximately 1E19 / cm3, a smooth change in composition is the band edge position of the relevant carriers is a change of approximately 2 eV by approximately 0.1 eV. In some embodiments, by doping approximately 1E20 / cm3, a smooth change in composition is a change in band edge position of the relevant carriers by approximately 0.1 eV at approximately 0.6 nm.

A constant doping level can be used to have a certain band edge variation at a certain distance when the barrier to carrier movement through the spatial variation of the composition is doped to effectively screen.

Referring to Figure 1, in some embodiments in accordance with the present invention, doping in the metal contact interface portion 105 may provide a low metal contact interface resistance. For example, in materials of very low Schottky barrier height, and materials of metal contact interface part 105 having small tunneling effective masses, a doping concentration of a few E19 / cm3 may be sufficient. In some embodiments, a doping concentration of 1E20 / cm &lt; 3 &gt; or more can be used for the metal contact interface portion 105. In most cases, even at low Schottky barrier heights, such as in the case of contacts with InAs, higher doping in the metal contact interface portion 105 can result in lower contact resistance.

Thus, in some embodiments, the highest concentration of doping that can be achieved in practice can be used for the metal contact interface portion 105.

Similarly, high doping can be used in the case of heterojunctions with small band edge offsets. Here, a higher concentration of doping can provide a lower heterojunction resistance. In some embodiments, doping levels greater than 1E19 / cm &lt; 3 &gt; can be used. In some embodiments, doping levels of about 1E20 / cm &lt; 3 &gt; or greater can be used.

For example, in some embodiments in which the arrangement shown in FIG. 4 is applied to an nMOS device, the first semiconductor material S1 may be Si, a SiGe alloy or Ge, the second semiconductor material S2 may be GaAs or In-Ga-N or the second semiconductor material S2 may be an In-Ga-As-N alloy, an In-Al-Ga-As alloy or an Al-Ga-As alloy The third semiconductor material S3 may be InAs or InN or the third semiconductor material S3 may be In or InN, or the third semiconductor material S3 may be In -As-N alloy, an In-Al-As alloy, or an In-Ga-As alloy. In the case of an In-Al-As alloy or an In-Ga-As alloy, it has a composition rich in In. If the second semiconductor material S2 is GaAs, then in some embodiments, the third semiconductor material S3 is substantially InAs. In some embodiments, the third semiconductor material S3 is greater than 1E19 / cm3 / RTI &gt; In some embodiments, the doping concentration of the third semiconductor material S3 is greater than or equal to 1E20 / cm3. In some embodiments, the metal contact 101 is formed of a refractory metal or a transition metal. Accordingly, the metal contact 101 is an alloy of the transition metal and the third semiconductor material S3. The compositional change of the alloy may be linear as shown in Fig. 4, nonlinear as shown in Fig. 5, or stepped as shown in Fig.

The metal in contact with the semiconductor material alloy 106 (i.e., the third semiconductor material S3) in the metal contact interface portion 105 has a low Schottky barrier height (e.g., about 0.2 eV or less) for many carriers, / RTI &gt; In some embodiments according to the present invention, the metal contact 101 may be a reactive metal contact. In some embodiments according to the present invention, the metal contact interface portion 105 comprising the third semiconductor material S3 has a low interface contact resistance.

FIGS. 5 and 6 illustrate a variation profile of the compositional change of the semiconductor material alloy 106. FIG. In particular, FIG. 5 shows the nonlinear compositional change profile of the semiconductor material alloy 106, while FIG. 6 shows the stepped compositional change profile of the semiconductor material alloy 106. 4 and 6 are for nMOS devices. 5, 7 and 8 are for pMOS devices. However, the principles described above with respect to nMOS can also be applied to pMOS devices as well.

For example, in some embodiments where the arrangement shown in Figure 1 is applied to an nMOS device, the first semiconductor material S1 may be Si, a SiGe alloy, or Ge, and the second semiconductor material S2 may be GaAs or In-Ga-N or the second semiconductor material S2 may be an In-Ga-As-N alloy, an In-Al-Ga-As alloy or an Al- The third semiconductor material S3 may be InAs or InN, or the third semiconductor material S3 may be In-As-In. Alternatively, the third semiconductor material S3 may have a composition such that the third semiconductor material S3 is within 0.2 eV of the conduction band edge E of the first semiconductor material S1, N alloy, an In-Al-As alloy, or an In-Ga-As alloy. In the case of an In-Al-As alloy or an In-Ga-As alloy, it has a composition rich in In. If the second semiconductor material S2 is GaAs, in some embodiments, the third semiconductor material S3 is substantially InAs. In some embodiments, the third semiconductor material S3 is doped to a concentration greater than 1E19 / cm3. In some embodiments, the doping concentration of the third semiconductor material S3 is greater than or equal to 1E20 / cm3. In some embodiments, the metal contact 101 is formed of a refractory metal or a transition metal. Accordingly, the metal contact 101 may be formed of an alloy of the refractory metal and the third semiconductor material S3, And an alloy of the semiconductor material S3.

Referring to Figures 1 and 4 to 6, the semiconductor material alloy 106 may have its surface sufficiently doped to provide a low contact resistance interface with the metal contact 101. In some embodiments, the semiconductor material alloy 106 has sufficient doping so that transport of carriers during operation of the device is not prevented. The profile of the changed composition of the semiconductor material alloy 106 may also be adjusted so that the function of the device is optimal (e. G., By reducing diffusion to the channel). In some embodiments, lightly doped regions may be formed. In some embodiments, as the lightly doped regions go from the source / drain region to the channel region, the band edge position of the materials used may not change significantly. In other words, the change in composition can be completely confined within the heavily doped region. Then, the interface with the first semiconductor material S1 must be confined within the heavily doped region of the source / drain region.

Figure 7 illustrates the compositional change profile of the semiconductor material alloy 106 from the channel region 100 to the interface semiconductor material with the metal contact 101, in some embodiments in accordance with the present invention. 7, the second semiconductor material S2 is selected as the channel region 100 and may be selected to be included in the alloy 106 along with the third semiconductor material S3. In addition, the composition change profile of the alloy including the second semiconductor material S2 and the third semiconductor material S3 is provided according to the relationship S2 _x S3 _{1 -x} . Where x = 1 at the interface 102 between the semiconductor material alloy 106 of the source / drain region 107 and the channel region 100 and a source / drain (not shown) providing the interface with the fourth semiconductor material S4 At the middle position of the region 107, x = 0.

Both semiconductor materials (S2, S2 _x S3 _{1 -x} and S3) are stable or metastable at the thermal load during the fabrication process and operation of the device. In addition, the semiconductor materials may be doped for pMOS or nMOS devices during epitaxial growth of the semiconductor material alloy 106. Although the composition variation shown in Fig. 7 is non-linear, other types of variation (such as a continuous change or a step change) can be used.

The spatial variation of the composition in the semiconductor material alloy 106 must be provided smoothly (e.g., to provide a small change in composition expressed in x value in the source / drain region 107) Provides a doping level that allows screening to effectively remove barriers to carrier movement that may occur due to changes in band edge positions throughout material alloy 106. [

The fourth semiconductor material S4 is substantially different from the third semiconductor material S3. Hence, a heterojunction is formed therebetween so as to have a relatively small offset between the band edges of the majority carriers of the device. When there is a small band offset in the heterojunction, sufficient doping can be provided to the heterojunction to eliminate the barrier to carrier flow in the heterojunction.

The fourth semiconductor material S4 will be selected to provide a relatively low Schottky barrier height (e.g., 0.2 eV or less) with the metal contact 101. In some embodiments according to the present invention, the metal contact 101 may be a reactive metal contact (e.g., a metallic material produced by the reaction of a metal or metal material with a fourth semiconductor material S4). In some embodiments according to the present invention, doping is provided at the interface between the fourth semiconductor material S4 and the metal contact 101 to provide a low interface contact resistance.

In the example of the pMOS device having the changed composition shown in Fig. 7, the fourth semiconductor material S4 is a Ge or Ge-rich SiGe alloy having a hetero junction with a GaSb or InCaSb alloy used as the third semiconductor material S3 Lt; / RTI &gt; The third semiconductor material S3 spatially changes to be another III-V material in the channel region 100. [ In some embodiments of pMOS devices, the fourth semiconductor material S4 may be a Ge-rich SiGe alloy having a heterojunction with an InAs alloy used as the third semiconductor material S3. The third semiconductor material S3 spatially changes to be InGaAs in the channel region 100. [

Figure 8 schematically illustrates the compositional change profiles of two semiconductor material alloys in source / drain region 107, in some embodiments in accordance with the present invention. According to Fig. 8, the first alloy comprises semiconductor materials S2 (which change the composition from the second semiconductor material S2 at the interface with the channel region 100 to the third semiconductor material S3 at the interface with the second alloy S2 , S3). 8, the second alloy includes fourth and fifth semiconductor materials S4 and S5, and the fourth semiconductor material S4 from the interface with the third semiconductor material S3, To a fifth semiconductor material (S5) providing a metal contact interface portion (105) with the contact (101). As there is a heterojunction in the manner shown in Fig. 8, the band offset in the heterojunction is small (preferably 0.2 eV or less) and can be doped over the entire heterojunction. In embodiments of the nMOS device in which the first semiconductor material S1 comprises SiGe (e.g., at least 90% Ge) or Ge having a high Ge concentration, the first semiconductor material S1 = the second semiconductor material S2), the third semiconductor material S3 may be a SiGe alloy with a low concentration of Ge (e.g. SiGe with Ge of 60%), and the fourth semiconductor material S4 may be GaAs And the fifth semiconductor material S5 may be InAs. In embodiments of the nMOS device in which the first semiconductor material S1 comprises SiGe (e.g., at least 90% Ge) or Ge having a high Ge concentration, the first semiconductor material S1 = the second semiconductor material S2), the third semiconductor material S3 may be a SiGe alloy with a low concentration of Ge (e.g. SiGe with Ge of 60%), and the fourth semiconductor material S4 may be GaAs And the fifth semiconductor material S5 may be InAs. The first semiconductor material S1 and the second semiconductor material S2 may be In-Ga-Sb alloys in the channel region, the third semiconductor material S3 may be In-Ga-Sb alloys, The material S4 may be a SiGe alloy and the fifth semiconductor material S5 may be a SiGe alloy or Ge with a high concentration of Ge.

In some embodiments according to the present invention, by forming a semiconductor alloy (consisting of a first semiconductor material S1 and a second semiconductor material S2) having a composition that changes smoothly between the channel region and the metal contact, A low resistance contact may be provided on the first semiconductor material S1 of the first semiconductor material S1. For example, a change in composition in the semiconductor material alloy causes the specific gravity of the first semiconductor material S1 and the second semiconductor material S2 to gradually change with the position in the source / drain region. For example, a change in the composition of the alloy may be provided such that the semiconductor material alloy is substantially the second semiconductor material S2 adjacent to the channel region. On the other hand, the semiconductor material alloy becomes substantially the third semiconductor material S3 at the metal contact remote from the channel region.

Furthermore, the semiconductor materials included in the semiconductor material alloy (consisting of the second semiconductor material S2 and the third semiconductor material S3) are each selected so as to have a specific relationship with respect to the first semiconductor material S1 in the channel region Can be selected. For example, the second semiconductor material S2 may have a band edge (e. G., A lower band edge offset) closer to the band edge of the second semiconductor material S2 than the band edge of the third semiconductor material S3 Lt; / RTI &gt; However, the third semiconductor material S3 may be selected to have a relatively large band edge offset relative to the first semiconductor material S1. The third semiconductor material S3 may be selected to have a low contact resistance with the metals (preferably less than 10 ^-8 ohm-cm ² , and in some embodiments, less than 10 ^-7 ohm-cm ² ) have. Furthermore, the semiconductor material alloy (consisting of the second semiconductor material S2 and the third semiconductor material S3) in the source / drain regions is formed so as to avoid abrupt changes in band edges in the source / ) Should be smooth.

Therefore, the first semiconductor material S1 and the third semiconductor material S3 can be either different (for example, the third semiconductor material S3) or the like (for example, I.e., the first semiconductor material S1). That is, the second semiconductor material S2 may be used as an intervening material, which is relatively close to the band edge of the first semiconductor material S1 but is present as an alloy with the third semiconductor material S3.

The contents of the foregoing description are not intended to be limiting, and the appended claims encompass all such modifications, improvements and other embodiments within the true spirit and scope of the inventive concept. Accordingly, to the fullest extent permitted by law, such ranges shall be determined by the claims that follow and the broadest interpretation of their equivalents, and should not be limited by the foregoing detailed description.

Claims (19)

In the semiconductor device,
A channel region comprising a first semiconductor material for a plurality of carriers during operation of the semiconductor device;
Metal contact;
A source / drain region comprising a semiconductor material alloy comprising a second semiconductor material; And
And at least one heterojunction disposed in the source / drain region between the metal contact and the channel region,
Wherein said heterojunction forms a band-edge offset of 0.2 eV or less of said majority carrier. The method according to claim 1,
Wherein the semiconductor material alloy has a spatially varying composition of the second semiconductor material and the third semiconductor material and the third semiconductor material is not fully miscible with the first semiconductor material. The method of claim 2,
Wherein a region of the heterojunction is doped with a dopant type associated with the conductivity of the majority carriers. The method of claim 2,
Wherein the spatial compositional change of the semiconductor material alloy is:
Wherein the second semiconductor material at the interface with the first semiconductor material of the channel region has a greater concentration than the third semiconductor material and the second semiconductor material at the interface with the metal contact is less than the third semiconductor material The concentration of the second semiconductor material is decreased and the concentration of the third semiconductor material is increased toward the interface with the metal contact at the interface with the channel region. The method of claim 4,
Spatial composition change of semiconductor material alloy is denoted by S2 _x S3 _{-x 1,} S2 is a second semiconductor material, S3 is the third semiconductor material is, x = 0 at the interface with the metal contact, Wherein x = 1 at the interface with the first semiconductor material in the channel region. The method of claim 5,
Wherein an increment in the spatial compositional change of the semiconductor material alloy is configured to prevent a band-edge offset between immediately adjacent portions of the spatially varying composition from becoming greater than 0.2 eV. The method according to claim 1,
Wherein the metal contact, the semiconductor materials, and the respective materials constituting the semiconductor material alloy at the interface with the metal contact are selected so that the Schottky barrier height therebetween is 0.2 eV or less. The method of claim 4,
Wherein the spatial compositional change of the semiconductor material alloy is linear, nonlinear, stepped, or a combination thereof. The method according to claim 1,
Wherein the first semiconductor material comprises at least one Group IV element and the second semiconductor material comprises a III-V semiconductor compound or a III-V semiconductor alloy, And a second semiconductor material. The method of claim 4,
The apparatus includes an NMOS device,
The first semiconductor material may be Si, a SiGe alloy, or Ge, and the second semiconductor material may be a GaAs, In-Ga-N, In-Ga-As-N alloy, Ga-As alloy, and the third semiconductor material is InAs, InN, In-As-N alloy, In-Al-As alloy or In-Ga-As alloy. The method according to claim 1,
Wherein the semiconductor material alloy has a spatially varying composition of the first semiconductor material and the second semiconductor material,
Wherein the change in the spatial composition of the semiconductor material alloy is such that at the interface with the first semiconductor material of the channel region the first semiconductor material has a greater concentration than the second semiconductor material and the third semiconductor material and the at least one hetero Wherein the second semiconductor material at the interface forming the junction has a greater concentration than the first semiconductor material and at an interface between the channel region and the first semiconductor material forming the at least one heterojunction, 1 concentration of the semiconductor material decreases and the concentration of the second semiconductor material increases,
Wherein the third semiconductor material is not fully miscible with the first semiconductor material. The method of claim 2,
Wherein the semiconductor material alloy has a first spatially varying composition of the second semiconductor material and the third semiconductor material,
The apparatus further comprising: an alloy of a second composition spatially varying, the alloy being located in the source / drain region between the channel region and the alloy of the first composition,
Wherein the alloy of the second composition has a spatially varying composition of a fourth semiconductor material and a fifth semiconductor material, wherein the fifth semiconductor material is not fully miscible with the first semiconductor material. In an electronic device,
A channel region comprising a first semiconductor material for a plurality of carriers during operation of the electronic device;
Metal contact; And
A source / drain region comprising a material alloy having at least one material component,
Wherein the source / drain region is free of all components of the first semiconductor material, and wherein a change in the spatial composition of the material alloy between the interface with the metal contact and the channel region is in the spatially varying composition Edge offset between the increment of the band-edge offset is not abruptly changed. 14. The method of claim 13,
Wherein at the interface with the first semiconductor material, the first semiconductor material and the material alloy form a heterojunction wherein the band-edge offset for the majority carriers is 0.2 eV or less. 15. The method of claim 14,
Wherein the band-edge offset for the majority carriers is 0.1 eV or less. 16. The method of claim 15,
Wherein the material alloy is doped in a range between 1E18 / cm3 and 1E20 / cm3. 18. The method of claim 16,
Wherein a band-edge offset between increments of the spatial compositional change of the material alloy is in a range between 0.1 eV at 6 nm and 0.1 eV at 0.6 nm. In an electronic device,
Metal contact;
A layer comprising a first material (S1) and a second material (S2) and having a spatially varying composition, denoted S2 _x S3 _{1 -x} ; And
and a third material (S3) in contact with said layer at x = 1,
The composition of the layer is completely S2 adjacent to the metal contact with x = 0 and completely away from the metal contact with x = 1, and the composition between x = 0 and x = Has a band edge offset of 0.2 eV or less with respect to the selected carrier,
The third material S3 is selected so that the band-edge offset of the heterojunction with the first material S1 is 0.2 eV or less, and the second material S2 has a Schottky barrier height 0.2 eV or less. 19. The method of claim 18,
Wherein the first material (S1), the second material (S2) and the third material (S3) are semiconductor materials.

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