JP2015156407A - Semiconductor device, transistor, method of manufacturing semiconductor device, and method of manufacturing transistor - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 33
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 239000000463 material Substances 0.000 claims abstract description 100
- 239000000203 mixture Substances 0.000 claims abstract description 47
- 230000004888 barrier function Effects 0.000 claims abstract description 21
- 229910005542 GaSb Inorganic materials 0.000 claims description 38
- 229910000673 Indium arsenide Inorganic materials 0.000 claims description 33
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims description 33
- 229910017115 AlSb Inorganic materials 0.000 claims description 22
- 239000000969 carrier Substances 0.000 claims description 4
- 108091006146 Channels Proteins 0.000 description 32
- 238000010586 diagram Methods 0.000 description 20
- 238000000034 method Methods 0.000 description 20
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 15
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 15
- 239000000758 substrate Substances 0.000 description 14
- 150000001875 compounds Chemical class 0.000 description 9
- 239000010410 layer Substances 0.000 description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 6
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- ZSBXGIUJOOQZMP-JLNYLFASSA-N Matrine Chemical compound C1CC[C@H]2CN3C(=O)CCC[C@@H]3[C@@H]3[C@H]2N1CCC3 ZSBXGIUJOOQZMP-JLNYLFASSA-N 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000002109 crystal growth method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 235000015067 sauces Nutrition 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
Description
本発明は、半導体装置、トランジスタ、半導体装置の製造方法、及び、トランジスタの製造方法に関する。 The present invention relates to a semiconductor device, a transistor, a method for manufacturing a semiconductor device, and a method for manufacturing a transistor.
高いオン電流と、急峻なスイッチング特性を得るために、ソース−チャネル間にIII−Ｖ族化合物を用いたヘテロ接合ＴＦＥＴ（TUNNELING FIELD EFFECT TRANSISTOR）が有望と考えられている。ソースとチャネル間の価電子帯端と伝導帯端のエネルギー差が重要なパラメータであり、最適値に設計することが望まれる。 In order to obtain a high on-current and steep switching characteristics, a heterojunction TFET (TUNNELING FIELD EFFECT TRANSISTOR) using a III-V group compound between the source and the channel is considered promising. The energy difference between the valence band edge and the conduction band edge between the source and the channel is an important parameter, and it is desired to design to an optimum value.
例えば、ＩｎＡｓ／ＡｌｘＧａ１−ｘＳｂヘテロ接合ＴＦＥＴにおいて、Ｓ値に対してｘ＝０．６が最適であることが非特許文献４にシミュレーションで示されている。しかし、ＩｎＡｓとＡｌｘＧａ１−ｘＳｂの格子定数が異なるため、ヘテロ接合界面にミスフィット転位等の欠陥が形成される。このためトラップアシスト電流が支配的となり、実際のデバイスではＳ値が悪いという問題がある。
For example,
これに対し、非特許文献５にＧａＡｓ０．５Ｓｂ０．５／Ｉｎ０．５３Ｇａ０．４７ＡｓやＧａＡｓ０．３５Ｓｂ０．６５／Ｉｎ０．７Ｇａ０．３Ａｓヘテロ接合が、格子整合する接合として示されている。この場合には、ミスフィット転位は形成されないが、重要なパラメータであるソースとチャネル間の価電子帯端と伝導帯端のエネルギー差ΔＥｃ−ｖは、それぞれ０．５ｅＶ、０．２５ｅＶに固定された値である。非特許文献４によると、Ｓ値及びオン電流に対して最適のΔＥｃ−ｖが、それぞれ０．０９４ｅＶ、０．０７４ｅＶであることが示されている。この値を外れると、Ｓ値の増大やオン電流の低下となる。この最適値に比べ、非特許文献５での０．５ｅＶ、０．２５ｅＶというΔＥｃ−ｖの値は大きく、Ｓ値やオン電流の特性が悪いという不都合がある。
On the other hand, Non-Patent
また、上記値を変化させるためには、（Ａｓ，Ｓｂ）の組成の組と（Ｉｎ，Ｇａ）の組成の組を調整する必要があるが、格子定数も変わってしまう。ＧａＡｓ０．５Ｓｂ０．５／Ｉｎ０．５３Ｇａ０．４７Ａｓヘテロ接合は、ＩｎＰと格子整合するためＩｎＰ基板上に形成可能であるが、これ以外の組成の組合せ、例えばＧａＡｓ０．３５Ｓｂ０．６５／Ｉｎ０．７Ｇａ０．３Ａｓヘテロ接合は、ＩｎＰと格子定数が異なるため、ＩｎＰ基板上に形成するためには、格子緩和バッファ層（非特許文献５ではＡｌ１−ｘＩｎｘＡｓを使用）の形成が必要である。格子緩和バッファ層を用いた格子定数の制御性は、２元化合物基板より当然低いため、格子定数の設計値とのずれによる格子歪みが導入され易い。歪みの導入により半導体のバンド構造が変化するため、ソースとチャネル間の価電子帯端と伝導帯端のエネルギー差も変化する。つまり、ＧａＡｓｘ１Ｓｂ１−ｘ１／Ｉｎｘ２Ｇａ１−ｘ２Ａｓのヘテロ接合において、ソースとチャネル間の価電子帯端と伝導帯端のエネルギー差の連続的制御には、ヘテロ接合を形成する２種類の半導体の組成制御以外に、格子緩和バッファ層の格子定数制御が必要であり、制御が難しい。また、格子緩和バッファ層を形成することによる、コスト増大の問題もある。 Further, in order to change the above value, it is necessary to adjust the composition set of (As, Sb) and the composition set of (In, Ga), but the lattice constant also changes. A GaAs 0.5 Sb 0.5 / In 0.53 Ga 0.47 As heterojunction can be formed on an InP substrate because of lattice matching with InP, but other combinations of compositions such as GaAs 0.35 The Sb 0.65 / In 0.7 Ga 0.3 As heterojunction has a lattice constant different from that of InP. Therefore, in order to form it on an InP substrate, a lattice relaxation buffer layer (Al 1-x in Non-Patent Document 5). In x As) is required. Since the controllability of the lattice constant using the lattice relaxation buffer layer is naturally lower than that of the binary compound substrate, lattice distortion due to deviation from the design value of the lattice constant is likely to be introduced. Since the band structure of the semiconductor changes due to the introduction of strain, the energy difference between the valence band edge and the conduction band edge between the source and the channel also changes. In other words, in the heterojunction of GaAs x1 Sb 1-x1 / In x2 Ga 1-x2 As, for the continuous control of the energy difference between the valence band edge and the conduction band edge between the source and the channel, the heterojunction is formed 2 In addition to controlling the composition of various types of semiconductors, it is necessary to control the lattice constant of the lattice relaxation buffer layer, which makes control difficult. There is also a problem of an increase in cost due to the formation of the lattice relaxation buffer layer.
本発明によれば、格子整合した第１の材料及び第２の材料により形成されたヘテロ接合からなり、キャリアが前記第１の材料の伝導帯と、前記第２の材料の価電子帯の間でトンネルするトンネル障壁を含み、前記第１の材料の伝導帯端Ｅｃと、前記第２の材料の価電子帯端Ｅｖのエネルギー差ΔＥｃ−ｖは、０．２ｅＶ以下であるトランジスタを有する半導体装置が提供される。 According to the present invention, the heterojunction is formed of a lattice-matched first material and a second material, and carriers are between the conduction band of the first material and the valence band of the second material. A semiconductor device including a transistor that includes a tunnel barrier that tunnels at a point where an energy difference ΔEc-v between a conduction band edge Ec of the first material and a valence band edge Ev of the second material is 0.2 eV or less Is provided.
また、本発明によれば、格子整合した第１の材料及び第２の材料により形成されたヘテロ接合からなり、キャリアが前記第１の材料の伝導帯と、前記第２の材料の価電子帯の間でトンネルするトンネル障壁を含み、前記第１の材料の伝導帯端Ｅｃと、前記第２の材料の価電子帯端Ｅｖのエネルギー差ΔＥｃ−ｖは、０．２ｅＶ以下であるトランジスタが提供される。 In addition, according to the present invention, the carrier includes a heterojunction formed of a lattice-matched first material and a second material, and carriers are the conduction band of the first material and the valence band of the second material. Provided is a transistor that includes a tunnel barrier that tunnels between them, and an energy difference ΔEc−v between a conduction band edge Ec of the first material and a valence band edge Ev of the second material is 0.2 eV or less Is done.
また、本発明によれば、格子整合した材料により形成されたヘテロ接合からなるトンネル障壁を含むトランジスタを設計する工程を有し、
前記工程では、格子定数が一致する第１の材料と第２の材料の少なくとも一方の材料の組成を調整することにより、格子定数を一定に保ったまま、前記第１の材料の伝導帯端と前記第２の材料の価電子帯端のエネルギー差を連続的に変化させ、前記第１の材料の伝導帯端と前記第２の材料の価電子帯端のエネルギー差が所定の値となるヘテロ接合からなるトンネル障壁を含むトランジスタを設計する半導体装置の製造方法が提供される。
Further, according to the present invention, the method includes designing a transistor including a tunnel barrier formed of a heterojunction formed of a lattice-matched material.
In the step, by adjusting the composition of at least one of the first material and the second material having the same lattice constant, the conduction band edge of the first material is maintained while keeping the lattice constant constant. The energy difference between the valence band edges of the second material is continuously changed so that the energy difference between the conduction band edge of the first material and the valence band edge of the second material becomes a predetermined value. A method of manufacturing a semiconductor device for designing a transistor including a tunnel barrier formed of a junction is provided.
また、本発明によれば、格子整合した材料により形成されたヘテロ接合からなるトンネル障壁を含むトランジスタを設計する工程を有し、
前記工程では、格子定数が一致する第１の材料と第２の材料の少なくとも一方の材料の組成を調整することにより、格子定数を一定に保ったまま、前記第１の材料の伝導帯端と前記第２の材料の価電子帯端のエネルギー差を連続的に変化させ、前記第１の材料の伝導帯端と前記第２の材料の価電子帯端のエネルギー差が所定の値となるヘテロ接合からなるトンネル障壁を含むトランジスタを設計するトランジスタの製造方法が提供される。
Further, according to the present invention, the method includes designing a transistor including a tunnel barrier formed of a heterojunction formed of a lattice-matched material.
In the step, by adjusting the composition of at least one of the first material and the second material having the same lattice constant, the conduction band edge of the first material is maintained while keeping the lattice constant constant. The energy difference between the valence band edges of the second material is continuously changed so that the energy difference between the conduction band edge of the first material and the valence band edge of the second material becomes a predetermined value. A method of manufacturing a transistor is provided for designing a transistor including a tunnel barrier comprising a junction.
本発明によれば、急峻なスイッチング特性を有するヘテロ接合ＴＦＥＴが得られる。 According to the present invention, a heterojunction TFET having steep switching characteristics can be obtained.
以下、本発明のトランジスタおよび当該トランジスタを有する半導体装置の実施形態について図面を用いて説明する。なお、図はあくまで発明の構成を説明するための概略図であり、各部材の大きさ、形状、数、異なる部材の大きさの比率などは図示するものに限定されない。 Hereinafter, embodiments of a transistor of the present invention and a semiconductor device having the transistor will be described with reference to the drawings. The drawings are only schematic diagrams for explaining the configuration of the invention, and the size, shape, number, and ratio of different member sizes are not limited to those shown in the drawings.
図１に、本実施形態の半導体装置が有する縦型ヘテロ接合ＴＦＥＴの断面模式図を示す。図１は、Ｎ型チャネルを示している。図示するように、ソースは高濃度Ｐ＋ＧａＳb領域、チャネルはＧａｘＩｎ１−ｘＡｓｙＳｂ１−ｙで形成されている。ＧａｘＩｎ１−ｘＡｓｙＳｂ１−ｙ（チャネル）は、組成ｙを調整することで、任意の組成ｘに対してＧａＳbと格子整合させることができる。そして、本実施形態においては、ＧａｘＩｎ１−ｘＡｓｙＳｂ１−ｙ（チャネル）は、ＧａＳｂ（ソース）と格子整合するよう組成ｘ及び組成ｙが調整されている。すなわち、ＧａｘＩｎ１−ｘＡｓｙＳｂ１−ｙ（チャネル）と、ＧａＳｂ（ソース）との間には、ミスフィット転位が発生しない。 FIG. 1 is a schematic cross-sectional view of a vertical heterojunction TFET included in the semiconductor device of this embodiment. FIG. 1 shows an N-type channel. As shown in the drawing, the source is formed of a high concentration P + GaSb region, and the channel is formed of Ga x In 1-x As y Sb 1 -y . Ga x In 1-x As y Sb 1-y (channel) can be lattice-matched with GaSb for an arbitrary composition x by adjusting the composition y. In this embodiment, the composition x and the composition y of the Ga x In 1-x As y Sb 1-y (channel) are adjusted so as to lattice match with the GaSb (source). That is, the Ga x In 1-x As y Sb 1-y ( channel) between the GaSb (source), misfit dislocations are not generated.
格子整合しているとは、積層された２つの結晶層において、その界面を形成するそれぞれの結晶層の面で、格子定数が等しくなっている状態をいう。歪が緩和しない臨界膜厚以下の場合、格子が歪むことで下位面での格子定数に一致するが、当該状態は、本実施形態でいうソースとチャネルが格子整合した状態に含まない。例えば、本実施形態のチャネルの膜厚は１０ｎｍ以上３００ｎｍ以下、ドレインの膜厚は５０ｎｍ以上３００ｎｍ以下であるが、無歪であるので、臨界膜厚の制約はなく、必要に応じて任意の膜厚にすることが出来る。 Lattice matching refers to a state in which the lattice constants are equal in the planes of the crystal layers forming the interface in the two stacked crystal layers. When the thickness is equal to or less than the critical film thickness at which strain is not relaxed, the lattice is distorted to match the lattice constant on the lower surface. For example, the channel thickness of this embodiment is 10 nm or more and 300 nm or less, and the drain thickness is 50 nm or more and 300 nm or less. However, since there is no distortion, there is no restriction on the critical thickness, and any film can be used as necessary. Can be thick.
また、本実施形態では、ＧａｘＩｎ１−ｘＡｓｙＳｂ１−ｙ（チャネル）と、ＧａＳｂ（ソース）とは、タイプII型のバンドアライメントとなっており、ＴＦＥＴ動作に重要なＧａｘＩｎ１−ｘＡｓｙＳｂ１−ｙの伝導帯端ＥｃとＧａＳｂの価電子帯端Ｅｖのエネルギー差ΔＥｃ−ｖは、組成ｘ、ｙで調整できる。本実施形態では、ΔＥｃ−ｖが０．２ｅＶ以下、好ましくは０．１５ｅＶ以下、さらに好ましくは０．１ｅＶ以下となるように調整する。また、ΔＥｃ−ｖが０ｅＶより大きく、好ましくはΔＥｃ−ｖのばらつきの標準偏差をσとすると３σ以上、さらに好ましくは６σ以上となるように調整する。タイプII型ヘテロ接合とは、接合を形成する２つの半導体のバンドアライメントにおいて、一方の半導体のＥｃとＥｖのエネルギー位置が、もう一方の半導体のＥｃとＥｖから、それぞれ同じ方向にずれ、かつ２つの半導体のバンドギャップに重なりがある状態の接合のことである。 Further, in this embodiment, Ga x an In and 1-x As y Sb 1- y ( channel), and the GaSb (source), and a type II band alignment, important Ga x an In the TFET operation 1-x As y Sb The energy difference ΔEc-v between the conduction band edge Ec of 1-y and the valence band edge Ev of GaSb can be adjusted by the composition x, y. In the present embodiment, ΔEc−v is adjusted to be 0.2 eV or less, preferably 0.15 eV or less, and more preferably 0.1 eV or less. Further, ΔEc-v is adjusted to be larger than 0 eV, preferably 3σ or more, more preferably 6σ or more, where σ is a standard deviation of variation of ΔEc-v. In type II heterojunction, in the band alignment of two semiconductors forming a junction, the energy positions of Ec and Ev of one semiconductor are shifted in the same direction from Ec and Ev of the other semiconductor, respectively, and 2 It is a junction where there is an overlap in the band gap of two semiconductors.
本実施形態の構造では、欠陥を発生させず、ΔＥｃ−ｖを所望の値にすることができ、急峻なスイッチング特性を有するヘテロ接合ＴＦＥＴが実現される。 In the structure of the present embodiment, a heterojunction TFET having a steep switching characteristic can be realized without causing a defect and making ΔEc-v a desired value.
なお、ヘテロ接合は、上記例の他、ＧａｘＩｎ１−ｘＡｓｙＳｂ１−ｙ、ＡｌｘＧａ１−ｘＡｓｙＳｂ１−ｙ、ＩｎＰｘＡｓｙＳｂ１−ｘ−ｙの中の何れか２種類の材料で構成することができる。ヘテロ接合を構成する２種類の材料のｘの値は異なっていてもよいし、同じであってもよい。また、ヘテロ接合を構成する２種類の材料のｙの値は異なっていてもよいし、同じであってもよい。例えば、ＧａＳｂとＧａｘＩｎ１−ｘＡｓｙＳｂ１−ｙの組み合わせ、ＩｎＡｓとＧａｘＩｎ１−ｘＡｓｙＳｂ１−ｙの組み合わせ、ＡｌＳｂとＧａｘＩｎ１−ｘＡｓｙＳｂ１−ｙの組み合わせ、ＧａＳｂとＡｌｘＧａ１−ｘＡｓｙＳｂ１−ｙの組み合わせ、ＩｎＡｓとＡｌｘＧａ１−ｘＡｓｙＳｂ１−ｙの組み合わせ、ＡｌＳｂとＡｌｘＧａ１−ｘＡｓｙＳｂ１−ｙの組み合わせ、ＧａＳｂとＩｎＰｘＡｓｙＳｂ１−ｘ−ｙの組み合わせ、ＩｎＡｓとＩｎＰｘＡｓｙＳｂ１−ｘ−ｙの組み合わせ、または、ＡｌＳｂとＩｎＰｘＡｓｙＳｂ１−ｘ−ｙの組み合わせであってもよい。また、ＧａＳｂと格子整合する３元化合物として、ＩｎＡｓ０．９１Ｓｂ０．０９、ＡｌＡｓ０．０８Ｓｂ０．９２、ＩｎＰ０．６３Ｓｂ０．３７があり、ＩｎＡｓと格子整合する３元化合物として、ＧａＡｓ０．０８Ｓｂ０．９２、ＡｌＡｓ０．１６Ｓｂ０．８４、ＩｎＰ０．６９Ｓｂ０．３１があり、ＡｌＳｂと格子整合する３元化合物として、ＩｎＡｓ０．８２Ｓｂ０．１８、Ｇａ０．９Ｉｎ０．１Ｓｂ、ＩｎＰ０．５６Ｓｂ０．４４があり、これらと、ＧａｘＩｎ１−ｘＡｓｙＳｂ１−ｙ、ＡｌｘＧａ１−ｘＡｓｙＳｂ１−ｙ、ＩｎＰｘＡｓｙＳｂ１−ｘ−ｙとの組み合わせであってもよい。なお、これらの組み合わせに限定されない。但し、課題の欄で説明した様に、格子定数を基板に用いる材料の値にした方が、格子緩和バッファが不要なことから、格子定数の制御性が高く、歪導入によるバンドアライメント変調の影響が抑制され、ΔＥｃ−ｖを高精度に制御できるという利点がある。 Incidentally, heterojunction, in addition to the above example, Ga x In 1-x As y Sb 1-y, Al x Ga 1-x As y Sb 1-y, in the InP x As y Sb 1-x -y Any two kinds of materials can be used. The values of x of the two types of materials constituting the heterojunction may be different or the same. Also, the y values of the two types of materials constituting the heterojunction may be different or the same. For example, GaSb and Ga x In 1-x As y combination of Sb 1-y, a combination of InAs and Ga x In 1-x As y Sb 1-y, AlSb and Ga x In 1-x As y Sb 1-y combination, GaSb and Al x Ga 1-x as y Sb combination of 1-y, a combination of InAs and Al x Ga 1-x as y Sb 1-y, AlSb and Al x Ga 1-x as y Sb 1- y combination, GaSb and InP x As y Sb 1-xy combination, InAs and InP x As y Sb 1-xy combination, or AlSb and InP x As y Sb 1-xy combination It may be. As ternary compounds lattice-matched with GaSb, there are InAs 0.91 Sb 0.09 , AlAs 0.08 Sb 0.92 , and InP 0.63 Sb 0.37 , and ternary compounds lattice-matched with InAs , GaAs 0.08 Sb 0.92 , AlAs 0.16 Sb 0.84 , InP 0.69 Sb 0.31 , and InAs 0.82 Sb 0.18 , Ga as ternary compounds lattice-matched with AlSb. 0.9 In 0.1 Sb, InP 0.56 Sb 0.44 , Ga x In 1-x As y Sb 1-y , Al x Ga 1-x As y Sb 1-y , InP A combination with x As y Sb 1-xy may be used. In addition, it is not limited to these combinations. However, as explained in the section of the problem, the lattice constant is set to the value of the material used for the substrate, and the lattice relaxation buffer is unnecessary, so the control of the lattice constant is higher, and the influence of band alignment modulation due to strain introduction. Is suppressed, and ΔEc-v can be controlled with high accuracy.
次に、本実施形態の半導体装置の製造方法、及び、トランジスタの製造方法について説明する。いずれの製造方法も、格子整合した材料により形成されたヘテロ接合からなるトンネル障壁を含むトランジスタを設計する工程を有する。 Next, a method for manufacturing a semiconductor device and a method for manufacturing a transistor according to the present embodiment will be described. Each manufacturing method includes a step of designing a transistor including a tunnel barrier made of a heterojunction formed of a lattice-matched material.
当該工程では、格子定数が一致する第１の材料と第２の材料の少なくとも一方の材料の組成を調整することにより、格子定数を一定に保ったまま、第１の材料の伝導帯端と第２の材料の価電子帯端のエネルギー差を連続的に変化させ、第１の材料の伝導帯端と第２の材料の価電子帯端のエネルギー差が所定の値となるヘテロ接合からなるトンネル障壁を含むトランジスタを設計する。以下、詳細に説明する。 In this step, by adjusting the composition of at least one of the first material and the second material having the same lattice constant, the conduction band edge of the first material and the second material are maintained while keeping the lattice constant constant. A tunnel composed of a heterojunction in which the energy difference between the conduction band edge of the first material and the energy band edge of the second material becomes a predetermined value by continuously changing the energy difference between the valence band edges of the two materials. Design transistors with barriers. Details will be described below.
非特許文献１に記載されている通り、Vegard則により、任意の（ｘ、ｙ）の組の４元化合物の格子定数を求めることができ（非特許文献１に記載の式（１）参照）、格子整合させる材料の格子定数を与えれば、ｘとｙの関係式を求めることができる。
As described in
図２乃至９に、ＧａＳｂ、ＩｎＡｓ及びＡｌＳｂ各々と格子整合するＧａｘＩｎ１−ｘＡｓｙＳｂ１−ｙ、ＡｌｘＧａ１−ｘＡｓｙＳｂ１−ｙ、又は、ＩｎＰｘＡｓｙＳｂ１−ｘ−ｙのｘ、ｙ組成の関係を示す。当該ｘ、ｙ組成の関係は、Vegard則により求めた。本実施形態では、このような関係に基づき、ｘ及びｙの値を調整することで、特にＧａＳｂ基板、ＩｎＡｓ基板及びＡｌＳｂ基板と、格子整合した材料により形成されたヘテロ接合を実現する。 2 to 9, Ga x In 1-x As y Sb 1-y , Al x Ga 1-x As y Sb 1-y , or InP x As y Sb 1 lattice-matched with GaSb, InAs, and AlSb, respectively. -x-y of x, illustrating the relationship between y composition. The relationship between the x and y compositions was determined according to the Vegard law. In the present embodiment, by adjusting the values of x and y based on such a relationship, in particular, a heterojunction formed of a lattice-matched material with a GaSb substrate, an InAs substrate, and an AlSb substrate is realized.
ここで、ｘ及びｙの値の調整について一例を説明する。 Here, an example of adjusting the values of x and y will be described.
まず、図１０を用いて、ヘテロ接合ＴＦＥＴでのバンド設計について説明する。図１０（ａ）、（ｂ）はＮ型チャネル、図１０（ｃ）、（ｄ）はＰ型チャネルを示す。また、図１０（ａ）、（ｃ）は、ソース、チャネル、ドレインを接続しない材料そのもののＥｃ、Ｅｖ（従って、Ｅｃは電子親和力Ｘ、ＥｖはＸ＋バンドギャップＥｇとなる）、図１０（ｂ）、（ｄ）は、それらを接続したデバイス構造でのＥｃ、Ｅｖのエネルギー位置を示す。ここで、Ｅｆはフェルミエネルギーを示す。図１０（ｂ）、（ｄ）は、ドレイン−ソース間に電圧Ｖｄｓを印加し、ゲート電圧にオン電圧を印加した状態とオフ電圧を印加した状態をそれぞれ示す。 First, band design in a heterojunction TFET will be described with reference to FIG. FIGS. 10A and 10B show an N-type channel, and FIGS. 10C and 10D show a P-type channel. 10A and 10C show Ec and Ev of the material itself that does not connect the source, channel, and drain (therefore, Ec is electron affinity X and Ev is X + band gap Eg), and FIG. ) And (d) show the energy positions of Ec and Ev in the device structure to which they are connected. Here, E f represents Fermi energy. FIGS. 10B and 10D show a state in which a voltage Vds is applied between the drain and source, an on-voltage is applied to the gate voltage, and an off-voltage is applied.
ここで重要な特性値が、ソースとチャネルの伝導帯端エネルギーＥｃと価電子帯端エネルギーＥｖの差ΔＥｃ−ｖである。ΔＥｃ−ｖは、Ｎ型チャネルの場合はソースのＥｖとチャネルのＥｃの差となり、Ｐ型チャネルの場合はチャネルのＥｖとソースのＥｃの差となる。ここでΔＥｃ−ｖの値は、Ｎ型チャネル、Ｐ型チャネルとも、図１０の状態のタイプII型の時に正とする。 An important characteristic value here is the difference ΔEc−v between the conduction band edge energy Ec and the valence band edge energy Ev of the source and channel. ΔEc−v is the difference between the source Ev and the channel Ec for the N-type channel, and the difference between the channel Ev and the source Ec for the P-type channel. Here, the value of ΔEc−v is positive when the N-type channel and the P-type channel are in the type II state shown in FIG.
ゲート電圧にしきい値電圧を越える電圧を印加したオン状態（実線）では、図１０の矢印で示したトンネルが発生し、そのトンネル電流を、ゲート電圧で制御する。一方、ゲート電圧にしきい値電圧を下回る電圧を印加したオフ状態（点線）では、このようなトンネルは発生しない。白抜きの丸印は正孔を、黒塗りの丸印は電子を示し、Ｎ型チャネルの場合は、ソースの価電子帯の電子が、チャネルの伝導帯にトンネルする（ソースの価電子帯には正孔が形成される）ことを表している。 In the ON state (solid line) in which a voltage exceeding the threshold voltage is applied to the gate voltage, a tunnel indicated by an arrow in FIG. 10 is generated, and the tunnel current is controlled by the gate voltage. On the other hand, such a tunnel does not occur in the off state (dotted line) in which a voltage lower than the threshold voltage is applied to the gate voltage. Open circles indicate holes, and black circles indicate electrons. In the case of an N-type channel, electrons in the valence band of the source tunnel to the conduction band of the channel (into the valence band of the source). Indicates that holes are formed.
図１１にＮ型チャネルのＩｄ−Ｖｇ特性を示すが、ΔＥｃ−ｖが０．０８ｅＶの方が０．１６ｅＶよりも、ドレイン電流Ｉｄが大きくなっている。これは、ΔＥｃ−ｖが大きいほどしきい値電圧Ｖｔが大きく、しきい値印加時点で、チャネルと接するソースのバンドの曲がりが大きくなるため、ソース−ドレイン間電圧Ｖｄｓの内チャネルに配分される電位差が小さくなっており、Ｖｇ＞Ｖｔでのゲート電圧に対するチャネル電位の変化が小さくなるためと考えられる。つまり、しきい値印加時点では、トンネル距離は同じであるが、Ｖｇ＞ＶｔではＶｇ−Ｖｔが同じでも、ΔＥｃ−ｖが小さい方がチャネル電位の変化が大きく、トンネル距離が小さいため、ドレイン電流が高くなる。ΔＥｃ−ｖは小さい方が、ドレイン電流が大きくなるが、ΔＥｃ−ｖが負になると、タイプIII型ヘテロ接合となり、障壁がなくなり、トンネル接合ではなくなるので、ΔＥｃ−ｖのばらつきも考慮して、ばらついてもΔＥｃ−ｖが正となるように、最適なΔＥｃ−ｖを設計する必要がある。従って、ΔＥｃ−ｖは任意の所望の値に設計出来ることが望まれる。本実施形態では、ΔＥｃ−ｖが０．２ｅＶ以下、好ましくは０．１５ｅＶ以下、さらに好ましくは０．１ｅＶ以下となるように設計する。また、ΔＥｃ−ｖが０ｅＶより大きく、好ましくはΔＥｃ−ｖのばらつきの標準偏差をσとすると３σ以上、さらに好ましくは６σ以上となるように設計する。 FIG. 11 shows the Id-Vg characteristics of the N-type channel. When ΔEc-v is 0.08 eV, the drain current Id is larger than 0.16 eV. This is because the threshold voltage Vt increases as ΔEc-v increases, and the bending of the source band in contact with the channel increases when the threshold is applied, so that the source-drain voltage Vds is distributed to the inner channel. This is probably because the potential difference is small and the change in channel potential with respect to the gate voltage when Vg> Vt is small. That is, when the threshold is applied, the tunnel distance is the same, but when Vg> Vt, even if Vg−Vt is the same, the smaller the ΔEc−v, the larger the channel potential change and the smaller the tunnel distance. Becomes higher. When ΔEc-v is smaller, the drain current becomes larger. However, if ΔEc-v becomes negative, it becomes a type III heterojunction, there is no barrier, and it is no longer a tunnel junction. It is necessary to design an optimal ΔEc-v so that ΔEc-v is positive even if it varies. Therefore, it is desirable that ΔEc−v can be designed to an arbitrary desired value. In this embodiment, it is designed such that ΔEc−v is 0.2 eV or less, preferably 0.15 eV or less, more preferably 0.1 eV or less. Further, ΔEc-v is designed to be larger than 0 eV, preferably 3σ or more, more preferably 6σ or more, where σ is a standard deviation of variation of ΔEc-v.
図１２乃至１９に、ＧａＳｂ、ＩｎＡｓ及びＡｌＳｂと格子整合するＧａｘＩｎ１−ｘＡｓｙＳｂ１−ｙ、ＡｌｘＧａ１−ｘＡｓｙＳｂ１−ｙ、及び、ＩｎＰｘＡｓｙＳｂ１−ｘ−ｙにおける、ｘ組成とＥｃ（電子親和力Ｘ）、Ｅｖ（Ｅｇ＋Ｘ）の関係をそれぞれ示す。ここで、Ｅｃ、Ｅｖは真空準位からのエネルギーの値として示し、図面上ＥｃがＥｖの上に来る軸の向きで示してある。これらの材料のＥｃ、Ｅｖの図の左右にある図は、ＧａＳｂまたはＩｎＡｓまたはＡｌＳｂと格子整合する２元および３元化合物の一例のＥｃ、Ｅｖを示す図である。図１２及び図１３に示したＧａｘＩｎ１−ｘＡｓｙＳｂ１−ｙは、文献値（非特許文献３参照）を表示しているが、図１４乃至図１９に示したＧａｘＩｎ１−ｘＡｓｙＳｂ１−ｙ、ＡｌｘＧａ１−ｘＡｓｙＳｂ１−ｙ、及び、ＩｎＰｘＡｓｙＳｂ１−ｘ−ｙは、図４乃至９で示した線の両端の材料（図中黒丸で示した、名称を記載した化合物）の、Ｅｃ、Ｅｖを内挿した線を示している。 12 to 19, GaSb, Ga x In 1 -x As y Sb 1-y that is lattice matched with InAs and AlSb, Al x Ga 1-x As y Sb 1-y, and, InP x As y Sb 1- The relationship between x composition, Ec (electron affinity X), and Ev (Eg + X) in xy is shown, respectively. Here, Ec and Ev are shown as values of energy from the vacuum level, and Ec in the drawing is shown in the direction of the axis on Ev. The diagrams on the left and right of the Ec and Ev diagrams of these materials are examples of Ec and Ev of binary and ternary compounds that lattice match with GaSb, InAs, or AlSb. Ga x In 1-x As y Sb 1-y shown in FIG. 12 and FIG. 13 displays literature values (see Non-Patent Document 3), but Ga x In 1 shown in FIG. 14 to FIG. -x As y Sb 1-y, Al x Ga 1-x As y Sb 1-y, and, InP x As y Sb 1- x-y , the material (FIG across the line indicated in FIG. 4 to 9 A line in which Ec and Ev are interpolated is shown for the compound indicated by the name indicated by a solid black circle).
まず、Ｎ型チャネルの場合を説明する。図１２に示す例の場合、ＧａＳｂとＧａｘＩｎ１−ｘＡｓｙＳｂ１−ｙ（０．１＜ｘ＜０．６）はタイプII型のヘテロ接合を形成し、Ｎ型チャネルのそれぞれソースとチャネルに使用出来る。高いドレイン電流を得るために、例えばΔＥｃ−ｖ＝０．１ｅＶとするには、ｘ＝０．２３が良いことになる。また、ＧａｘＩｎ１−ｘＡｓｙＳｂ１−ｙ（ｘ＞０．６）のＥｖはＧａＳｂのＥｖと同程度であるので、これをソースにすることもできる。一方、ＧａｘＩｎ１−ｘＡｓｙＳｂ１−ｙ（０＜ｘ＜０．４）とＩｎＡｓ０．９１Ｓｂ０．０９がタイプII型のヘテロ接合を形成し、それぞれソースとチャネルに使用できる。高いドレイン電流を得るために、例えばΔＥｃ−ｖ＝０．１ｅＶとするためには、ｘ＝０．２３が良いことになる。ｘ≧０．８を除き、少しだけ異なるｘ組成同士はタイプII型のヘテロ接合となるので、タイプII型を形成するだけなら、ソースとチャネルのｘ組成の組は無限に存在する。但し、高いドレイン電流を得るために、例えばΔＥｃ−ｖ＝０．１ｅＶとするためには、ＧａｘＩｎ１−ｘＡｓｙＳｂ１−ｙ（ｘ≧０．２３）をソースにすれば、ＧａｘＩｎ１−ｘＡｓｙＳｂ１−ｙをチャネルにできる組成ｘの範囲が存在する。このｘ＝０．２３は、Ｅｃの最大値（ｘ＝０でのＥｃ）＋０．１ｅＶに一致するＥｖを有する組成ｘとして求められる。この組成ｘの範囲は、当然、ΔＥｃ−ｖの設計値に依存する。 First, the case of an N-type channel will be described. In the example shown in FIG. 12, GaSb and Ga x In 1-x As y Sb 1-y (0.1 <x <0.6) forms a heterojunction type II, respectively the source of N-type channel And can be used for channels. In order to obtain a high drain current, for example, Δ = 0.23 is good for ΔEc−v = 0.1 eV. Further, Ev of Ga x In 1-x As y Sb 1-y (x> 0.6) is because it is comparable to the Ev of GaSb, it is also possible to do this source. On the other hand, Ga x In 1-x As y Sb 1-y (0 <x <0.4) and InAs 0.91 Sb 0.09 form a type II heterojunction and can be used for the source and channel, respectively. . In order to obtain a high drain current, for example, in order to set ΔEc−v = 0.1 eV, x = 0.23 is good. Except for x ≧ 0.8, slightly different x compositions form a type II heterojunction. Therefore, if only a type II type is formed, there are infinite combinations of source and channel x compositions. However, in order to obtain a high drain current, for example, ΔEc-v = 0.1 eV, Ga x In 1-x As y Sb 1-y (x ≧ 0.23) is used as a source, and Ga range of composition x as possible x in 1-x As y Sb 1-y on the channel exists. This x = 0.23 is calculated | required as a composition x which has Ev which corresponds to the maximum value (Ec in x = 0) + 0.1eV of Ec. The range of the composition x naturally depends on the design value of ΔEc−v.
一方、P型チャネルの場合には、ソースとチャネルの材料が、上述のＮ型チャネルの場合と逆になる。ＩｎＡｓまたはＡｌＳｂと格子整合するＧａｘＩｎ１−ｘＡｓｙＳｂ１−ｙの場合（図１３及び図１４参照）は、同様であるので、説明を省略する。 On the other hand, in the case of a P-type channel, the source and channel materials are reversed from those in the case of the N-type channel described above. In the case of Ga x In 1-x As y Sb 1-y lattice-matched with InAs or AlSb (see FIGS. 13 and 14), the description is omitted.
ＧａｘＩｎ１−ｘＡｓｙＳｂ１−ｙと異なり、ＡｌｘＧａ１−ｘＡｓｙＳｂ１−ｙとＩｎＰｘＡｓｙＳｂ１−ｘ−ｙは、ＥｃとＥｖのｘ組成に対する傾きが互いに逆になるので、少しだけｘ組成の異なるものの組合せはタイプI型のヘテロ接合となる。従って、ＧａＳｂと格子整合するＡｌｘＧａ１−ｘＡｓｙＳｂ１−ｙの場合（図１５参照）、タイプII型となる組合せは、一例としてＩｎＡｓ０．９１Ｓｂ０．０９とＡｌｘＧａ１−ｘＡｓｙＳｂ１−ｙ（０．２＜ｘ＜０．８９）がある。高いドレイン電流を得るために、例えばΔＥｃ−ｖ＝０．１ｅＶとするためには、ＡｌｘＧａ１−ｘＡｓｙＳｂ１−ｙ（ｘ＝０．４３）となる。このｘ組成の値は、当然、ΔＥｃ−ｖの設計値に依存するが、前述した通り、Ｅｃ、Ｅｖの図面は単純な内挿であり、実際とは異なっている可能性があるため、あくまでｘ組成の値は参考値である。Ｎ型チャネルの場合には、ＡｌｘＧａ１−ｘＡｓｙＳｂ１−ｙ（０．２＜ｘ＜０．８９）をソースとし、ＩｎＡｓ０．９１Ｓｂ０．０９をチャネルとする。Ｐ型チャネルの場合には、ソースとチャネルの材料が、Ｎ型チャネルの場合と逆になる。なお、ＩｎＡｓと格子整合するＡｌｘＧａ１−ｘＡｓｙＳｂ１−ｙの場合（図１６参照）は、同様であるので、説明を省略する。 Unlike Ga x In 1-x As y Sb 1-y, Al x Ga 1-x As y Sb 1-y and InP x As y Sb 1-x -y , the inclination with respect to x composition of Ec and Ev are mutually Since the opposite is true, a combination of materials having slightly different x compositions becomes a type I heterojunction. Therefore, in the case of Al x Ga 1-x As y Sb 1-y lattice-matched with GaSb (see FIG. 15), the type II type combination is, for example, InAs 0.91 Sb 0.09 and Al x Ga 1. there is -x As y Sb 1-y ( 0.2 <x <0.89). In order to obtain a high drain current, for example, ΔEc−v = 0.1 eV, Al x Ga 1−x As y Sb 1−y (x = 0.43). The value of this x composition naturally depends on the design value of ΔEc−v. However, as described above, the drawings of Ec and Ev are simple interpolations and may differ from actual ones. The value of x composition is a reference value. In the case of an N-type channel, Al x Ga 1-x As y Sb 1-y (0.2 <x <0.89) is used as a source, and InAs 0.91 Sb 0.09 is used as a channel. In the case of a P-type channel, the source and channel materials are the opposite of those for an N-type channel. Note that the case of Al x Ga 1-x As y Sb 1-y that lattice matches with InAs (see FIG. 16) is the same, and the description thereof is omitted.
一方、ＧａＳｂと格子整合するＩｎＰｘＡｓｙＳｂ１−ｘ−ｙの場合（図１７参照）、タイプII型となる組合せは、一例としてＧａＳｂとＩｎＰｘＡｓｙＳｂ１−ｘ−ｙ（０．１３＜ｘ＜０．６３）がある。高いドレイン電流を得るために、例えばΔＥｃ−ｖ＝０．１ｅＶとするためには、ＩｎＰｘＡｓｙＳｂ１−ｘ−ｙ（ｘ＝０．２８）となる。このｘ組成の値は、当然、ΔＥｃ−ｖの設計値に依存するが、前述した通り、Ｅｃ、Ｅｖの図面は単純な内挿であり、実際とは異なっている可能性があるため、あくまでｘ組成の値は参考値である。Ｎ型チャネルの場合には、ＧａＳｂをソースとし、ＩｎＰｘＡｓｙＳｂ１−ｘ−ｙ（０．１３＜ｘ＜０．６３）をチャネルとする。Ｐ型チャネルの場合には、ソースとチャネルの材料が、Ｎ型チャネルの場合と逆になる。なお、ＩｎＡｓまたはＡｌＳｂと格子整合するＩｎＰｘＡｓｙＳｂ１−ｘ−ｙの場合（図１８及び図１９参照）は、同様であるので、説明を省略する。 On the other hand, in the case of InP x As y Sb 1- xy that lattice-matches with GaSb (see FIG. 17), the type II type combination is GaSb and InP x As y Sb 1-xy (0. 13 <x <0.63). In order to obtain a high drain current, for example in order to .DELTA.Ec-v = 0.1 eV is a InP x As y Sb 1-x -y (x = 0.28). The value of this x composition naturally depends on the design value of ΔEc−v. However, as described above, the drawings of Ec and Ev are simple interpolations and may differ from actual ones. The value of x composition is a reference value. In the case of an N-type channel, GaSb is used as a source, and InP x As y Sb 1-xy (0.13 <x <0.63) is used as a channel. In the case of a P-type channel, the source and channel materials are the opposite of those for an N-type channel. In the case of InP x As y Sb 1- xy that lattice matches with InAs or AlSb (see FIGS. 18 and 19), the description is omitted.
また、図１２、１５、１７に示したＧａＳｂと格子整合する、ＧａｘＩｎ１−ｘＡｓｙＳｂ１−ｙ、ＡｌｘＧａ１−ｘＡｓｙＳｂ１−ｙ、ＩｎＰｘＡｓｙＳｂ１−ｘ−ｙの内、任意の２種類の材料をヘテロ接合に用いることも可能であり、図１３、１６、１８に示したＩｎＡｓと格子整合する、ＧａｘＩｎ１−ｘＡｓｙＳｂ１−ｙ、ＡｌｘＧａ１−ｘＡｓｙＳｂ１−ｙ、ＩｎＰｘＡｓｙＳｂ１−ｘ−ｙの内、任意の２種類の材料をヘテロ接合に用いることも可能であり、図１４、１９に示したＡｌＳｂと格子整合する、ＧａｘＩｎ１−ｘＡｓｙＳｂ１−ｙ、ＩｎＰｘＡｓｙＳｂ１−ｘ−ｙの内、任意の２種類の材料をヘテロ接合に用いることも可能である。これらの材料は、全てＧａＳｂ又はＩｎＡｓ又はＡｌＳｂと格子整合するので、それらを用いたヘテロ接合にはミスフィット転位等の欠陥が形成されない。これらのヘテロ接合をタイプII型にする設計方法や、所望のΔＥｃ−ｖの値にする設計方法は、図１２乃至１９を用いて説明した方法と同様であるので、説明を省略する。 Further, the GaSb lattice-matched that shown in FIG. 12,15,17, Ga x In 1-x As y Sb 1-y, Al x Ga 1-x As y Sb 1-y, InP x As y Sb 1- Any two kinds of materials among x-y can be used for the heterojunction, and Ga x In 1-x As y Sb 1-y is lattice-matched with InAs shown in FIGS. , Al x Ga 1-x As y Sb 1-y , and InP x As y Sb 1-xy can be used for any two kinds of materials for the heterojunction, as shown in FIGS. It is also possible to use any two kinds of materials of Ga x In 1-x As y Sb 1-y and InP x As y Sb 1- xy that lattice match with AlSb for the heterojunction. All of these materials lattice match with GaSb, InAs, or AlSb, so that defects such as misfit dislocations are not formed in the heterojunction using them. The design method for making these heterojunctions type II and the design method for making the desired ΔEc-v value are the same as the method described with reference to FIGS.
以下、図２０乃至２２を参照して、本実施形態の半導体装置の製造方法に含まれるトランジスタ製造工程の流れの一例（Ｎ型チャネル）を説明する。 Hereinafter, an example (N-type channel) of a transistor manufacturing process included in the method for manufacturing a semiconductor device of this embodiment will be described with reference to FIGS.
まず、ドーピング制御したエピタキシャル成長法により、図２０に示す様に、ＧａＳｂ基板上に、順に、３００〜５００ｎｍ程度のＧａＳｂバッファ領域、ソースとなる５０〜３００ｎｍ程度のP＋ＧａＳｂ領域、チャネルとなる１０〜３００ｎｍ程度のノンドープＧａｘＩｎ１−ｘＡｓｙＳｂ１−ｙ領域、ドレインとなる５０〜３００ｎｍ程度のＮ＋ＧａｘＩｎ１−ｘＡｓｙＳｂ１−ｙ領域を形成する。結晶成長方法としては、有機金属化学気相エピタキシー法（ＭＯＶＰＥ）や分子線エピタキシー法（ＭＢＥ）が用いられる。ｘ、ｙ組成の値は、Ｇａ、Ｉｎ、Ａｓ、Ｓｂ各元素の原料のフラックスの比率で制御し、ドーピング量はドーパント原料と各元素原料のフラックス比で制御する。 First, by doping-controlled epitaxial growth, as shown in FIG. 20, a GaSb buffer region of about 300 to 500 nm, a P + GaSb region of about 50 to 300 nm serving as a source, and 10 to 10 serving as a channel are sequentially formed on a GaSb substrate. A non-doped Ga x In 1-x As y Sb 1-y region of about 300 nm and an N + Ga x In 1-x As y Sb 1-y region of about 50 to 300 nm serving as a drain are formed. As a crystal growth method, a metal organic chemical vapor epitaxy method (MOVPE) or a molecular beam epitaxy method (MBE) is used. The values of the x and y compositions are controlled by the ratio of the raw material flux of each element of Ga, In, As, and Sb, and the doping amount is controlled by the flux ratio of the dopant raw material and each elemental material.
次に、図２１に示す様に、ドライエッチング又はウェットエッチングにより、メサ構造を形成した後、ゲート絶縁膜として５ｎｍ程度のＡｌ２Ｏ３膜を原子層堆積法（ＡＬＤ）で形成し、次いで、ゲート電極として１００ｎｍ程度のＴｉＮをスパッタ法で形成した後、リソグラフィ法とドライエッチング法で、ゲート電極をパターニングする。 Next, as shown in FIG. 21, after forming a mesa structure by dry etching or wet etching, an Al 2 O 3 film of about 5 nm is formed by atomic layer deposition (ALD) as a gate insulating film, After forming about 100 nm of TiN as a gate electrode by sputtering, the gate electrode is patterned by lithography and dry etching.
次に、図２２に示す様に、層間膜として２００ｎｍ程度のＳｉＯ２膜を化学気相成長法（ＣＶＤ）で形成した後、リソグラフィ法とドライエッチング法で、ソース領域とドレイン領域にコンタクトを開口する。次いで、金属をスパッタ法で堆積し、リソグラフィ法とドライエッチング法で、ソース電極とドレイン電極を形成する。 Next, as shown in FIG. 22, an SiO 2 film having a thickness of about 200 nm is formed as an interlayer film by chemical vapor deposition (CVD), and then contacts are opened in the source region and the drain region by lithography and dry etching. To do. Next, a metal is deposited by a sputtering method, and a source electrode and a drain electrode are formed by a lithography method and a dry etching method.
その他のヘテロ接合からなるトンネル障壁を含むトランジスタを有する半導体装置の製造方法は、上記と同様にして実現できる。なお、基板としては、ＧａＳｂと格子整合するヘテロ接合の場合にはＧａＳｂ基板を、ＩｎＡｓと格子整合するヘテロ接合の場合にはＩｎＡｓ基板を、ＡｌＳｂと格子整合するヘテロ接合の場合にはＡｌＳｂ基板をそれぞれ用いることができる。２元III−Ｖ族化合物基板と格子整合させることで、基板とヘテロエピタキシャル層との間に、格子緩和バッファ層を形成する必要がなく、格子定数の制御性が良く、プロセスが簡単なことから、高い歩留りと低コストで製造できる利点がある。 Other methods for manufacturing a semiconductor device having a transistor including a tunnel barrier made of a heterojunction can be realized in the same manner as described above. As the substrate, a GaSb substrate is used in the case of a heterojunction lattice-matched with GaSb, an InAs substrate is used in a heterojunction lattice-matched with InAs, and an AlSb substrate is used in a heterojunction lattice-matched with AlSb. Each can be used. Lattice matching with a binary III-V compound substrate eliminates the need to form a lattice relaxation buffer layer between the substrate and the heteroepitaxial layer, provides good control of the lattice constant, and simplifies the process. There is an advantage that it can be manufactured with high yield and low cost.
なお、上記実施形態では、タイプII型ヘテロ接合からなるトンネル障壁を含むトランジスタ、及び、当該トランジスタを有する半導体装置を説明したが、本実施形態は、その他、タイプI型ヘテロ接合からなるトンネル障壁を含むトランジスタ、及び、当該トランジスタを有する半導体装置とすることもできる。本発明で重要な点は、ソースとチャネル間の価電子帯端と伝導帯端のエネルギー差ΔＥｃ−ｖを所望の値に設計することであり、その設計ができればタイプIであるかタイプIIであるかは関係がないからである。この製造方法は、上述したタイプII型ヘテロ接合からなるトンネル障壁を含むトランジスタ、及び、当該トランジスタを有する半導体装置の製造方法に準じて実現できる。 In the above embodiment, a transistor including a tunnel barrier formed of a type II heterojunction and a semiconductor device including the transistor have been described. However, in the present embodiment, a tunnel barrier formed of a type I heterojunction is additionally provided. A transistor including the transistor and a semiconductor device including the transistor can also be used. The important point in the present invention is to design the energy difference ΔEc−v between the valence band edge and the conduction band edge between the source and the channel to a desired value. If the design can be made, it is type I or type II. This is because there is no relationship. This manufacturing method can be realized according to the above-described method for manufacturing a transistor including a tunnel barrier formed of a type II heterojunction and a semiconductor device having the transistor.
Claims (10)
前記第１の材料及び前記第２の材料の格子定数が、ＧａＳｂ、ＩｎＡｓ又はＡｌＳｂと一致する半導体装置。 The semiconductor device according to claim 1,
A semiconductor device in which the lattice constants of the first material and the second material coincide with GaSb, InAs, or AlSb.
前記ヘテロ接合が、Ｇａｘ１Ｉｎ１−ｘ１Ａｓｙ１Ｓｂ１−ｙ１、Ａｌｘ２Ｇａ１−ｘ２Ａｓｙ２Ｓｂ１−ｙ２、ＩｎＰｘ３Ａｓｙ３Ｓｂ１−ｘ３−ｙ３の中の何れか２種類の材料で構成されている半導体装置。 The semiconductor device according to claim 1 or 2,
The heterojunction, Ga x1 In 1-x1 As y1 Sb 1-y1, Al x2 Ga 1-x2 As y2 Sb 1-y2, InP x3 As y3 any two among Sb 1-x3-y3 material A semiconductor device composed of
前記第１の材料はＧａＳｂ、ＩｎＡｓ又はＡｌＳｂであり、前記第２の材料は前記第１の材料と格子定数が一致する半導体装置。 The semiconductor device according to claim 3.
The first material is GaSb, InAs, or AlSb, and the second material is a semiconductor device having a lattice constant that matches that of the first material.
前記第１の材料及び前記第２の材料の格子定数が、ＧａＳｂ、ＩｎＡｓ又はＡｌＳｂと一致するトランジスタ。 The transistor of claim 5, wherein
A transistor in which the lattice constants of the first material and the second material match those of GaSb, InAs, or AlSb.
前記ヘテロ接合が、Ｇａｘ１Ｉｎ１−ｘ１Ａｓｙ１Ｓｂ１−ｙ１、Ａｌｘ２Ｇａ１−ｘ２Ａｓｙ２Ｓｂ１−ｙ２、ＩｎＰｘ３Ａｓｙ３Ｓｂ１−ｘ３−ｙ３の中の何れか２種類の材料で構成されているトランジスタ。 The transistor according to claim 5 or 6,
The heterojunction, Ga x1 In 1-x1 As y1 Sb 1-y1, Al x2 Ga 1-x2 As y2 Sb 1-y2, InP x3 As y3 any two among Sb 1-x3-y3 material A transistor composed of
前記第１の材料はＧａＳｂ、ＩｎＡｓ又はＡｌＳｂであり、前記第２の材料は前記第１の材料と格子定数が一致するトランジスタ。 The transistor of claim 7, wherein
The first material is GaSb, InAs, or AlSb, and the second material is a transistor whose lattice constant matches that of the first material.
前記工程では、格子定数が一致する第１の材料と第２の材料の少なくとも一方の材料の組成を調整することにより、格子定数を一定に保ったまま、前記第１の材料の伝導帯端と前記第２の材料の価電子帯端のエネルギー差を連続的に変化させ、前記第１の材料の伝導帯端と前記第２の材料の価電子帯端のエネルギー差が所定の値となるヘテロ接合からなるトンネル障壁を含むトランジスタを設計する半導体装置の製造方法。 Designing a transistor including a tunnel barrier composed of a heterojunction formed of a lattice-matched material;
In the step, by adjusting the composition of at least one of the first material and the second material having the same lattice constant, the conduction band edge of the first material is maintained while keeping the lattice constant constant. The energy difference between the valence band edges of the second material is continuously changed so that the energy difference between the conduction band edge of the first material and the valence band edge of the second material becomes a predetermined value. A method of manufacturing a semiconductor device for designing a transistor including a tunnel barrier formed of a junction.
前記工程では、格子定数が一致する第１の材料と第２の材料の少なくとも一方の材料の組成を調整することにより、格子定数を一定に保ったまま、前記第１の材料の伝導帯端と前記第２の材料の価電子帯端のエネルギー差を連続的に変化させ、前記第１の材料の伝導帯端と前記第２の材料の価電子帯端のエネルギー差が所定の値となるヘテロ接合からなるトンネル障壁を含むトランジスタを設計するトランジスタの製造方法。 Designing a transistor including a tunnel barrier composed of a heterojunction formed of a lattice-matched material;
In the step, by adjusting the composition of at least one of the first material and the second material having the same lattice constant, the conduction band edge of the first material is maintained while keeping the lattice constant constant. The energy difference between the valence band edges of the second material is continuously changed so that the energy difference between the conduction band edge of the first material and the valence band edge of the second material becomes a predetermined value. A transistor manufacturing method for designing a transistor including a tunnel barrier formed of a junction.
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