CN105552120A - Staggered heterojunction tunneling field effect transistor based on GaAsBi-Ga(In)AsN material - Google Patents
Staggered heterojunction tunneling field effect transistor based on GaAsBi-Ga(In)AsN material Download PDFInfo
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- 239000000463 material Substances 0.000 title claims abstract description 30
- 230000005641 tunneling Effects 0.000 title claims abstract description 28
- 230000005669 field effect Effects 0.000 title claims abstract description 22
- 239000002131 composite material Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 32
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 22
- 230000008569 process Effects 0.000 claims description 19
- 238000002513 implantation Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 9
- 239000007787 solid Substances 0.000 claims description 9
- 229910052785 arsenic Inorganic materials 0.000 claims description 8
- 230000008020 evaporation Effects 0.000 claims description 8
- 238000001704 evaporation Methods 0.000 claims description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims description 8
- 229910052733 gallium Inorganic materials 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
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- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 230000000873 masking effect Effects 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 claims description 2
- 125000001309 chloro group Chemical group Cl* 0.000 claims 1
- 238000001451 molecular beam epitaxy Methods 0.000 claims 1
- 230000004888 barrier function Effects 0.000 abstract description 3
- 239000000470 constituent Substances 0.000 abstract 2
- 229910052797 bismuth Inorganic materials 0.000 description 9
- 230000007246 mechanism Effects 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 229910000789 Aluminium-silicon alloy Inorganic materials 0.000 description 1
- 235000007926 Craterellus fallax Nutrition 0.000 description 1
- 240000007175 Datura inoxia Species 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
- H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/207—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
Abstract
The invention discloses a staggered heterojunction tunneling field effect transistor based on a GaAsBi-Ga(In)AsN material, and aims to solve the problem of poor performance of a tunneling field effect transistor prepared from an existing III-V group of materials. The staggered heterojunction tunneling field effect transistor comprises a substrate (1), a drain (2), a channel (3), a source (4), an oxide layer (5) and a gate electrode (6), wherein the channel and the drain each adopts a GaAsBi composite material with Bi constituent of (0.0, 0.1], the source adopts a Ga(In)AsN composite material with N constituent of (0, 0.09], the source, the channel and the drain are sequentially and vertically arranged, and the oxide layer and the gate electrode wrap the channel. Through mutual contact of the source electrode Ga(In)AsN and the channel GaAsBi, a staggered heterojunction tunnel junction is formed, the tunneling barrier height is reduced, the tunneling probability and the tunneling current are increased, the comprehensive performance of a device is enhanced, and the staggered heterojunction tunneling field effect transistor can be used for fabricating a large-scaled integrated circuit.
Description
Technical field
The invention belongs to technical field of microelectronic devices, particularly the staggered heterojunction tunneling field-effect transistor of one, can be used for large scale integrated circuit.
Background technology
Along with the fast development of integrated circuit technique, chip feature sizes is constantly reducing, and on one single chip, integrated level improves constantly, and the power consumption penalty therefore brought becomes a key difficult problem.According to the display of ITRS data, when characteristic size is reduced to 32nm node, power consumption can be 8 times of expectation trend, and namely under little characteristic size, conventional MOS device will can not meet performance requirement because power consumption penalty is serious.Meanwhile, along with the reduction of characteristic size, MOSFET is faced with the restriction that the subthreshold amplitude of oscillation under room temperature cannot break through 60mv/decade.Tunneling field-effect transistor TFET based on voltage-controlled interband quantum tunneling mechanism adopts because of it working mechanism being different from conventional MOSFET device, thus not by the restriction of the MOSTET subthreshold amplitude of oscillation, and can effectively reduce power consumption.Current, for TFET, the problem of the most key property increases tunnelling probability and then promotes tunnelling current, and material engineering and energy band engineering enjoy the concern of numerous researchers, expect to utilize material engineering and energy band engineering to solve this difficult problem.In theory with verified in experiment: staggered heterojunction TFET, compared with homojunction TFET, because it can realize less effective energy gap, thus can have higher tunnelling current and more excellent device performance.
III-V material has high electron mobility because of it, and material category comparatively horn of plenty, easily realize heterojunction, become the focus of people's research, now successfully prepared many high-performance TFET devices.TFET prepared by the III-V material related at present, because it cannot form staggered heterojunction, tunnelling probability is lower, cause On current less, or form staggered heterojunction, but composition material is certainly as low bandgap material, cause leakage current too high, be difficult to reach performance requirement.
Summary of the invention
Deficiency existing when the object of the invention is to prepare TFET for common III-V material, and in conjunction with the distinctive character of Ga (In) AsN, GaAsBi material self, staggered heterojunction tunneling field-effect transistor of a kind of GaAsBi-GaAs (In) N and preparation method thereof is provided, to reduce tunneling barrier, increase tunnelling current, reduce leakage current simultaneously, improve the overall performance of device.
Technical scheme of the present invention is achieved in that
One, know-why:
Show according to material behavior research, in common III-V material GaAs, introduce N or Bi component, effectively can improve material character, and the impact of N and Bi element on GaAs material is different.Mix N element in GaAs after, GaAs conduction band positions is mainly made to move down rapidly, and mix Bi element and mainly make the valence band location of GaAs is moved, according to Solid Band Structure arrangement principle, Ga (In) AsN/GaAsBi can form good staggered heterojunction, has little tunable effective energy gap, thus reduces potential barrier, promote tunnelling probability, increase On current.And GaAsBi and Ga (In) AsN material still has larger energy gap when Bi and N component is relatively high, thus effectively can reduce leakage current, boost device overall performance.
Two, device architecture
According to the staggered heterojunction tunneling field-effect transistor of this principle GaAsBi-Ga of the present invention (In) AsN material, comprising: substrate, drain electrode, raceway groove, source electrode, oxide layer film and gate electrode; Drain electrode, raceway groove and source electrode vertically distribute from the bottom to top successively on substrate, and oxide layer film and gate electrode are from inside to outside around the surrounding covering raceway groove, it is characterized in that: drain electrode and raceway groove all adopt general formula to be GaAs
1-ybi
ycomposite material, source electrode adopt general formula be Ga (In) As
1-xn
xcomposite material, form staggered heterogeneous tunnel junctions with the interface between source electrode Ga (In) AsN and raceway groove GaAsBi, wherein y is Bi component, 0≤y≤0.1, and x is N component, and 0<x≤0.09.
Make the method for the invention described above device, comprise the steps:
1) utilize molecular beam epitaxial process, be the GaAsBi composite material of 0 ~ 0.1 in GaAs substrate (1) upper growth Bi component, form drain electrode layer;
2) utilize molecular beam epitaxial process, GaAsBi source layer grows the GaAsBi composite material that Bi component is 0 ~ 0.1, form channel layer;
3) utilize molecular beam epitaxial process, GaAsBi channel layer grows Ga (In) the AsN composite material that N component is 0 ~ 0.09, form source layer;
4) etching technics is utilized, by source layer, channel layer, the partial etching of drain electrode layer surrounding falls, at the vertical distributed architecture in formation source region, centre, channel region, drain region;
5) carry out to source region, channel region and drain region the ion implantation that energy is 20KeV, namely in source region, implantation dosage is 10
19cm
-3te element, formed N
+impure source (4), in channel region, implantation dosage is 10
15cm
-3te element, formed N
-the raceway groove (3) of doping, in drain region, implantation dosage is 10
19cm
-3si element, formed P
+doped-drain (2);
6) utilize atomic layer deposition processes or chemical vapor deposition method, under respective environment, generate oxide layer film (5) and gate electrode (6) successively in raceway groove (3) surrounding.
Tool of the present invention has the following advantages:
The present invention owing to introducing N and Bi component in GaAs, change GaAs material and comprise the character that can be with, simultaneously because source electrode adopts Ga (In) AsN composite material, raceway groove adopts GaAsBi composite material, the staggered heterojunction of the heterojunction that the raceway groove made and source contact are formed, and along with the increase of N and Bi component, effective energy gap on staggered heterojunction surface constantly reduces, namely effectively reduce tunneling barrier, increase tunnelling probability, improve On current; Meanwhile, Ga (In) AsN and GaAsBi self energy gap is comparatively large, effectively reduces leakage current, and then improves device performance.
Accompanying drawing explanation
Fig. 1 is staggered heterojunction tunneling field-effect transistor profile of the present invention;
Fig. 2 is the schematic flow sheet of system of the present invention staggered heterojunction P raceway groove tunneling field-effect transistor.
Fig. 3 is the schematic flow sheet that the present invention makes staggered heterojunction N raceway groove tunneling field-effect transistor.
Embodiment
In order to make objects and advantages of the present invention clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
With reference to Fig. 1, comprise based on the staggered heterojunction tunneling field-effect transistor of GaAsBi-Ga (In) AsN material in the present invention: substrate 1, drain electrode 2, raceway groove 3, source electrode 4, oxide layer film 5 and gate electrode 6.This source electrode 4 adopts general formula to be Ga (In) As
1-xn
xcomposite material, wherein x is the component of N, 0<x≤0.1; This raceway groove 3 and drain electrode 2 all adopt general formula to be GaAs
1-ybi
ycomposite material, wherein y is the component of Bi, 0<y≤0.09; This substrate 1 adopts non-impurity-doped (100) crystal orientation GaAs or Ge material; This oxide layer film 5 is SiO
2or HfO
2or Al
2o
3; This gate electrode 6 adopts Poly-Si or Al or TiN or AlSi material.
Substrate 1, drain electrode 2, raceway groove 3, source electrode 4 vertically distribute from bottom to top, and form staggered tunnel junctions at source electrode 4 and the contact position of raceway groove 3.Oxide layer film 5 and gate electrode 6 are looped around the periphery of raceway groove 3 successively.
With reference to Fig. 2, the present invention makes the method based on the staggered heterojunction tunneling field-effect transistor of GaAsBi-Ga (In) AsN material, provides following three kinds of embodiments.
Embodiment 1: make GaAs
0.904n
0.096/ GaAs
0.92bi
0.08staggered heterojunction P raceway groove tunneling field-effect transistor.
With reference to Fig. 2, the performing step of this example is as follows:
Step 1: growth drain electrode layer
Utilize molecular beam epitaxial process, at non-impurity-doped (100) on GaAs substrate 1, using solid Ga, As and Bi as evaporation source, under temperature is 360 DEG C of conditions, growth Bi component is the GaAsBi composite material of 0.08, forms drain electrode layer, as Fig. 2 (a).
Step 2: make channel layer
Utilize molecular beam epitaxial process, on drain electrode layer, using solid Ga, As and Bi as evaporation source, under temperature is 360 DEG C of conditions, growth Bi component is the GaAsBi composite material of 0.08, forms channel layer, as Fig. 2 (b).
Above-mentioned molecular beam epitaxial process, with reference to X.Lu, D.A.Beaton, R.B.Lewisetal., EffectofmolecularbeamepitaxygrowthconditionsontheBiconte ntofGaAs
1-xbi
x[J] .AppliedPhysicsLetters, 2008,92 (19): 192110.
Step 3: growth source layer
Utilize molecular beam epitaxial process, on channel layer, using solid Ga, As and N as evaporation source, under temperature is 500 DEG C of conditions, growth N component is the GaAsN composite material of 0.096, forms source layer, as Fig. 2 (c).
The molecular beam epitaxial process of this step, with reference to I.Suemune, K.Uesugi, T.Y.Seong, GrowthandstructuralcharacterizationofIII – N – Vsemiconductoralloys [J] .Semiconductorscienceandtechnology, 2002,17 (8): 755.
Step 4: etching source layer, channel layer and drain electrode layer
Utilize Cl
2, BCl
3, CH
4as gas source, source layer, channel layer and drain electrode layer surrounding redundance, as etching gas, under the masking action of photoresist, etch by Ar mixing, the vertical distributed architecture in top-down source area, channel region and drain region is formed, as Fig. 2 (d) in centre.
Step 5: ion implantation is carried out to source area, channel region and drain region.
In drain region, Implantation Energy is 20KeV, dosage is 10
19cm
-3si element, formed p
+the drain electrode 2 of doping;
In channel region, Implantation Energy is 20KeV, dosage is 10
15cm
-3te element, formed n
-the raceway groove 3 of doping;
In source area, Implantation Energy is 20KeV, dosage is 10
19cm
-3te element, formed n
+impure source 4, as Fig. 2 (e).
Step 6: deposited oxide layer and gate electrode.
Utilize chemical vapor deposition techniques first under 200 DEG C of conditions, pass into SiH
4and N
2o, gas flow rate is respectively 20sccm and 10sccm, in raceway groove 3 surrounding around deposited oxide layer SiO
2shape oxide layer film 5; Form gate electrode 6 in the surrounding of oxide layer film 5 around deposit Poly-Si and Al metallic film again, thus to realize in raceway groove 3 surrounding, around the structure generating oxide layer oxide layer film 5 and gate electrode 6 successively, as Fig. 2 (f), completing element manufacturing.
Embodiment 2: make GaAs
0.928n
0.072/ GaAs
0.94bi
0.06staggered heterojunction P raceway groove tunneling field-effect transistor
With reference to Fig. 2, the performing step of this example is as follows:
Step one: utilize molecular beam epitaxial process, at non-impurity-doped (100) on Ge substrate 1, using solid Ga, As and Bi as evaporation source, under temperature is 380 DEG C of conditions, growth Bi component is the GaAsBi composite material of 0.06, forms drain electrode layer, as Fig. 2 (a).
Step 2: utilize molecular beam epitaxial process, on drain electrode layer, using solid Ga, As and Bi as evaporation source, under temperature is 380 DEG C of conditions, growth Bi component is the GaAsBi composite material of 0.06, forms channel layer, as Fig. 2 (b).
Step 3: utilize molecular beam epitaxial process, on channel layer, using solid Ga, As and N as evaporation source, under temperature is 550 DEG C of conditions, growth N component is the GaAsN composite material of 0.072, forms drain electrode layer, as Fig. 2 (c).
Step 4: utilize Cl
2, BCl
3, CH
4as gas source, source layer, channel layer and drain electrode layer surrounding redundance, as etching gas, under the masking action of photoresist, etch by Ar mixing, the vertical distributed architecture in top-down source area, channel region and drain region is formed, as Fig. 2 (d) in centre.
Step 5: ion implantation is carried out to source area, channel region and drain region:
In drain region, Implantation Energy is 20KeV, dosage is 10
19cm
-3si element, formed p
+the drain electrode 2 of doping;
In channel region, Implantation Energy is 20KeV, dosage is 10
15cm
-3te element, formed n
-the raceway groove 3 of doping;
In source area, Implantation Energy is 20KeV, dosage is 10
19cm
-3te element, formed n
+impure source 4; As Fig. 2 (e).
Step 6: utilize atomic layer deposition processes, first in raceway groove 3 surrounding around deposited oxide layer HfO
2form oxide layer film 5; Form gate electrode 6 in the surrounding of oxide layer film 5 around deposit Poly-Si and Al metallic film again, thus to realize in raceway groove 3 surrounding, around the structure generating oxide layer film 5 and gate electrode 6 successively, as Fig. 2 (f), completing element manufacturing.
The concrete operations of this step depositing technics are see B.H.Lee, L.Kangetal., Thermalstabilityandelectricalcharacteristicsofultrathinh afniumoxidegatedielectricreoxidizedwithrapidthermalannea ling [J] .AppliedPhysicsLetters, 2000,76 (14): 1926-1928.
Embodiment 3: make GaAs
0.976n
0.024/ GaAs
0.98bi
0.02staggered heterojunction N raceway groove tunneling field-effect transistor
With reference to Fig. 3, the performing step of this example is as follows:
Steps A: epitaxial drain layer
Utilize molecular beam epitaxial process, in (100) on GaAs substrate 1, growth N component is the GaAsN composite material of 0.024, form drain electrode layer, as Fig. 3 (a), the process conditions of its growth are: evaporation source is solid Ga, As and N, and temperature is 600 DEG C.
Step B: growth channel layer
Utilize molecular beam epitaxial process, on GaAsN drain electrode layer, growth N component is the GaAsN composite material of 0.024, forms channel layer, and as Fig. 3 (b), the process conditions of its growth are: evaporation source is solid Ga, As and N, and temperature is 600 DEG C.
Step C: prepare source layer
Utilize molecular beam epitaxial process, on GaAsN channel layer, growth Bi component is the GaAsBi composite material of 0.02, forms source layer, and as Fig. 3 (c), the process conditions of its growth are: evaporation source solid Ga, As and Bi, temperature is 400 DEG C.
Step D: preparation source, drain electrode and channel region.
The specific implementation of this step is identical with the step 4 of embodiment 1.
Step e: ion implantation is carried out to source, drain region and channel region.
First, in drain region, Implantation Energy is 20KeV, dosage is 10
19cm
-3te element, formed n
+assorted drain electrode 2,
Secondly, in channel region, Implantation Energy is 20KeV, dosage is 10
15cm
-3si element, formed p
-raceway groove 3;
Finally, in source area, Implantation Energy is 20KeV, dosage is 10
19cm
-3si element, formed p
+impure source 4; As Fig. 3 (e).
Step F: preparation oxide layer and gate electrode,
Utilize atomic layer deposition processes, first in ALD reaction chamber 300 DEG C, in 665Pa environment, N
2under atmosphere, use TMC and H
2o in the surrounding of raceway groove 3 around deposited oxide layer Al
2o
3; Then at oxide layer Al
2o
3surrounding again around depositing metal Al film, generate the structure of oxide layer film 5 and gate electrode 6 successively, as Fig. 3 (f), complete element manufacturing.
The above is only several preferred implementation of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (9)
1. based on the staggered heterojunction tunneling field-effect transistor of GaAsBi-Ga (In) AsN material, comprising: substrate (1), drain electrode (2), raceway groove (3), source electrode (4), oxide layer (5) and gate electrode (6); Drain electrode (2), raceway groove (3) and source electrode (4) vertically distribute from the bottom to top successively on substrate (1), and oxide layer film (5) and gate electrode (6) are from inside to outside around the surrounding covering raceway groove (3), it is characterized in that: drain electrode (2) and raceway groove (3) all adopt general formula to be GaAs
1-ybi
ycomposite material, source electrode (4) adopt general formula be Ga (In) As
1-xn
xcomposite material, thus the interface between source electrode Ga (In) AsN and raceway groove GaAsBi forms staggered heterogeneous tunnel junctions, and wherein y is Bi component, 0<y≤0.1, and x is N component, and 0<x≤0.09.
2. as claimed in claim 1 based on the staggered tunneling field-effect transistor of GaAsBi-Ga (In) AsN material, it is characterized in that, substrate (1) adopts monocrystalline GaAs or Ge material.
3. as claimed in claim 1 based on the staggered tunneling field-effect transistor of GaAsBi-Ga (In) AsN material, it is characterized in that, oxide layer film (5) is wrapped in the outside of raceway groove (3), gate electrode (6) is wrapped in the outside of oxide layer film (5), is formed from inside to outside successively around package structure.
4., based on the manufacture method of the staggered tunneling field-effect transistor of GaAsBi-Ga (In) AsN material, comprise the steps:
1) utilize molecular beam epitaxial process, be the GaAsBi composite material of 0 ~ 0.1 in GaAs substrate (1) upper growth Bi component, form drain electrode layer;
2) utilize molecular beam epitaxial process, GaAsBi source layer grows the GaAsBi composite material that Bi component is 0 ~ 0.1, form channel layer;
3) utilize molecular beam epitaxial process, GaAsBi channel layer grows Ga (In) the AsN composite material that N component is 0 ~ 0.09, form source layer;
4) etching technics is utilized, by source layer, channel layer, the partial etching of drain electrode layer surrounding falls, at the vertical distributed architecture in formation source region, centre, channel region, drain region;
5) carry out to source region, channel region and drain region the ion implantation that energy is 20KeV, namely in source region, implantation dosage is 10
19cm
-3te element, formed N
+impure source (4), in channel region, implantation dosage is 10
15cm
-3te element, formed N
-the raceway groove (3) of doping, in drain region, implantation dosage is 10
19cm
-3si element, formed P
+doped-drain (2);
6) utilize atomic layer deposition processes or chemical vapor deposition method, under respective environment, generate oxide layer film (5) and gate electrode (6) successively in raceway groove (3) surrounding.
5. method as claimed in claim 4, wherein said step 1) and 2) molecular beam epitaxial process, be with solid Ga, Bi and As
2as evaporation source, epitaxial growth GaAsBi layer under temperature is 350 –, 410 DEG C of conditions.
6. method as claimed in claim 4, wherein said step 3) molecular beam epitaxy, be using solid Ga, As and N as evaporation source, epitaxial growth Ga (In) AsN layer under temperature is 420 –, 640 DEG C of conditions.
7. method as claimed in claim 4, wherein said step 4) etching technics, be utilize chloro atomic group, under the masking action of photoresist, etching GaAsBi and Ga (In) AsN material.
8. method as claimed in claim 4, wherein said step 5) ion implantation technology, being by injecting Te element in source electrode (4) and raceway groove (3), in drain electrode (2), injecting Si element form N-shaped and p-type area.
9. method as claimed in claim 4, wherein said step 6) atomic layer deposition processes or chemical vapor deposition method, be first in raceway groove (3) surrounding around deposit SiO
2or HfO
2or Al
2o
3form oxide layer film (5), then form gate electrode (6) in the surrounding of oxide layer film (5) around deposit Poly-Si or Al material.
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| WO2013179700A1 (en) * | 2012-05-31 | 2013-12-05 | 独立行政法人産業技術総合研究所 | Semiconductor device, transistor, method for manufacturing semiconductor device, and method for manufacturing transistor |
| CN105047719A (en) * | 2015-08-11 | 2015-11-11 | 西安电子科技大学 | Staggered heterojunction tunneling field effect transistor based on InAsN-GaAsSb material |
-
2015
- 2015-12-15 CN CN201510937928.7A patent/CN105552120A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013179700A1 (en) * | 2012-05-31 | 2013-12-05 | 独立行政法人産業技術総合研究所 | Semiconductor device, transistor, method for manufacturing semiconductor device, and method for manufacturing transistor |
| CN105047719A (en) * | 2015-08-11 | 2015-11-11 | 西安电子科技大学 | Staggered heterojunction tunneling field effect transistor based on InAsN-GaAsSb material |
Non-Patent Citations (1)
| Title |
|---|
| J. HWANG ET AL: "Band structure of strain-balanced GaAsBi/GaAsN superlattices on GaAs", 《PHYSICAL REVIEW B 83》 * |
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