CN103311215A - Molded interconnection system ball grid array integrated circuit - Google Patents
Molded interconnection system ball grid array integrated circuit Download PDFInfo
- Publication number
- CN103311215A CN103311215A CN2013101862114A CN201310186211A CN103311215A CN 103311215 A CN103311215 A CN 103311215A CN 2013101862114 A CN2013101862114 A CN 2013101862114A CN 201310186211 A CN201310186211 A CN 201310186211A CN 103311215 A CN103311215 A CN 103311215A
- Authority
- CN
- China
- Prior art keywords
- packaging
- base plate
- weld pad
- integrated circuit
- grid array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention discloses a molded interconnection system ball grid array integrated circuit (MISBGA), which comprises a package substrate and a package body, wherein the package body is arranged on the package substrate and comprises a lower spacer, a semiconductor element, sealing resin and a plurality of upper bonding pads; each upper bonding pad is communicated with a chip through a bonding wire; each upper bonding pad is arranged at one end of a via hole so as to be communicated with a lower bonding pad at the other end of the via hole through a metal material filled in the via hole; a solder ball is carried on the lower bonding pad; and the thickness of the substrate is 0.12 mm. By reducing the thickness of the conventional package substrate, the effective reduction of the size of the conventional semiconductor package is facilitated. The upper and lower bonding pads are arranged in an array, the reduction of the size of the package is facilitated, and more input and output channels are provided. Meanwhile, the via holes of a certain space are arranged, the U-shaped port strength enhancement design is matched, and the substrate is prepared from a proper material, so that the package substrate can be thinned and the requirements of structural strength can also be met.
Description
Technical field
The present invention relates to a kind of semiconductor package part, the mold pressing pattern internal wiring road ball grid array integrated circuit (MISBGA) that specifically a kind of structural strength is strong, size is ultra-thin belongs to the semiconductor packaging field.
Background technology
Along with electronic product to multi-functional, high-performance and microminiaturized development, the encapsulation of IC chip is required more and more stricter, when the IC frequency surpassed 100MHz, the conventional package mode such as DIP encapsulation, QFP encapsulation and PGA encapsulation, may produce the phenomenon that wiring is crosstalked.More and more less when the characteristic size of IC chip, complexity is more and more higher, be that I/0 number I/0 density more and more, encapsulation on the integrated circuit are when more and more higher, adopt the package pins spacing of above-mentioned conventional package technology constantly to dwindle, the center is crossed in actual production, not only can bring difficulty to production, also easily cause decrease in yield and assembly cost to improve.Therefore, a kind of chip soldered ball semiconductor packages BGA that solves the problems of the technologies described above arises at the historic moment, and becomes the preferred solution of high density, high-performance, many pin package.But the pin pitch of existing BGA product and thickness still are difficult to satisfy electronic product to the requirement of packaging part ultrathin and narrow pitch.
Usually the former material of BGA product use substrate is a monoblock resin and plastic, owing to forming the structural strength that the conducting perforation can reduce sheet material at substrate, in order to keep the structural strength of substrate, need to select the thicker substrate of thickness, so incite somebody to action so that the volume of traditional semiconductor package part can't effectively dwindle.Therefore, be necessary to provide a kind of proof strength structural behaviour, ultra-thin substrate, making the ultra-thin semiconductor packaging part, and then solve the existing problem of prior art.
Summary of the invention
The purpose of this invention is to provide a kind of semiconductor package part, especially relate to a kind of semiconductor package part, the packaging part of the mold pressing pattern internal wiring road ball grid array integrated circuit that specifically a kind of structural strength is strong, size is ultra-thin.Purpose of the present invention realizes by following technical proposals:
A kind of ultra-thin semiconductor packaging part, comprise the packaging body that arranges on base plate for packaging and the base plate for packaging, described packaging body comprises by binding agent and is bonded in lower gasket on the described base plate for packaging, carries the semiconductor element on described lower gasket and is used for the sealing resin of sealing.
Packaging body of the present invention also is included in weld pad on several is set on described base plate for packaging, each described upper weld pad is communicated to chip by the bonding wire of corresponding setting, each described upper weld pad is arranged at an end of the via of offering on the base plate for packaging, make weld pad be communicated to the lower weld pad that is positioned at the via other end by the metal material of filling in the via, be equipped with solder ball at described lower weld pad, the thickness of described base plate for packaging is at 0.12mm.
The present invention further, the diameter of described solder ball is 0.3mm, the thickness of described base plate for packaging is at 0.12mm, described upper weld pad and described lower weld pad are all surperficial at described base plate for packaging with array arrangement, help and dwindle the packaging part volume, and more Multiinputoutput passage is provided, described upper weld pad, via outer wall and described lower weld pad form increases U-shaped mouthful of base plate for packaging intensity.
The present invention further, the diameter of the described bonding wire ball of the Thickness Ratio of described base plate for packaging is little.
The present invention further, described base plate for packaging comprises by in iron, copper, resin or the ceramic material one or more to be made.
The present invention further, at least one surface of described base plate for packaging forms at least one surface lines layer.
Application of the present invention is implemented its remarkable technique effect is mainly reflected in:
1, passes through the reduced thickness of conventional package substrates to 0.12mm, help the volume of traditional semiconductor package part is effectively dwindled, the raw material of producing base plate for packaging adopts cheaply, and iron material replaces the high resin and plastic of traditional price, the unit price of the base plate for packaging of every monolithic reduces, and is conducive to reduce the cost of whole semiconductor package part;
2, show by the many experiments test, in the attenuate substrate, arrange a determining deviation via, cooperate the design of U-shaped mouth intensity enhancing, and prepare base plate for packaging with suitable material, can make base plate for packaging of the present invention can attenuate, can satisfy the requirement of structural strength again.
Following constipation closes accompanying drawing, the specific embodiment of the present invention is described in further detail, so that technical solution of the present invention is easier to understand, grasp.
Description of drawings
Fig. 1 is the structural representation of mold pressing pattern internal wiring of the present invention road ball grid array integrated circuit preferred embodiment;
Fig. 2 is weld pad array arrangement photo figure on the ball grid array integrated circuit of mold pressing pattern internal wiring of the present invention road;
Fig. 3 is weld pad array arrangement photo figure under the ball grid array integrated circuit of mold pressing pattern internal wiring of the present invention road;
Fig. 4 is mold pressing pattern internal wiring of the present invention road ball grid array integrated circuit partial structurtes schematic diagram.
Embodiment
The present invention will be described below in conjunction with accompanying drawing and specific embodiment, for embodiment the present invention is made the generality illustration, help to understand better the present invention, but can't limit the scope of the invention.
See also Fig. 1, ultra-thin semiconductor packaging part of the present invention, comprise as known in the art on base plate for packaging 2 and the base plate for packaging 2 packaging body that arranges, this packaging body comprises by binding agent and is bonded in lower gasket 23 on the base plate for packaging 2, carries the semiconductor element 1 on described lower gasket 23 and is used for the sealing resin 11 of sealing.As described in the present invention, packaging body also is included in weld pad 20 on several is set on base plate for packaging 2, weld pad 20 is communicated to chip 1 by the bonding wire 10 of corresponding setting on each, weld pad 20 is arranged at an end of the via of offering 24 on the base plate for packaging 2 on each, make weld pad 20 be communicated to the lower weld pad 21 that is positioned at via 24 other ends by the metal material of via 24 interior fillings, be equipped with solder ball 22 at lower weld pad 21.The more traditional base plate for packaging of the thickness of base plate for packaging 2 of the present invention is thin, be 0.12mm.
The diameter of described solder ball is 0.3mm, described upper weld pad and described lower weld pad all with array arrangement at described substrate surface, help and dwindle the packaging part volume, and more Multiinputoutput passage is provided, described upper weld pad, via outer wall and described lower weld pad form increases U-shaped mouthful of base plate for packaging intensity
The embodiment of the invention particularly, the diameter of solder ball 22 is 0.3mm, the thickness of described base plate for packaging 2 is at 0.12mm, the diameter of the Thickness Ratio solder ball 22 of base plate for packaging 2 is little, makes stable being fixed on the lower gasket 21 of bonding wire ball.As shown in Figures 2 and 3, described upper weld pad 20 and described lower weld pad 21 all with array arrangement on described base plate for packaging 2 surfaces, help and dwindle the packaging part volume, and more Multiinputoutput passage is provided.As shown in Figure 4, described upper weld pad 20, via 24 outer walls and described lower weld pad 21 form increases U-shaped mouthful of base plate for packaging intensity.Base plate for packaging 2 comprises can iron, in copper, resin or the ceramic material one or more are made, but be not limited to above-mentioned material.Base plate for packaging 2 at least one surfaces form at least one surface lines layer.In the concrete preparation process, conventional BGA method for packing as known to the skilled person, the present invention is applicable to dissimilar BGA encapsulation, according to the arrangement mode of solder ball 22, applicable to peripheral type, staggered or full array type, details are as follows take PBGA as the example concrete steps:
At first, the preparation of substrate, namely provide the as described herein base plate for packaging 2 of thickness, every base plate for packaging 2 all forms pre-set circuitous pattern thereon through conventional PCB processing technology lithography step in advance, such as the land array of via, electrode and installation solder ball 22; Then, adopt binding agent that chip 1 is bonded on the base plate for packaging 2, then adopt gold thread, copper wire bonding realization chip 1 to be connected with substrate; Then molding is sealed or the liquid glue embedding, with protection chip, bonding wire 10, upper weld pad 20 and lower weld pad 21; Use suction to pick up instrument solder ball 22 is placed on the lower weld pad 21, in traditional reflow soldering, carry out reflow soldering; At last, above-mentioned packaging body is carried out eccentric cleaning, remove scolder and the fiber grain stayed on the packaging body, again through mark, separation, inspection, test and packing warehouse-in, namely finish the encapsulation step of PBGA.The BGA encapsulation of other types is technology equally as known to those skilled in the art, is not again describing in detail.
Therefore, the present invention passes through the reduced thickness of conventional package substrates to 0.12mm, help the volume of traditional semiconductor package part is effectively dwindled, and reduce owing to producing the raw material of base plate for packaging, the unit price of the base plate for packaging of every monolithic reduces, and is conducive to reduce the cost of whole semiconductor package part; And, show through the many experiments test, in attenuate base plate for packaging 2, via 24, the cooperation U-shaped mouth intensity enhancing design (Fig. 4) of a determining deviation are set, and prepare base plate for packaging 2 with suitable material, can make base plate for packaging of the present invention can attenuate, can satisfy the requirement of structural strength again.
The above only is preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the technology of the present invention principle; can also make some improvement and modification, these improve and modification also should be considered as protection scope of the present invention.
Claims (5)
1. mold pressing pattern internal wiring road ball grid array integrated circuit, comprise the upper packaging body that arranges of base plate for packaging (2) and base plate for packaging (2), described packaging body comprises by binding agent and is bonded in lower gasket (23) on the described base plate for packaging (2), carries the semiconductor element (1) on described lower gasket (23) and is used for the sealing resin (11) of sealing, it is characterized in that:
Described packaging body also is included in described base plate for packaging, weld pad on several is set (2), (20), each described upper weld pad, (20) bonding wire by corresponding setting, (10) be communicated to chip, (1), each described upper weld pad, (20) be arranged at base plate for packaging, (2) via of offering on, (24) a end, make weld pad, (20) pass through via, the metal material of filling (24) is communicated to and is positioned at via, (24) the lower weld pad of the other end, (21), at described lower weld pad, (21) be equipped with solder ball on, (22)
The thickness of described base plate for packaging (2) is at 0.12mm, described upper weld pad (20) and described lower weld pad (21) all with array arrangement on described base plate for packaging (2) surface,
Described upper weld pad (20), via (24) outer wall and described lower weld pad (21) form increases U-shaped mouthful of base plate for packaging (2) intensity.
2. mold pressing pattern internal wiring according to claim 1 road ball grid array integrated circuit, it is characterized in that: the diameter of described solder ball (22) is 0.3mm.
3. mold pressing pattern internal wiring according to claim 1 road ball grid array integrated circuit, it is characterized in that: the diameter of the described solder ball of Thickness Ratio (22) of described base plate for packaging (2) is little.
4. mold pressing pattern internal wiring according to claim 1 road ball grid array integrated circuit is characterized in that: described base plate for packaging (2) comprises by in iron, copper, resin or the ceramic material one or more to be made.
5. mold pressing pattern internal wiring according to claim 1 road ball grid array integrated circuit, it is characterized in that: at least one surface of described base plate for packaging (2) forms at least one surface lines layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013101862114A CN103311215A (en) | 2013-05-17 | 2013-05-17 | Molded interconnection system ball grid array integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013101862114A CN103311215A (en) | 2013-05-17 | 2013-05-17 | Molded interconnection system ball grid array integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103311215A true CN103311215A (en) | 2013-09-18 |
Family
ID=49136268
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013101862114A Pending CN103311215A (en) | 2013-05-17 | 2013-05-17 | Molded interconnection system ball grid array integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103311215A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0823047A (en) * | 1994-07-06 | 1996-01-23 | Hitachi Cable Ltd | Bga type semiconductor device |
| JP2005277000A (en) * | 2004-03-24 | 2005-10-06 | Renesas Technology Corp | Method of manufacturing semiconductor device |
| US20090039488A1 (en) * | 2007-08-10 | 2009-02-12 | Siliconware Precision Industries Co., Ltd. | Semiconductor package and method for fabricating the same |
| CN203367270U (en) * | 2013-05-17 | 2013-12-25 | 矽品科技（苏州）有限公司 | Mould pressing type internal circuit ball grid array integrated circuit |
-
2013
- 2013-05-17 CN CN2013101862114A patent/CN103311215A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0823047A (en) * | 1994-07-06 | 1996-01-23 | Hitachi Cable Ltd | Bga type semiconductor device |
| JP2005277000A (en) * | 2004-03-24 | 2005-10-06 | Renesas Technology Corp | Method of manufacturing semiconductor device |
| US20090039488A1 (en) * | 2007-08-10 | 2009-02-12 | Siliconware Precision Industries Co., Ltd. | Semiconductor package and method for fabricating the same |
| CN203367270U (en) * | 2013-05-17 | 2013-12-25 | 矽品科技（苏州）有限公司 | Mould pressing type internal circuit ball grid array integrated circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7378297B2 (en) | Methods of bonding two semiconductor devices | |
| CN106887393B (en) | It is integrated with the packaging method of the encapsulating structure of power transmission chip | |
| CN206282838U (en) | The integrated encapsulation structure of passive device and active device | |
| CN103681371A (en) | Silica-based wafer level fan-out encapsulation method and silica-based wafer level fan-out encapsulation structure | |
| US9123629B2 (en) | Chip package and method for forming the same | |
| CN110211946A (en) | A kind of chip-packaging structure and its manufacturing method | |
| CN106356342A (en) | Packaging structure | |
| CN106531710A (en) | Packager piece of integrated power supply system and package method | |
| KR100800475B1 (en) | Package on package and method for a manufacturing the same | |
| CN108389850A (en) | Three-dimensional system level packaging structure and its packaging method | |
| CN110299328A (en) | A kind of stack packaged device and its packaging method | |
| CN203367270U (en) | Mould pressing type internal circuit ball grid array integrated circuit | |
| CN106898557A (en) | It is integrated with the method for packing of the packaging part of power transmission system | |
| CN203707108U (en) | Silica-based wafer level fan-out packaging structure | |
| CN103311215A (en) | Molded interconnection system ball grid array integrated circuit | |
| CN201000885Y (en) | Lead wire-free integrated circuit chip encapsulation | |
| KR20160017412A (en) | Stack type semiconductor package structure by use of cavity substrate and method thereof | |
| CN105390477B (en) | A kind of multi-chip 3 D secondary encapsulation semiconductor devices and its packaging method | |
| CN102556938B (en) | Stacked die package structure and manufacturing method thereof | |
| CN208460760U (en) | Three-dimensional system level packaging structure | |
| CN106449545A (en) | Packaging structure | |
| CN206179856U (en) | Superchip packaging structure that reroutes | |
| CN206003767U (en) | A kind of Ultrathin packaging device | |
| CN100539122C (en) | The packaging body of system in package | |
| CN204361080U (en) | Circuits System and chip package thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20130918 |
|
| RJ01 | Rejection of invention patent application after publication |