CN103210493A - 邻接的soi结隔离结构和器件以及制造方法 - Google Patents
邻接的soi结隔离结构和器件以及制造方法 Download PDFInfo
- Publication number
- CN103210493A CN103210493A CN2011800538131A CN201180053813A CN103210493A CN 103210493 A CN103210493 A CN 103210493A CN 2011800538131 A CN2011800538131 A CN 2011800538131A CN 201180053813 A CN201180053813 A CN 201180053813A CN 103210493 A CN103210493 A CN 103210493A
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- Prior art keywords
- epitaxial loayer
- doped
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- concentration
- silicon layer
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Links
- 238000002955 isolation Methods 0.000 title claims description 15
- 238000004519 manufacturing process Methods 0.000 title abstract description 8
- 239000002019 doping agent Substances 0.000 claims abstract description 147
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 109
- 239000010703 silicon Substances 0.000 claims abstract description 109
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 108
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000012212 insulator Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 20
- 230000008021 deposition Effects 0.000 claims description 9
- 230000005669 field effect Effects 0.000 claims description 9
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052799 carbon Inorganic materials 0.000 claims description 4
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 210000000746 body region Anatomy 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims 3
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 description 98
- 150000002500 ions Chemical class 0.000 description 16
- 230000000694 effects Effects 0.000 description 9
- 238000000151 deposition Methods 0.000 description 7
- 238000000137 annealing Methods 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000011960 computer-aided design Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 229910052914 metal silicate Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (25)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/943,084 | 2010-11-10 | ||
US12/943,084 US8741725B2 (en) | 2010-11-10 | 2010-11-10 | Butted SOI junction isolation structures and devices and method of fabrication |
PCT/US2011/060084 WO2012064912A2 (en) | 2010-11-10 | 2011-11-10 | Butted soi junction isolation structures and devices and method of fabrication |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103210493A true CN103210493A (zh) | 2013-07-17 |
CN103210493B CN103210493B (zh) | 2016-01-06 |
Family
ID=46018798
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201180053813.1A Active CN103210493B (zh) | 2010-11-10 | 2011-11-10 | 邻接的soi结隔离结构和器件以及制造方法 |
Country Status (6)
Country | Link |
---|---|
US (2) | US8741725B2 (zh) |
JP (1) | JP2014500621A (zh) |
CN (1) | CN103210493B (zh) |
DE (1) | DE112011103730B4 (zh) |
GB (1) | GB2497259B (zh) |
WO (1) | WO2012064912A2 (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105097520A (zh) * | 2014-05-04 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
CN108695161A (zh) * | 2017-04-07 | 2018-10-23 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
CN109950314A (zh) * | 2017-12-21 | 2019-06-28 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其制造方法 |
CN112204459A (zh) * | 2018-02-27 | 2021-01-08 | 洛克利光子有限公司 | 电吸收调制器 |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8741725B2 (en) | 2010-11-10 | 2014-06-03 | International Business Machines Corporation | Butted SOI junction isolation structures and devices and method of fabrication |
US8338279B2 (en) | 2011-03-30 | 2012-12-25 | International Business Machines Corporation | Reduced pattern loading for doped epitaxial process and semiconductor structure |
US9006827B2 (en) * | 2011-11-09 | 2015-04-14 | International Business Machines Corporation | Radiation hardened memory cell and design structures |
US9142642B2 (en) * | 2012-02-10 | 2015-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for doped SiGe source/drain stressor deposition |
US9236257B2 (en) * | 2013-03-13 | 2016-01-12 | Varian Semiconductor Equipment Associates, Inc. | Techniques to mitigate straggle damage to sensitive structures |
US9165944B2 (en) | 2013-10-07 | 2015-10-20 | Globalfoundries Inc. | Semiconductor device including SOI butted junction to reduce short-channel penalty |
US9209200B2 (en) | 2013-10-18 | 2015-12-08 | Globalfoundries Inc | Methods for forming a self-aligned maskless junction butting for integrated circuits |
US9385117B2 (en) * | 2013-12-31 | 2016-07-05 | Texas Instruments Incorporated | NPN heterojunction bipolar transistor in CMOS flow |
US10008383B2 (en) * | 2014-03-10 | 2018-06-26 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and manufacturing method thereof |
US9136321B1 (en) * | 2014-04-30 | 2015-09-15 | International Business Machines Corporation | Low energy ion implantation of a junction butting region |
EP3140680B1 (en) * | 2014-05-07 | 2021-04-21 | WiTricity Corporation | Foreign object detection in wireless energy transfer systems |
US9627480B2 (en) | 2014-06-26 | 2017-04-18 | Globalfoundries Inc. | Junction butting structure using nonuniform trench shape |
US9691669B1 (en) * | 2015-08-28 | 2017-06-27 | Pdf Solutions, Inc. | Test structures and methods for measuring silicon thickness in fully depleted silicon-on-insulator technologies |
US9905688B2 (en) * | 2016-01-28 | 2018-02-27 | Texas Instruments Incorporated | SOI power LDMOS device |
US10177243B1 (en) * | 2017-06-19 | 2019-01-08 | Nxp B.V. | Extended drain NMOS transistor with buried P type region |
CN109300789B (zh) * | 2017-07-25 | 2021-07-09 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
US10510886B2 (en) * | 2017-10-26 | 2019-12-17 | Samsung Electronics Co., Ltd. | Method of providing reacted metal source-drain stressors for tensile channel stress |
US20220246756A1 (en) * | 2021-01-29 | 2022-08-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure and method for manufacturing the same |
Citations (8)
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JPH07335888A (ja) * | 1994-06-13 | 1995-12-22 | Samsung Electron Co Ltd | シリコンオンインシュレータトランジスタ |
US5683934A (en) * | 1994-09-26 | 1997-11-04 | Motorola, Inc. | Enhanced mobility MOSFET device and method |
US6495402B1 (en) * | 2001-02-06 | 2002-12-17 | Advanced Micro Devices, Inc. | Semiconductor-on-insulator (SOI) device having source/drain silicon-germanium regions and method of manufacture |
US20040026746A1 (en) * | 2002-08-09 | 2004-02-12 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
US20040094802A1 (en) * | 2001-12-10 | 2004-05-20 | Hynix Semiconductor Inc. | Semiconductor device and method of forming the same |
CN1741277A (zh) * | 2004-08-27 | 2006-03-01 | 株式会社瑞萨科技 | 半导体装置及其制造方法 |
US20090026552A1 (en) * | 2007-07-27 | 2009-01-29 | Da Zhang | Method for forming a transistor having gate dielectric protection and structure |
US20090256201A1 (en) * | 2008-04-10 | 2009-10-15 | Advanced Micro Devices, Inc. | Metal oxide semiconductor transistor with reduced gate height, and related fabrication methods |
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US5057443A (en) * | 1988-06-29 | 1991-10-15 | Texas Instruments Incorporated | Method for fabricating a trench bipolar transistor |
US6452233B1 (en) * | 1999-03-23 | 2002-09-17 | Citizen Watch Co., Ltd. | SOI device having a leakage stopping layer |
US7534689B2 (en) * | 2006-11-21 | 2009-05-19 | Advanced Micro Devices, Inc. | Stress enhanced MOS transistor and methods for its fabrication |
JP5141029B2 (ja) * | 2007-02-07 | 2013-02-13 | 富士通セミコンダクター株式会社 | 半導体装置とその製造方法 |
US7544997B2 (en) | 2007-02-16 | 2009-06-09 | Freescale Semiconductor, Inc. | Multi-layer source/drain stressor |
US7553717B2 (en) * | 2007-05-11 | 2009-06-30 | Texas Instruments Incorporated | Recess etch for epitaxial SiGe |
US7736957B2 (en) * | 2007-05-31 | 2010-06-15 | Freescale Semiconductor, Inc. | Method of making a semiconductor device with embedded stressor |
US7737498B2 (en) * | 2008-05-07 | 2010-06-15 | International Business Machines Corporation | Enhanced stress-retention silicon-on-insulator devices and methods of fabricating enhanced stress retention silicon-on-insulator devices |
WO2010086154A1 (en) * | 2009-01-30 | 2010-08-05 | 5Advanced Micro Devices, Inc | In situ formed drain and source regions including a strain inducing alloy and a graded dopant profile |
US8299453B2 (en) | 2009-03-03 | 2012-10-30 | International Business Machines Corporation | CMOS transistors with silicon germanium channel and dual embedded stressors |
US8741725B2 (en) | 2010-11-10 | 2014-06-03 | International Business Machines Corporation | Butted SOI junction isolation structures and devices and method of fabrication |
-
2010
- 2010-11-10 US US12/943,084 patent/US8741725B2/en active Active
-
2011
- 2011-11-10 GB GB1306404.3A patent/GB2497259B/en not_active Expired - Fee Related
- 2011-11-10 JP JP2013538873A patent/JP2014500621A/ja not_active Ceased
- 2011-11-10 CN CN201180053813.1A patent/CN103210493B/zh active Active
- 2011-11-10 WO PCT/US2011/060084 patent/WO2012064912A2/en active Application Filing
- 2011-11-10 DE DE112011103730.9T patent/DE112011103730B4/de active Active
-
2014
- 2014-03-25 US US14/224,384 patent/US9105718B2/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH07335888A (ja) * | 1994-06-13 | 1995-12-22 | Samsung Electron Co Ltd | シリコンオンインシュレータトランジスタ |
US5683934A (en) * | 1994-09-26 | 1997-11-04 | Motorola, Inc. | Enhanced mobility MOSFET device and method |
US6495402B1 (en) * | 2001-02-06 | 2002-12-17 | Advanced Micro Devices, Inc. | Semiconductor-on-insulator (SOI) device having source/drain silicon-germanium regions and method of manufacture |
US20040094802A1 (en) * | 2001-12-10 | 2004-05-20 | Hynix Semiconductor Inc. | Semiconductor device and method of forming the same |
US20040026746A1 (en) * | 2002-08-09 | 2004-02-12 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
CN1741277A (zh) * | 2004-08-27 | 2006-03-01 | 株式会社瑞萨科技 | 半导体装置及其制造方法 |
US20090026552A1 (en) * | 2007-07-27 | 2009-01-29 | Da Zhang | Method for forming a transistor having gate dielectric protection and structure |
US20090256201A1 (en) * | 2008-04-10 | 2009-10-15 | Advanced Micro Devices, Inc. | Metal oxide semiconductor transistor with reduced gate height, and related fabrication methods |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105097520A (zh) * | 2014-05-04 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
CN105097520B (zh) * | 2014-05-04 | 2018-09-07 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
CN108695161A (zh) * | 2017-04-07 | 2018-10-23 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
CN109950314A (zh) * | 2017-12-21 | 2019-06-28 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其制造方法 |
CN109950314B (zh) * | 2017-12-21 | 2023-01-20 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其制造方法 |
CN112204459A (zh) * | 2018-02-27 | 2021-01-08 | 洛克利光子有限公司 | 电吸收调制器 |
Also Published As
Publication number | Publication date |
---|---|
US8741725B2 (en) | 2014-06-03 |
US20140203359A1 (en) | 2014-07-24 |
WO2012064912A3 (en) | 2012-07-19 |
GB201306404D0 (en) | 2013-05-22 |
GB2497259A (en) | 2013-06-05 |
US20120112280A1 (en) | 2012-05-10 |
DE112011103730T5 (de) | 2013-09-26 |
US9105718B2 (en) | 2015-08-11 |
WO2012064912A2 (en) | 2012-05-18 |
CN103210493B (zh) | 2016-01-06 |
JP2014500621A (ja) | 2014-01-09 |
DE112011103730B4 (de) | 2016-06-09 |
GB2497259B (en) | 2013-12-11 |
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