CN103178842B - A kind of phaselocked loop signal source with ECL phase discriminator and generation method thereof - Google Patents
A kind of phaselocked loop signal source with ECL phase discriminator and generation method thereof Download PDFInfo
- Publication number
- CN103178842B CN103178842B CN201110431636.8A CN201110431636A CN103178842B CN 103178842 B CN103178842 B CN 103178842B CN 201110431636 A CN201110431636 A CN 201110431636A CN 103178842 B CN103178842 B CN 103178842B
- Authority
- CN
- China
- Prior art keywords
- signal
- level
- frequency
- output
- pecl
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 72
- 230000003321 amplification Effects 0.000 claims description 6
- 230000001808 coupling Effects 0.000 claims description 6
- 238000010168 coupling process Methods 0.000 claims description 6
- 238000005859 coupling reaction Methods 0.000 claims description 6
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 4
- 238000001914 filtration Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 229920000729 poly(L-lysine) polymer Polymers 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003111 delayed Effects 0.000 description 1
- 235000005035 ginseng Nutrition 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006011 modification reaction Methods 0.000 description 1
- 230000003071 parasitic Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
- 230000002194 synthesizing Effects 0.000 description 1
Abstract
The present invention relates to field tests, a kind of phaselocked loop signal source with ECL phase discriminator and generation method thereof, wherein signal source includes that reference clock unit is for providing reference clock signal；ECL phase discriminator, receive the first level conversion unit and transmit the reference clock signal of the PECL level come, output signal with second electrical level converting unit transmits the change through scaling down processing come, sends the PECL level signal comprising phase information of two paths of signals to the 3rd level conversion unit；3rd level conversion unit by the PECL level conversion comprising phase information by meeting the level signal that output unit is used；Output unit is according to the frequency signal of phase information exporting change.By the embodiment of the present invention, the level translator by ECL phase discriminator with its co-ordination can improve the phase demodulation frequency of signal source, such that it is able to reduce the phase noise of signal source further.
Description
Technical field
The present invention relates to field tests, a kind of phaselocked loop signal source with ECL phase discriminator and generation method thereof.
Background technology
Phase Lock Technique is the most conventional method accurately determining frequency, and application is more extensive, the requirement to performance simultaneously
More and more higher.As the major part of frequency synthesis, the phase noise of phaselocked loop also becomes a very important index,
In transmission equipment, it can determine the purity of frequency spectrum of output signal；In reception equipment, it is affect receiving sensitivity one
Individual factor.
In the loop bandwidth of phaselocked loop, the phase noise of reference clock is affect pll output signal phase noise one
Principal element, in the case of the phase noise of reference does not has influence on noise floor, the phase noise of output can be the phase of reference
Position noise penalty 20lgN, phase demodulation frequency is the highest, and frequency dividing ratio N is the least, so in-band phase noise is the best.
Fig. 1 is the phase-locked loop structures figure that prior art intermediate frequency spectrum analyser DSA1030 uses.This phaselocked loop is occurred by reference clock
Device 101, phase discriminator 102, electric charge pump 103, low pass filter (LPF) 104, voltage controlled oscillator 105, frequency division module 106
Deng part composition.In this scheme, phase demodulation frequency is 10MHz, and common CMOS technology phase demodulation selected by phase discriminator, defeated
Entering output is all CMOS level.Electric charge pump 103 is by controlling diode break-make realization switch, carrying out discharge and recharge, phase discriminator
The CMOS level of output can be directly as the switching signal of electric charge pump.
Although it is fairly simple that the program realizes circuit, but phase demodulation frequency can not be too high, phase demodulation frequency more than 20MHz time the most not
Can normal tracking lock.And phase demodulation frequency is the lowest, the phase noise caused in phase locking frequency multiplying deteriorates the most.
For radio-frequency signal source, phase noise is one of its very important technical specification, and energy is being pursued in each factory commercial city
The equipment of more preferable noiseproof feature is provided.And the most effectively provide phase demodulation frequency high in prior art thus reduce signal phase and make an uproar
The scheme of sound.
Summary of the invention
The embodiment of the present invention is in order to solve above-mentioned technical problem, it is proposed that one has emitter-coupled logic integrated circuit phase discriminator
Phaselocked loop signal source and the method for generation, can improve the frequency of phase discriminator, reduce the noise of signal source.
Embodiments provide one and there is the phaselocked loop signal source of emitter-coupled logic integrated circuit (ECL) phase discriminator,
Including,
Including reference clock unit, the first level conversion unit, second electrical level converting unit, ECL phase discriminator, the 3rd level
Converting unit, output unit；
Described reference clock unit, is used for providing reference clock signal；
Described first level conversion unit, is positive emitter coupling logic level by the level conversion of described reference clock signal
PECL；
Described second electrical level converting unit, by the level of the frequency signal of the change of the described signal source output through frequency dividing
Be converted to PECL level；
Described ECL phase discriminator, receives described first level conversion unit and transmits the reference clock signal of the PECL level come,
Transmit, with described second electrical level converting unit, the signal of coming, obtain the phase contrast of two paths of signals, phase information will be comprised
PECL level signal send described 3rd level conversion unit to；
Described 3rd level conversion unit, is converted to meet described by the described PECL level signal comprising phase information
The level signal comprising phase information that output unit uses；
Described output unit, according to the frequency signal of the described level signal exporting change comprising phase information.
A kind of phaselocked loop signal source with emitter-coupled logic integrated circuit phase discriminator described according to embodiments of the present invention
One further aspect, described output unit farther includes, electric charge pump, loop filter, voltage controlled oscillator, frequency dividing
Module；
Described electric charge pump, according to described 3rd level conversion unit output the level signal comprising phase information to described
Loop filter carries out discharge and recharge；
Described loop filter, produces one according to described phase information and controls voltage signal；
Described voltage controlled oscillator, according to the frequency signal of described control voltage signal exporting change；
Described frequency division module, is connected between described voltage controlled oscillator and second electrical level converting unit, is believed by described output frequency
Number frequency reducing, sends described second electrical level converting unit to.
A kind of phaselocked loop signal source with emitter-coupled logic integrated circuit phase discriminator described according to embodiments of the present invention
Another further aspect, also includes amplification module between described voltage controlled oscillator and described frequency division module or divides mould in advance
Block, for carrying out power amplification or frequency reducing to the output frequency signal of described voltage controlled oscillator.
A kind of phaselocked loop signal source with emitter-coupled logic integrated circuit phase discriminator described according to embodiments of the present invention
Another further aspect, described first level conversion unit and second electrical level converting unit use and are output as PECL level
Logical device.
A kind of phaselocked loop signal source with emitter-coupled logic integrated circuit phase discriminator described according to embodiments of the present invention
Another further aspect, described first level conversion unit and second electrical level converting unit are ECL NAND gate, nor gate
Or comparator.
A kind of phaselocked loop signal source with emitter-coupled logic integrated circuit phase discriminator described according to embodiments of the present invention
Another further aspect, when described first level conversion unit and second electrical level converting unit are comparator, when described
The voltage of input signal is more than comparing voltage, then output PECL high level, when the voltage of described input signal is less than described comparison
During voltage, then output PECL low level, the described voltage that compares is set to the dc-bias of applied signal voltage.
A kind of phaselocked loop signal source with emitter-coupled logic integrated circuit phase discriminator described according to embodiments of the present invention
Another further aspect, when the first level conversion unit uses comparator, input signal is reference clock signal, when
When second electrical level converting unit uses comparator, input signal is the output frequency signal after frequency dividing.
The embodiment of the present invention additionally provides a kind of signal generating method, is applied to have emitter-coupled logic integrated circuit ECL mirror
The phaselocked loop signal source of phase device, including,
Generate reference clock signal；
By the level conversion of described reference clock signal for having positive emitter coupling logic level PECL；
It is that there is PECL level by the level conversion of the frequency signal of the change of the described signal source output through frequency dividing
Signal；
According to the described reference clock signal with PECL level and the described output frequency signal through level conversion,
To the phase contrast of two paths of signals, output comprises the PECL level signal of phase information；
The described PECL level signal comprising phase information is converted to meet output uses comprises phase information
Level signal；
Frequency signal according to the level signal exporting change comprising phase information.
Another further aspect of a kind of signal generating method described according to embodiments of the present invention, according to comprising phase
The frequency signal of the level signal exporting change of potential difference information also includes, according to comprising the level signal of phase information,
Loop filter carries out discharge and recharge, and described loop filter produces one according to described phase information and controls voltage signal,
Frequency signal according to described control voltage signal exporting change.
Another further aspect of a kind of signal generating method described according to embodiments of the present invention, will be through dividing
The level conversion of output frequency signal of described signal source be to have in the signal of PECL level also to include, amplify described
The power of the output frequency signal of voltage controlled oscillator, then carry out divide operation, or the frequency that described voltage controlled oscillator is exported
Signal carries out pre-frequency dividing, reduces the frequency of described output frequency signal.
By the embodiment of the present invention, the level translator by ECL phase discriminator with its co-ordination can improve signal source
Phase demodulation frequency, such that it is able to reduce the phase noise of signal source further.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing skill
In art description, the required accompanying drawing used is briefly described, it should be apparent that, the accompanying drawing in describing below is only the present invention
Some embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to root
Other accompanying drawing is obtained according to these accompanying drawings.
Fig. 1 is the phase-locked loop structures figure that in prior art, DSA1030 uses；
Fig. 2 show embodiment of the present invention one and has the phaselocked loop letter of emitter-coupled logic integrated circuit (ECL) phase discriminator
The structural representation in number source；
Fig. 3 show a kind of phaselocked loop signal source with ECL phase discriminator of the embodiment of the present invention and generates the flow chart of method；
Fig. 4 show the structural representation that embodiment of the present invention another kind has the phaselocked loop signal source of ECL phase discriminator；
Fig. 5 a is the structural representation of embodiment of the present invention level conversion unit 402；
Fig. 5 b is the oscillogram of embodiment of the present invention level conversion unit 402 input and output signal；
Fig. 6 is the structural representation of embodiment of the present invention level conversion unit 409.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clearly and completely
Describe, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments.Based on this
Embodiment in bright, the every other reality that those of ordinary skill in the art are obtained under not making creative work premise
Execute example, broadly fall into the scope of protection of the invention.
It is illustrated in figure 2 embodiment of the present invention one and there is the phaselocked loop letter of emitter-coupled logic integrated circuit (ECL) phase discriminator
The structural representation in number source.
Including reference clock unit 201, the first level conversion unit 202, second electrical level converting unit 203, ECL phase discriminator 204,
3rd level conversion unit 205, output unit 206.
Described reference clock unit 201 provides reference clock signal.
Described first level conversion unit 202, is positive emitter coupling logic level by the level conversion of described reference clock signal
(PECL)。
Described second electrical level converting unit 203, by the frequency signal of the change of the described signal source output through frequency dividing
Level conversion is for having PECL level.
Described ECL phase discriminator 204, receives described first level conversion unit 202 and transmits the ginseng with PECL level of coming
Examine clock signal, and described second electrical level converting unit 203 transmit the signal of coming, and obtains the phase contrast of two paths of signals,
Send the PECL level signal comprising phase information to described 3rd level conversion unit 205.
Described 3rd level conversion unit 205, the described PECL level conversion comprising phase information is described for meeting
What output unit 206 was used comprises the level signal of phase information.
Described output unit 206, according to the frequency signal of the described level signal exporting change comprising phase information.
Wherein, the frequency signal of the change of output unit output is exactly the frequency signal of the change that described signal source exports.
Wherein, described output unit 206 farther includes, electric charge pump, according to described 3rd level conversion unit 205 output
The level signal comprising phase information carries out discharge and recharge to described loop filter.Wherein, loop filter is entered by electric charge pump
Row discharge and recharge is to carry out according to the level signal comprising phase information, such as, when the level signal comprising phase contrast is height
During level, described loop filter is charged, when the level signal comprising phase information is low level, to described
Loop filter discharges.
Loop filter, produces one according to described phase information and controls voltage signal, send voltage controlled oscillator to.Described
Loop filter also filters the high fdrequency component controlled in voltage signal and noise, takes the average weight of voltage signal.
Described voltage controlled oscillator, according to the described frequency signal controlling voltage signal exporting change comprising phase information.
Also include frequency division module, be connected between described voltage controlled oscillator and second electrical level converting unit 203, by described output
Frequency signal frequency reducing, sends described second electrical level converting unit 203 to.When using the frequency division module with the output of PECL level
Time, second electrical level converting unit 203 can be save, so can reduce circuit area, cost-effective.
Amplification module or pre-frequency division module can also be included, in order to extend between described voltage controlled oscillator and described frequency division module
The frequency range of application voltage controlled oscillator and amplitude range.Wherein amplification module is for amplifying the letter of described voltage controlled oscillator output
Number power, the output frequency value of pre-frequency division module is the 1/M of voltage controlled oscillator output frequency value, and M is the frequency dividing of pre-frequency division module
Ratio, the output of voltage controlled oscillator inputs to frequency division module after pre-frequency division module again, so needs frequency division module can work
Big frequency reduces to the 1/M of voltage controlled oscillator maximum output frequency, reduces the requirement to the peak frequency that frequency division module can work.
Wherein said ECL phase discriminator 204 is by the phase discriminator of ECL circuit realiration, replaces traditional transistor-transistor logic electricity
Road (TTL) logic, this ECL phase discriminator logic swing is less, when circuit is from a kind of status transition to another kind of state,
The discharge and recharge time of parasitic capacitance will be reduced.
Described first level conversion unit 202 and second electrical level converting unit 203 can use the logic being output as PECL level
Device, such as comparator, ECL NAND gate, nor gate etc. realizes level conversion.
When using described comparator, when the voltage of described input signal is more than comparing voltage, then output PECL high level is (i.e.
Control electric charge pump loop filter is charged), when described input signal voltage less than described compare voltage time, the most defeated
Going out PECL low level (i.e. controlling electric charge pump to discharge loop filter), the described voltage that compares could be arranged to input signal electricity
The dc-bias of pressure.Wherein, when the first level conversion unit 202 uses comparator, input signal is reference clock letter
Number, when second electrical level converting unit 203 uses comparator, input signal is the output frequency signal after frequency dividing.
Described tertiary voltage converting unit 205 changes the level signal comprising phase information of described ECL phase discriminator 204 output,
The level signal comprising phase information that described ECL phase discriminator 204 exports is converted to control two single-ended controls of electric charge pump
Signal processed.
Pass through above-described embodiment, it is possible to achieve the phase demodulation frequency of frequency synthesizer gets a promotion, such as, can be more than 150MHz,
The phase noise optimizing PLL there is great beneficial effect.
It is illustrated in figure 3 a kind of phaselocked loop signal source with ECL phase discriminator of the embodiment of the present invention and generates the flow chart of method.
Including step 301, generate reference clock signal.
Step 302, by the level conversion of described reference clock signal for having positive emitter coupling logic level (PECL).
Step 303, by the level conversion of the frequency signal of the change of the described signal source output through frequency dividing for having
The signal of PECL level.
Step 304, according to the described reference clock signal with PECL level and the described output frequency through level conversion
Rate signal, obtains the phase contrast of two paths of signals, and output comprises the PECL level signal of phase information.
Step 305, is converted to the described PECL level signal comprising phase information to meet that output uses comprises phase
The level signal of potential difference information.
Step 306, according to the frequency signal of the level signal exporting change comprising phase information.
Farther include in described step 306, according to comprising the level signal of phase information, loop filter is carried out
Discharge and recharge, described loop filter produces one according to described phase information and controls voltage signal, after described conversion
Control voltage signal and control the change of output frequency signal.
In described step 303, in the output frequency signal of described signal source is divided, it is also possible to include amplifying
The signal power of described voltage controlled oscillator output frequency signal, then carry out divide operation, or described voltage controlled oscillator is exported
Frequency signal carry out pre-frequency dividing, reduce the frequency signal of described output.
Pass through above-described embodiment, it is possible to achieve the phase demodulation frequency of frequency synthesizer gets a promotion, to the phase noise optimizing PLL
There is great beneficial effect.
It is illustrated in figure 4 the structural representation that embodiment of the present invention another kind has the phaselocked loop signal source of ECL phase discriminator.
Including reference clock unit 401, level conversion unit 402, ECL phase discriminator 403, level conversion unit 404, electric charge
Pump 405, loop filter 406, voltage controlled oscillator 407, frequency divider 408, level conversion unit 409, pre-divider 410.
Described reference clock unit 401 provides the reference clock signal f1 of phase demodulation.
The level conversion of reference clock signal f1 is to have the signal fr of PECL level, wherein level by level conversion unit 402
Converting unit 402 can use comparator circuit to realize this level conversion unit 402 as shown in Figure 5 a, and described reference clock is believed
Number f1 is sinusoidal wave, utilizes level conversion unit 402 that sine wave is converted to PECL level, uses for ECL phase discriminator 403,
In fig 5 a, reference clock signal f1 inputs from the position 2 of comparator 501；Relatively voltage is accessed by the position 1 of comparator 501；
Position 3 is the final output of comparator 501, is the square-wave signal meeting PECL level.The input of comparator 501 each position,
As shown in Figure 5 b, in Fig. 5 b, 2 is reference clock signal f1 input waveform to signal output waveform, for sine wave；1 for the most electric
Pressure, for constant DC voltage, comparing voltage value is set to the dc-bias V ' of reference clock signal input；3 for comparing
The output of device 501, the instantaneous value when 2, more than when comparing voltage, exports PECL high level VH, the instantaneous value when 2 is less than the most electric
During pressure, export PECL low level VL.Can also use ECL NAND gate in other embodiments, nor gate etc. realizes level and turns
Change the level conversion function of unit 402.
ECL phase discriminator 403, for comparison reference clock fr and voltage controlled oscillator 407 through the phase place of divided signal fv, phase
Position control information is included in the PECL low and high level of its output and embodies, and such as output high level then represents reference clock fr's
The phase place of phase place advanced divided signal fv, low level represents the phase place of the delayed phase divided signal fv of reference clock fr.
This ECL phase discriminator 403 have employed ECL circuit realiration, replaces traditional transistor-transistor logic circuit (TTL) logic,
Utilize ECL level rise and fall time short, the feature that conversion speed is fast, can realization high phase comparison frequency phase demodulation, change greatly
It is apt to the phase noise of radio-frequency signal source output signal.
Wherein, owing to after the divided device of voltage controlled oscillator 407 408, the signal f2 of output is sinusoidal wave, and signal amplitude can basis
The difference of frequency dividing ratio has difference, frequency dividing ratio increase can cause the reduction of amplitude output signal, and this signal amplitude can not meet ECL
The requirement of phase discriminator 403 incoming level, needs to add level conversion unit 404 between frequency divider 408 and ECL phase discriminator 403.
Level conversion unit 404 can use the structure of such as Fig. 5 a identical with level conversion unit 402, does not repeats them here.
After relatively voltage is set to frequency divider 408 frequency dividing, output signal is through every directly, and the DC offset voltage value after biasing is the most right
In different frequency dividing ratio situations, even if amplitude output signal is different, uses and same compare voltage ratio relatively, also do not interfere with ratio
The correctness of relatively output signal, so can ensure that the level being input to ECL phase discriminator 403 is PECL level.
Such as: the f2 after frequency dividing is the sinusoidal signal of 0-0.8V, after AC coupled biases (bias voltage V ' is set to 1.5V),
At 2, input is the sinusoidal signal of 1.1-1.9V, and comparing voltage at 1 is set to 1.5V, then when at 2, input is more than 1.5V, 3
Place is output as 2.3V, and at 2, input is output as 1.9V when being less than 1.5V at 3, is output as the side with ECL logic level at 3
Ripple signal.
Comprising two switches in electric charge pump 405, two single-ended control signals control two switches respectively.Synchronization the two
Single-ended control signal level is contrary, one shutoff of one conducting of i.e. two switches, the turn-on and turn-off switched by control,
Loop filter 406 it is charged or discharges, thus the level signal comprising phase information be converted to and comprise phase contrast
The voltage signal of information.
Wherein, between electric charge pump 405 and ECL phase discriminator 403, also there is level conversion unit 409, if ECL phase discriminator 403
Being output as two groups of differential signals, each of which group differential signal is contrary two signals, ECL phase discriminator 403 output level
The amplitude of oscillation is 0.4V, i.e. high level 2.3V, low level 1.9V, uses these two groups of differential signals to be used as to control electric charge pump 405 and switchs
Work, needs to constitute two single-ended control signals after level conversion unit 409, and control signal high level is 1.5V, low
Level is 0 (at other is may be for other value in embodiment, the most only for citing), and described level conversion unit 409 is main
Complete two functions: one is that two groups of differential signals are converted into two single-ended signals；Another has been the conversion of level value,
The differential amplifier circuit with current source is used to complete this function in the present embodiment, for each group of differential signal, electricity
Flat converting unit 409 can as shown in Figure 6, and one group of differential signal of ECL phase discriminator 403 exports respectively as Ui1And Ui2Input,
Uo1Export single-ended control signal U in road as electric charge pump 405o1=I1×R1, single-ended control signal U in another roado2Can be by another
One level conversion unit 409 obtains from the differential signal of another group ECL phase discriminator 403 output.Described phase information exists
The low and high level of the differential signal of ECL phase discriminator output is embodied, such as, wherein high level of charge pump pair during high level
Loop filter 406 is charged, and during low level, loop filter 406 is discharged by electric charge pump.Described loop filter 406,
According to the electric charge pump change in voltage brought to its discharge and recharge, be converted to phase information control voltage signal, send to
Voltage controlled oscillator 407.
Described voltage controlled oscillator 407 controls the change of output frequency signal fo according to the voltage signal that controls after described conversion.
Output frequency signal fo is divided by described frequency divider 408, reduces the frequency of output frequency signal, is then input to
Level conversion unit 404.Wherein, if frequency divider 408 can directly export the signal of PECL level, it is possible to omit level
Converting unit 404, such that it is able to reduce circuit area, cost-effective.
Pre-divider 410 or amplifier (not shown) can also be included between voltage controlled oscillator 407 and described frequency divider 408,
This pre-divider 410 is for reducing the frequency of described output frequency signal, and output frequency value is voltage controlled oscillator 407 output frequency
The frequency dividing ratio that 1/M, M are pre-divider 410 of value, the output of voltage controlled oscillator 407 inputs to after pre-divider 410 again
Frequency divider 408, so needs frequency divider 408 peak frequency that can work to reduce to the 1/M of the maximum output frequency of voltage controlled oscillator 407,
Reduce the requirement to the peak frequency that frequency divider 408 can work.Described amplifier can increase the power of output frequency signal,
When the frequency signal amplitude of voltage controlled oscillator output is less, it is impossible to when meeting frequency divider to the requirement of input signal amplitude, then need
Amplifier is wanted to amplify the power of output frequency signal.
By the embodiment of the present invention, the level translator by ECL phase discriminator with its co-ordination can improve signal source
Phase demodulation frequency, such that it is able to reduce the phase noise of signal source further.
Above-described detailed description of the invention, has been carried out the purpose of the present invention, technical scheme and beneficial effect the most in detail
Illustrate, be it should be understood that the detailed description of the invention that the foregoing is only the present invention, be not intended to limit the present invention
Protection domain, all within the spirit and principles in the present invention, any modification, equivalent substitution and improvement etc. done, all should wrap
Within being contained in protection scope of the present invention.
Claims (10)
1. a phaselocked loop signal source with emitter-coupled logic integrated circuit ECL phase discriminator, it is characterised in that
Including reference clock unit, the first level conversion unit, second electrical level converting unit, ECL phase discriminator, the 3rd level
Converting unit, output unit；
Described reference clock unit, is used for providing reference clock signal；
Described first level conversion unit, is positive emitter coupling logic level by the level conversion of described reference clock signal
PECL；
Described second electrical level converting unit, by the level of the frequency signal of the change of the described signal source output through frequency dividing
Be converted to PECL level；
Described ECL phase discriminator, receives described first level conversion unit and transmits the reference clock signal of the PECL level come,
Transmit, with described second electrical level converting unit, the signal of coming, obtain the phase contrast of two paths of signals, phase information will be comprised
PECL level signal send described 3rd level conversion unit to；
Described 3rd level conversion unit, is converted to meet described by the described PECL level signal comprising phase information
The level signal comprising phase information that output unit uses；
Described output unit, according to the frequency signal of the described level signal exporting change comprising phase information.
A kind of phaselocked loop signal source with emitter-coupled logic integrated circuit ECL phase discriminator the most according to claim 1,
It is characterized in that, described output unit farther includes, electric charge pump, loop filter, voltage controlled oscillator, frequency division module；
Described electric charge pump, according to described 3rd level conversion unit output the level signal comprising phase information to described
Loop filter carries out discharge and recharge；
Described loop filter, produces one according to described phase information and controls voltage signal；
Described voltage controlled oscillator, according to the frequency signal of described control voltage signal exporting change；
Described frequency division module, is connected between described voltage controlled oscillator and second electrical level converting unit, by the frequency signal of output
Frequency reducing, sends described second electrical level converting unit to.
A kind of phaselocked loop signal source with emitter-coupled logic integrated circuit ECL phase discriminator the most according to claim 2,
It is characterized in that, between described voltage controlled oscillator and described frequency division module, also include amplification module or pre-frequency division module, be used for
The output frequency signal of described voltage controlled oscillator is carried out power amplification or frequency reducing.
A kind of phaselocked loop signal source with emitter-coupled logic integrated circuit ECL phase discriminator the most according to claim 1,
It is characterized in that, described first level conversion unit and second electrical level converting unit use the logic device being output as PECL level
Part.
A kind of phaselocked loop signal source with emitter-coupled logic integrated circuit ECL phase discriminator the most according to claim 4,
It is characterized in that, described first level conversion unit and second electrical level converting unit are ECL NAND gate, nor gate or comparator.
A kind of phaselocked loop signal source with emitter-coupled logic integrated circuit ECL phase discriminator the most according to claim 5,
It is characterized in that, when described first level conversion unit and second electrical level converting unit are comparator, when the electricity of input signal
Pressure more than comparing voltage, then output PECL high level, when described input signal voltage less than described compare voltage time, the most defeated
Going out PECL low level, the described voltage that compares is set to the dc-bias of applied signal voltage.
A kind of phaselocked loop signal source with emitter-coupled logic integrated circuit ECL phase discriminator the most according to claim 6,
It is characterized in that, when the first level conversion unit uses comparator, input signal is reference clock signal, works as second electrical level
When converting unit uses comparator, input signal is the output frequency signal after frequency dividing.
8. a signal generating method, is applied to the phaselocked loop signal source with emitter-coupled logic integrated circuit ECL phase discriminator,
It is characterized in that including,
Generate reference clock signal；
By the level conversion of described reference clock signal for having positive emitter coupling logic level PECL；
It is that there is PECL level by the level conversion of the frequency signal of the change of the described signal source output through frequency dividing
Signal；
Reference clock signal according to the described PECL of having level and the described frequency signal with PECL level, obtain two
The phase contrast of road signal, output comprises the PECL level signal of phase information；
The described PECL level signal comprising phase information is converted to meet output uses comprises phase information
Level signal；
Frequency signal according to the level signal exporting change comprising phase information.
A kind of signal generating method the most according to claim 8, it is characterised in that according to comprising phase information
The frequency signal of level signal exporting change also includes, according to comprising the level signal of phase information, to loop filtering
Device carries out discharge and recharge, and described loop filter produces one according to described phase information and controls voltage signal, according to described control
The frequency signal of voltage signal exporting change processed.
A kind of signal generating method the most according to claim 8, it is characterised in that by the described letter through frequency dividing
The level conversion of the output frequency signal in number source is to have in the signal of PECL level also to include, amplifies voltage controlled oscillator
The power of output frequency signal, then carry out divide operation, or the frequency signal of voltage controlled oscillator output is carried out pre-frequency dividing,
Reduce the frequency of described output frequency signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110431636.8A CN103178842B (en) | 2011-12-21 | A kind of phaselocked loop signal source with ECL phase discriminator and generation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110431636.8A CN103178842B (en) | 2011-12-21 | A kind of phaselocked loop signal source with ECL phase discriminator and generation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103178842A CN103178842A (en) | 2013-06-26 |
| CN103178842B true CN103178842B (en) | 2016-12-14 |
Family
ID=
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2299423Y (en) * | 1997-05-12 | 1998-12-02 | 中国科学院陕西天文台 | VHF frequency synthesizer |
| CN101807920A (en) * | 2010-03-10 | 2010-08-18 | 东南大学 | Self-adaptive frequency calibration frequency synthesizer |
| CN101854173A (en) * | 2010-06-11 | 2010-10-06 | 西安电子科技大学 | InGaP/GaAs HBT (Heterojunction Bipolar Transistor) super-high-speed frequency-halving circuit based on ECL (Emitter-Coupled Logic) |
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2299423Y (en) * | 1997-05-12 | 1998-12-02 | 中国科学院陕西天文台 | VHF frequency synthesizer |
| CN101807920A (en) * | 2010-03-10 | 2010-08-18 | 东南大学 | Self-adaptive frequency calibration frequency synthesizer |
| CN101854173A (en) * | 2010-06-11 | 2010-10-06 | 西安电子科技大学 | InGaP/GaAs HBT (Heterojunction Bipolar Transistor) super-high-speed frequency-halving circuit based on ECL (Emitter-Coupled Logic) |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104113303B (en) | 50% duty ratio clock generation circuit | |
| US20120213268A1 (en) | Locking System and Method Thereof | |
| CN101621297B (en) | Detection method and circuit of frequency lock of phase lock loop | |
| CN100558156C (en) | Be applicable to the clock generation circuit in low dithering of digital TV in high resolution | |
| CN103684438A (en) | Delay locked loop | |
| CN107707253B (en) | Self-detection common time base circuit, system and method based on arbitrary variable reference source | |
| US7417477B2 (en) | PLL circuit | |
| CN106603070A (en) | Phase-locked loop low in stray and quick in locking | |
| CN102710257B (en) | Frequency locking method, voltage-controlled oscillator and frequency generating unit | |
| CN107623521A (en) | A kind of pll clock generator | |
| CN111953339B (en) | Phase-locked loop fast locking frequency discrimination circuit | |
| CN204465511U (en) | A kind of program control frequency doubling device based on PLL phase-locked loop and frequency divider | |
| CN101888244B (en) | Low-power consumption phase-locked loop circuit | |
| CN102684684B (en) | Orthogonal clock generating circuit for multichannel forward clock high-speed serial interface | |
| CN102340308B (en) | Fractional-N frequency synthesizer | |
| CN204031123U (en) | A kind ofly be applied to the phase discriminator based on Sampling techniques in phase-locked loop and charge pump circuit | |
| TWI434168B (en) | Clock and data recovery circuit | |
| CN103178842B (en) | A kind of phaselocked loop signal source with ECL phase discriminator and generation method thereof | |
| CN111147071A (en) | Proportional path gain regulator applied to clock data recovery circuit | |
| CN105743514A (en) | High-speed serializer with feedback parallel data interface | |
| CN102931981A (en) | Ultra-low power consumption phase locked loop circuit | |
| CN203608181U (en) | Frequency synthesizer | |
| CN205490493U (en) | High speed serialization ware with feedback parallel data interface | |
| CN106505997A (en) | clock and data recovery circuit and clock and data recovery method | |
| CN202841098U (en) | High-speed input/output interface and receiving circuit thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant |