CN103178842A - Phase-locked loop signal source with emitter coupled logic (ECL) phase discriminator and generation method thereof - Google Patents
Phase-locked loop signal source with emitter coupled logic (ECL) phase discriminator and generation method thereof Download PDFInfo
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Abstract
The invention relates to the field of testing, in particular to a phase-locked loop signal source with an emitter coupled logic (ECL) phase discriminator and a generation method thereof. The signal source comprises a reference clock unit for providing reference clock signals and the ECL phase discriminator, wherein the ECL phase discriminator is used for receiving reference clock signals of a positive emitter coupled logic (PECL) level transmitted by a first level conversion unit and variable output signals undergone frequency division processing and transmitted by a second level conversion unit and transmitting PECL level signals containing phase difference information of two paths of signals to a third level conversion unit; the third level conversion unit converts PECL level comprising phase difference information into level signals in accordance with using of an output unit; and the output unit outputs variable frequency signals according to phase difference information. By means of an embodiment of the phase-locked loop signal source with the ECL phase discriminator, the phase discrimination frequency of the signal source can be improved through the ECL phase discriminator and the level converter working in coordination with the ECL phase discriminator, and phase noises of the signal source can be further reduced.
Description
Technical field
The present invention relates to field tests, especially a kind of phase-locked loop signal source and generation method thereof with ECL phase discriminator.
Background technology
Phase Lock Technique is the commonly used at present method of frequency of accurately determining, applies also more and more extensive, simultaneously also more and more higher to the requirement of performance.As the major part of frequency synthesis, the phase noise of phase-locked loop also becomes a very important index, and in transmitting apparatus, it can determine the spectral purity of output signal; In receiving equipment, it is a factor that affects receiving sensitivity.
In the loop bandwidth of phase-locked loop, the phase noise of reference clock is a principal element that affects the pll output signal phase noise, in the situation that the phase noise of reference does not have influence on noise floor, the phase noise of output can worsen 20lgN to the phase noise of reference, phase demodulation frequency is higher, frequency dividing ratio N is less, so in-band phase noise is better.
Fig. 1 is the phase-locked loop structures figure that prior art intermediate frequency spectrum analyzer DSA1030 adopts.This phase-locked loop is by reference clock generator 101, phase discriminator 102, and charge pump 103, low pass filter (LPF) 104, voltage controlled oscillator 105, frequency division module 106 grades partly form.In this scheme, phase demodulation frequency is 10MHz, and phase discriminator has been selected common CMOS technology phase demodulation, and input and output are all the CMOS level.Charge pump 103 is to realize switch by controlling the diode break-make, discharged and recharged, the CMOS level of phase discriminator output can be directly as the switching signal of charge pump.
Although this scheme realizes that circuit is fairly simple, phase demodulation frequency can not be too high, normal tracking lock just when phase demodulation frequency is greater than 20MHz.And phase demodulation frequency is lower, the phase noise caused in phase locking frequency multiplying worsens more.
For radio-frequency signal source, phase noise is one of its very important technical indicator, and the equipment that better noiseproof feature can be provided is being pursued in each factory commercial city.Thereby and effectively do not provide phase demodulation frequency the high scheme that reduces the signal phase noise in prior art.
Summary of the invention
The embodiment of the present invention, in order to solve the problems of the technologies described above, has proposed a kind of phase-locked loop signal source and generation method thereof with emitter-coupled logic integrated circuit phase discriminator, can improve the frequency of phase discriminator, reduces the noise of signal source.
The embodiment of the present invention provides a kind of phase-locked loop signal source with emitter-coupled logic integrated circuit (ECL) phase discriminator, comprises,
Comprise the reference clock unit, the first level conversion unit, second electrical level converting unit, ECL phase discriminator, the 3rd level conversion unit, output unit;
Described reference clock unit, for providing reference clock signal;
Described the first level conversion unit is positive emitter coupling logic level PECL by the level conversion of described reference clock signal;
Described second electrical level converting unit, the level conversion of the frequency signal of the variation that will export through the described signal source of frequency division is the PECL level;
Described ECL phase discriminator, receive the reference clock signal of the PECL level that described the first level conversion unit sends, the signal sent with described second electrical level converting unit, obtain the phase difference of two paths of signals, the PECL level signal that will comprise phase information sends described the 3rd level conversion unit to;
Described the 3rd level conversion unit, be converted to the described PECL level signal that comprises phase information to meet the level signal that comprises phase information that described output unit is used;
Described output unit, according to the frequency signal of the described level signal exporting change that comprises phase information.
According to the described a kind of further aspect with phase-locked loop signal source of emitter-coupled logic integrated circuit phase discriminator of the embodiment of the present invention, described output unit further comprises, charge pump, loop filter, voltage controlled oscillator, frequency division module;
Described charge pump, discharged and recharged described loop filter according to the level signal that comprises phase information of described the 3rd level conversion unit output;
Described loop filter, produce one according to described phase information and control voltage signal;
Described voltage controlled oscillator, according to the frequency signal of described control voltage signal exporting change;
Described frequency division module, be connected between described voltage controlled oscillator and second electrical level converting unit, by described output frequency signal frequency reducing, sends described second electrical level converting unit to.
According to described a kind of another the further aspect with phase-locked loop signal source of emitter-coupled logic integrated circuit phase discriminator of the embodiment of the present invention, also comprise amplification module or pre-frequency division module between described voltage controlled oscillator and described frequency division module, for the output frequency signal to described voltage controlled oscillator, carry out power amplification or frequency reducing.
According to described a kind of another the further aspect with phase-locked loop signal source of emitter-coupled logic integrated circuit phase discriminator of the embodiment of the present invention, described the first level conversion unit and second electrical level converting unit adopt the logical device that is output as the PECL level.
According to described a kind of another the further aspect with phase-locked loop signal source of emitter-coupled logic integrated circuit phase discriminator of the embodiment of the present invention, described the first level conversion unit and second electrical level converting unit are ECL NAND gate, NOR gate or comparator.
According to described a kind of another the further aspect with phase-locked loop signal source of emitter-coupled logic integrated circuit phase discriminator of the embodiment of the present invention, when described the first level conversion unit and second electrical level converting unit are comparator, when the voltage of described input signal is greater than comparative voltage, export the PECL high level, when the voltage of described input signal is less than described comparative voltage, export the PECL low level, described comparative voltage is set to the dc-bias of applied signal voltage.
According to described a kind of another the further aspect with phase-locked loop signal source of emitter-coupled logic integrated circuit phase discriminator of the embodiment of the present invention, when the first level conversion unit adopts comparator, input signal is reference clock signal, when the second electrical level converting unit adopts comparator, input signal is the output frequency signal after frequency division.
The embodiment of the present invention also provides a kind of signal generating method, is applied to have the phase-locked loop signal source of emitter-coupled logic integrated circuit ECL phase discriminator, comprise,
The generating reference clock signal;
By the level conversion of described reference clock signal for thering is positive emitter coupling logic level PECL;
The level conversion of the frequency signal of the variation that will export through the described signal source of frequency division is the signal with PECL level;
According to described reference clock signal and the described output frequency signal through level conversion with PECL level, obtain the phase difference of two paths of signals, output packet is containing the PECL level signal of phase information;
The described PECL level signal that comprises phase information is converted to and meets the level signal that comprises phase information that output is used;
Frequency signal according to the level signal exporting change that comprises phase information.
Another further aspect according to the described a kind of signal generating method of the embodiment of the present invention, in the frequency signal of the level signal exporting change according to comprising phase information, also comprise, according to the level signal that comprises phase information, loop filter is discharged and recharged, described loop filter produces one according to described phase information and controls voltage signal, according to the frequency signal of described control voltage signal exporting change.
Another further aspect according to the described a kind of signal generating method of the embodiment of the present invention, to be also to comprise in thering is the signal of PECL level through the level conversion of the output frequency signal of the described signal source of frequency division, amplify the power of the output frequency signal of described voltage controlled oscillator, carry out again divide operation, perhaps the frequency signal of described voltage controlled oscillator output carried out to pre-frequency division, reduce the frequency of described output frequency signal.
By the embodiment of the present invention, can improve the phase demodulation frequency of signal source by the ECL phase discriminator with the level translator of its co-ordination, thereby can further reduce the phase noise of signal source.
The accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, below will the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the phase-locked loop structures figure that in prior art, DSA1030 adopts;
Figure 2 shows that a kind of structural representation with phase-locked loop signal source of emitter-coupled logic integrated circuit (ECL) phase discriminator of the embodiment of the present invention;
Figure 3 shows that the flow chart of the phase-locked loop signal source generation method of a kind of ECL of having phase discriminator of the embodiment of the present invention;
Figure 4 shows that embodiment of the present invention another kind has the structural representation of the phase-locked loop signal source of ECL phase discriminator;
The structural representation that Fig. 5 a is embodiment of the present invention level conversion unit 402;
The oscillogram that Fig. 5 b is embodiment of the present invention level conversion unit 402 input and output signals;
The structural representation that Fig. 6 is embodiment of the present invention level conversion unit 409.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Embodiment in bright based on this, those of ordinary skills, not making under the creative work prerequisite the every other embodiment obtained, belong to the scope of protection of the invention.
Be illustrated in figure 2 a kind of structural representation with phase-locked loop signal source of emitter-coupled logic integrated circuit (ECL) phase discriminator of the embodiment of the present invention.
Comprise reference clock unit 201, the first level conversion units 202, second electrical level converting unit 203, ECL phase discriminator 204, the three level conversion units 205, output unit 206.
Described reference clock unit 201 provides reference clock signal.
Described the first level conversion unit 202 is positive emitter coupling logic level (PECL) by the level conversion of described reference clock signal.
Described second electrical level converting unit 203, the level conversion of the frequency signal of the variation that will export through the described signal source of frequency division is for having the PECL level.
Described ECL phase discriminator 204, receive the reference clock signal with PECL level that described the first level conversion unit 202 sends, the signal sent with described second electrical level converting unit 203, obtain the phase difference of two paths of signals, the PECL level signal that will comprise phase information sends described the 3rd level conversion unit 205 to.
Described the 3rd level conversion unit 205 is to meet the level signal that comprises phase information that described output unit 206 is used by the described PECL level conversion that comprises phase information.
Described output unit 206, according to the frequency signal of the described level signal exporting change that comprises phase information.Wherein, the frequency signal of the variation of output unit output is exactly the frequency signal of the variation of described signal source output.
Wherein, described output unit 206 further comprises, charge pump is discharged and recharged described loop filter according to the level signal that comprises phase information of described the 3rd level conversion unit 205 outputs.Wherein, it is that the level signal that basis comprises phase information is carried out that charge pump is discharged and recharged loop filter, for example, when the level signal that comprises phase difference is high level, described loop filter is charged, when the level signal that comprises phase information is low level, described loop filter is discharged.
Loop filter, produce one according to described phase information and control voltage signal, sends voltage controlled oscillator to.Described loop filter also filtering is controlled high fdrequency component and the noise in voltage signal, and the average weight of signal is pressed in power taking.
Described voltage controlled oscillator, according to the frequency signal of the described control voltage signal exporting change that comprises phase information.
Also comprise frequency division module, be connected between described voltage controlled oscillator and second electrical level converting unit 203, by described output frequency signal frequency reducing, send described second electrical level converting unit 203 to.When employing has the frequency division module of PECL level output, can save second electrical level converting unit 203, can reduce circuit area like this, cost-saving.
Can also comprise amplification module or pre-frequency division module between described voltage controlled oscillator and described frequency division module, in order to frequency range and the amplitude range of expanded application voltage controlled oscillator.Wherein amplification module is for amplifying the signal power of described voltage controlled oscillator output, the 1/M that the output frequency value of pre-frequency division module is the voltage controlled oscillator output frequency value, the frequency dividing ratio that M is pre-frequency division module, the output of voltage controlled oscillator inputs to frequency division module after pre-frequency division module again, need like this frequency division module peak frequency of can working to reduce to the 1/M of the maximum output frequency of voltage controlled oscillator, reduced the requirement of the peak frequency that can work to frequency division module.
Wherein said ECL phase discriminator 204 is the phase discriminator of being realized by the ECL circuit, replace traditional transistor-transistor logic circuit (TTL) logic, this ECL phase discriminator logic swing is less, when circuit during from a kind of status transition to another kind of state, will reduce time that discharges and recharges of parasitic capacitance.
Described the first level conversion unit 202 and second electrical level converting unit 203 can adopt the logical device that is output as the PECL level, for example comparator, ECL NAND gate, and NOR gate etc. realize level conversion.
When adopting described comparator, when the voltage of described input signal is greater than comparative voltage, export PECL high level (controlling charge pump is charged to loop filter), when the voltage of described input signal is less than described comparative voltage, export PECL low level (controlling charge pump discharges to loop filter), described comparative voltage can be set to the dc-bias of applied signal voltage.Wherein, when the first level conversion unit 202 adopts comparator, input signal is reference clock signal, and when second electrical level converting unit 203 adopts comparator, input signal is the output frequency signal after frequency division.
The level signal that comprises phase information of described ECL phase discriminator 204 outputs of described tertiary voltage converting unit 205 conversion, be converted to by the level signal that comprises phase information of described ECL phase discriminator 204 outputs two single-ended control signals controlling charge pump.
By above-described embodiment, can realize that the phase demodulation frequency of frequency synthesizer gets a promotion, for example can be greater than 150MHz, the phase noise of optimizing PLL is had to great beneficial effect.
Be illustrated in figure 3 the flow chart of the phase-locked loop signal source generation method of a kind of ECL of having phase discriminator of the embodiment of the present invention.
Comprise step 301, the generating reference clock signal.
In described step 306, further comprise, according to the level signal that comprises phase information, loop filter is discharged and recharged, described loop filter produces one according to described phase information and controls voltage signal, controls the variation of output frequency signal according to the control voltage signal after described conversion.
In described step 303, at the output frequency signal to described signal source, carry out in frequency division, can also comprise the signal power of amplifying described voltage controlled oscillator output frequency signal, carry out again divide operation, perhaps the frequency signal of described voltage controlled oscillator output carried out to pre-frequency division, reduce the frequency signal of described output.
By above-described embodiment, can realize that the phase demodulation frequency of frequency synthesizer gets a promotion, the phase noise of optimizing PLL is had to great beneficial effect.
Be illustrated in figure 4 the structural representation that embodiment of the present invention another kind has the phase-locked loop signal source of ECL phase discriminator.
Comprise reference clock unit 401, level conversion unit 402, ECL phase discriminator 403, level conversion unit 404, charge pump 405, loop filter 406, voltage controlled oscillator 407, frequency divider 408, level conversion unit 409, pre-divider 410.
The reference clock signal f1 that described reference clock unit 401 provides phase demodulation to use.
Level conversion unit 402 is the signal fr with PECL level with reference to the level conversion of clock signal f1, wherein level conversion unit 402 can be as shown in Figure 5 a, adopt comparator circuit to realize this level conversion unit 402, described reference clock signal f1 is sinusoidal wave, utilize level conversion unit 402 that sine wave is converted to the PECL level, for ECL phase discriminator 403, use, in Fig. 5 a, reference clock signal f1 is from position 2 inputs of comparator 501; Comparative voltage is by position 1 access of comparator 501; Position 3 is the final output of comparator 501, is the square-wave signal that meets the PECL level.As shown in Figure 5 b, in Fig. 5 b, 2 for reference clock signal f1 input waveform, is sine wave for the input of comparator 501 each positions, signal output waveform; 1 is comparative voltage, is constant direct voltage, and comparing voltage value is set to the dc-bias V ' of reference clock signal input; 3 outputs that are comparator 501, when the instantaneous value when 2 is greater than comparative voltage, output PECL high level V
h, when the instantaneous value when 2 is less than comparative voltage, output PECL low level V
l.Can also use the ECL NAND gate in other embodiments, NOR gate etc. realize the level conversion function of level conversion unit 402.
ECL phase discriminator 403, for comparing the phase place of reference clock fr and voltage controlled oscillator 407 signal fv after frequency division, phase error information is included in the PECL low and high level of its output and embodies, for example export the phase place of signal fv after the leading frequency division of phase place that high level represents reference clock fr, low level represents the phase place of signal fv after the phase place hysteresis frequency division of reference clock fr.This ECL phase discriminator 403 has adopted the ECL circuit to realize, replace traditional transistor-transistor logic circuit (TTL) logic, utilize the ECL electrical level rising short fall time, the characteristics that conversion speed is fast, can realize using the high phase comparison frequency phase demodulation, improve greatly the phase noise of radio-frequency signal source output signal.
Wherein, the signal f2 exported after frequency divider 408 due to voltage controlled oscillator 407 is sinusoidal wave, and signal amplitude can have difference according to the difference of frequency dividing ratio, the frequency dividing ratio increase can cause reducing of amplitude output signal, this signal amplitude can not meet the requirement of ECL phase discriminator 403 incoming levels, need between frequency divider 408 and ECL phase discriminator 403, add level conversion unit 404.
Level conversion unit 404 can adopt the structure of Fig. 5 a for example identical with level conversion unit 402, does not repeat them here.Comparative voltage is set to after frequency divider 408 frequency divisions output signal through every directly, DC offset voltage value after biasing, like this for different frequency dividing ratio situations, even amplitude output signal difference, use same comparative voltage relatively, also can not affect the correctness of comparison output signal, the level that can guarantee like this to be input to ECL phase discriminator 403 is the PECL level.
For example: the sinusoidal signal that the f2 after frequency division is 0-0.8V, after the AC coupled biasing (bias voltage V ' is made as 1.5V), be input as the sinusoidal signal of 1.1-1.9V at 2 places, 1 place's comparative voltage is made as 1.5V, when the input of 2 places is greater than 1.5V, be output as 2.3V at 3 places, when the input of 2 places is less than 1.5V, at 3 places, be output as 1.9V, 3 places are output as the square-wave signal with ECL logic level.
Comprise two switches in charge pump 405, two single-ended control signals are controlled respectively two switches.These two single-ended control signal level of synchronization are contrary, i.e. shutoff of conducting of two switches, turn-on and turn-off by control switch, loop filter 406 is carried out to charge or discharge, and the level signal that will comprise thus phase information is converted to and the voltage signal that comprises phase information.
Wherein, also there is level conversion unit 409 between charge pump 405 and ECL phase discriminator 403, if ECL phase discriminator 403 is output as two groups of differential signals, wherein each group differential signal is two contrary signals, the amplitude of oscillation of ECL phase discriminator 403 output levels is 0.4V, be high level 2.3V, low level 1.9V, use these two groups of differential signals as controlling charge pump 405 switchs, need to after level conversion unit 409, form two single-ended control signals, the control signal high level is 1.5V, low level is that 0 (at other is may be worth for other in embodiment, here only for giving an example), described level conversion unit 409 mainly completes two functions: the one, convert two groups of differential signals to two single-ended signals, another has been the conversion of level value, adopt in the present embodiment the differential amplifier circuit with current source to complete this function, for each group differential signal, level conversion unit 409 can be as shown in Figure 6, and one group of differential signal output of ECL phase discriminator 403 is respectively as U
i1and U
i2input, U
o1output is as the charge pump 405 mono-single-ended control signal U in tunnel
o1=I
1* R
1, the single-ended control signal U in another road
o2can from the differential signal of another group ECL phase discriminator 403 outputs, obtain by another level conversion unit 409.Described phase information is embodied in the low and high level of the differential signal of ECL phase discriminator output, and for example, wherein the high level of charge pump is charged to loop filter 406 during high level, and during low level, charge pump is discharged to loop filter 406.Described loop filter 406, the change in voltage of bringing it discharged and recharged according to charge pump, be converted to the control voltage signal by phase information, sends voltage controlled oscillator 407 to.
Described voltage controlled oscillator 407 is controlled the variation of output frequency signal fo according to the control voltage signal after described conversion.
408 couples of output frequency signal fo of described frequency divider carry out frequency division, reduce the frequency of output frequency signal, then are input to level conversion unit 404.Wherein, if frequency divider 408 can directly be exported the signal of PECL level, just can omit level conversion unit 404, thereby can reduce circuit area, cost-saving.
Can also comprise pre-divider 410 or amplifier (not shown) between voltage controlled oscillator 407 and described frequency divider 408, this pre-divider 410 is for reducing the frequency of described output frequency signal, the 1/M that output frequency value is voltage controlled oscillator 407 output frequency value, the frequency dividing ratio that M is pre-divider 410, the output of voltage controlled oscillator 407 inputs to frequency divider 408 after pre-divider 410 again, need like this frequency divider 408 peak frequency of can working to reduce to the 1/M of voltage controlled oscillator 407 maximum output frequencies, reduced the requirement of the peak frequency that can work to frequency divider 408.Described amplifier can increase the power of output frequency signal, when the frequency signal amplitude of voltage controlled oscillator output is less, in the time of can not meeting frequency divider to the requiring of input signal amplitude, needs amplifier to amplify the power of output frequency signal.
By the embodiment of the present invention, can improve the phase demodulation frequency of signal source by the ECL phase discriminator with the level translator of its co-ordination, thereby can further reduce the phase noise of signal source.
Above-described embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only the specific embodiment of the present invention; the protection range be not intended to limit the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. the phase-locked loop signal source with emitter-coupled logic integrated circuit ECL phase discriminator, is characterized in that,
Comprise the reference clock unit, the first level conversion unit, second electrical level converting unit, ECL phase discriminator, the 3rd level conversion unit, output unit;
Described reference clock unit, for providing reference clock signal;
Described the first level conversion unit is positive emitter coupling logic level PECL by the level conversion of described reference clock signal;
Described second electrical level converting unit, the level conversion of the frequency signal of the variation that will export through the described signal source of frequency division is the PECL level;
Described ECL phase discriminator, receive the reference clock signal of the PECL level that described the first level conversion unit sends, the signal sent with described second electrical level converting unit, obtain the phase difference of two paths of signals, the PECL level signal that will comprise phase information sends described the 3rd level conversion unit to;
Described the 3rd level conversion unit, be converted to the described PECL level signal that comprises phase information to meet the level signal that comprises phase information that described output unit is used;
Described output unit, according to the frequency signal of the described level signal exporting change that comprises phase information.
2. a kind of phase-locked loop signal source with emitter-coupled logic integrated circuit ECL phase discriminator according to claim 1, is characterized in that, described output unit further comprises, charge pump, loop filter, voltage controlled oscillator, frequency division module;
Described charge pump, discharged and recharged described loop filter according to the level signal that comprises phase information of described the 3rd level conversion unit output;
Described loop filter, produce one according to described phase information and control voltage signal;
Described voltage controlled oscillator, according to the frequency signal of described control voltage signal exporting change;
Described frequency division module, be connected between described voltage controlled oscillator and second electrical level converting unit, by described output frequency signal frequency reducing, sends described second electrical level converting unit to.
3. a kind of phase-locked loop signal source with emitter-coupled logic integrated circuit ECL phase discriminator according to claim 2, it is characterized in that, also comprise amplification module or pre-frequency division module between described voltage controlled oscillator and described frequency division module, for the output frequency signal to described voltage controlled oscillator, carry out power amplification or frequency reducing.
4. a kind of phase-locked loop signal source with emitter-coupled logic integrated circuit ECL phase discriminator according to claim 1, is characterized in that, described the first level conversion unit and second electrical level converting unit adopt the logical device that is output as the PECL level.
5. a kind of phase-locked loop signal source with emitter-coupled logic integrated circuit ECL phase discriminator according to claim 4, is characterized in that, described the first level conversion unit and second electrical level converting unit are ECL NAND gate, NOR gate or comparator.
6. a kind of phase-locked loop signal source with emitter-coupled logic integrated circuit ECL phase discriminator according to claim 5, it is characterized in that, when described the first level conversion unit and second electrical level converting unit are comparator, when the voltage of described input signal is greater than comparative voltage, export the PECL high level, when the voltage of described input signal is less than described comparative voltage, export the PECL low level, described comparative voltage is set to the dc-bias of applied signal voltage.
7. a kind of phase-locked loop signal source with emitter-coupled logic integrated circuit ECL phase discriminator according to claim 6, it is characterized in that, when the first level conversion unit adopts comparator, input signal is reference clock signal, when the second electrical level converting unit adopts comparator, input signal is the output frequency signal after frequency division.
8. a signal generating method, be applied to have the phase-locked loop signal source of emitter-coupled logic integrated circuit ECL phase discriminator, it is characterized in that comprising,
The generating reference clock signal;
By the level conversion of described reference clock signal for thering is positive emitter coupling logic level PECL;
The level conversion of the frequency signal of the variation that will export through the described signal source of frequency division is the signal with PECL level;
According to described reference clock signal and the described output frequency signal through level conversion with PECL level, obtain the phase difference of two paths of signals, output packet is containing the PECL level signal of phase information;
The described PECL level signal that comprises phase information is converted to and meets the level signal that comprises phase information that output is used;
Frequency signal according to the level signal exporting change that comprises phase information.
9. a kind of signal generating method according to claim 8, it is characterized in that, in the frequency signal of the level signal exporting change according to comprising phase information, also comprise, according to the level signal that comprises phase information, loop filter is discharged and recharged, described loop filter produces one according to described phase information and controls voltage signal, according to the frequency signal of described control voltage signal exporting change.
10. a kind of signal generating method according to claim 8, it is characterized in that, to be also to comprise in thering is the signal of PECL level through the level conversion of the output frequency signal of the described signal source of frequency division, amplify the power of the output frequency signal of described voltage controlled oscillator, carry out again divide operation, perhaps the frequency signal of described voltage controlled oscillator output carried out to pre-frequency division, reduce the frequency of described output frequency signal.
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| US10685802B2 (en) | 2016-05-18 | 2020-06-16 | Infineon Technologies Ag | Circuit architecture for a measuring arrangement, a level converter circuit, a charge pump stage and a charge pump, and method for operating same |
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