CN105553470A - Serializer based on half rate clock recovery circuit - Google Patents
Serializer based on half rate clock recovery circuit Download PDFInfo
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- CN105553470A CN105553470A CN201610061974.XA CN201610061974A CN105553470A CN 105553470 A CN105553470 A CN 105553470A CN 201610061974 A CN201610061974 A CN 201610061974A CN 105553470 A CN105553470 A CN 105553470A
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The invention discloses a serializer based on a half rate clock recovery circuit. The invention relates to the field of signal transformation, and aims at solving technical problems of the existing serializers, for example, in the same serializer, clock frequencies acquired by different clock generators are not matched, which causes relatively large error of output data, and glitch of output level of a logical circuit, clock jitter, data distortion, and so on. The structure mainly comprises a first clock generator, a first multiplexing circuit, a feedback clock generator, a second multiplexing circuit and a phase discriminator, wherein the first clock generator outputs a first clock signal for building a signal acquisition time window; the first multiplexing circuit samples the first clock signal output by the first clock generator, and receives a parallel source signal by an input end thereof and outputs a composite signal by an output end thereof. The serializer based on the half rate clock recovery circuit is used for high-speed serialization of signals.
Description
Technical field
The present invention relates to signal conversion art, be specifically related to a kind of serializer based on half rate clock restore circuit.
Background technology
Serializer receives parallel data and converts it to serial bit stream; Input signal is generally 8 bit parallel data, usually certain encoding scheme also can be utilized to convert 8 bit data to 10 bit data when upper serial output link transmission.Deserializer is then a contrary process.It receives serial data, decodes if desired, then is converted to the data of parallel form.Deserializer also will recover data clock, and clock is transmitted to follow-up element together with data.In SerDes, these 2 complementary elements provide and a kind ofly original parallel data transaction are become serial data thus carries out the effective means of high efficiency of transmission; Phase-locked loop (PLL) module is also had, its receiving system reference clock in SerDes, and by its frequency multiplication to corresponding data rate.Independently sampler module by use this frequency multiplication cross clock lock input serial data.
Existing serializer, particularly, adopt some optocouplers, have impact on operating rate in integrated circuit, and power consumption also can rise; And optocoupler serial line unit is not long for useful life, easily cause card; There is clock jitter and data dithering; Lack detection check interface.
Summary of the invention
For above-mentioned prior art, the object of the invention is to provide a kind of serializer based on half rate clock restore circuit, it is intended to solve existing serializer exists clock generators different in identical serializer and gathers clock frequency and not mate and to cause exporting data error larger, subsistence logic circuit output level burr simultaneously, the technical problem such as clock jitter and data distortion.
For achieving the above object, the technical solution used in the present invention is as follows:
Based on a serializer for half rate clock restore circuit, comprise parallel source signal, also comprise the first clock generator: export the first clock signal, for building signals collecting time window; First multiplex electronics: the first clock signal that its sampling clock port accepts first clock generator exports, input receives parallel source signal and output exports mixed signal; Feedback clock generator: receive the first clock signal of the first clock generator output to obtain reference clock, output feedack clock signal, for building time delayed signal acquisition time window; Second multiplex electronics: the feedback clock signal that its sampling clock port accepts feedback clock generator exports, input receives the mixed signal of the first multiplex electronics output and output exports serial signal; Second clock generator: export second clock signal, for building restoring signal acquisition time window; Clock data recovery circuit: have Semi-digital inside and outside ring structure, its inner ring road receives the second clock Signal reception serial signal that second clock generator exports, and exports the parallel signal relative to serial signal half frequency.
In such scheme, preferably, described clock data recovery circuit, comprises inner ring road: comprising phase-locked loop, and phase-locked loop exports multi-phase clock signal; The outer ring be connected with phase-locked loop: comprising the phase discriminator forming clock recovery loop, digital filter and phase interpolator, serial signal is inputted by phase discriminator input and multi-phase clock signal is inputted by phase interpolator.Serial signal converts the parallel data of two to after the clock sampling of half rate, then compares through phase discriminator and produces phase place discriminative information.Phase place discriminative information gives ratio and the integral element of digital filter simultaneously, finally produces phase control information and gives phase interpolator.The parallel signal of half frequency is the sign of serial signal, achieves feedback and the detection of output signal.
Described phase discriminator, comprises sample circuit circuits for triggering, decision circuit, two along circuits for triggering; Sample circuit circuits for triggering respectively under the control of the orthogonal each other clock pulse clk0 in four roads, clk90, clk180, clk270 to sampling input data, the sampled data under the sampled data respectively under output clock pulse clk0, the sampled data under clock pulse clk90, the sampled data under clock pulse clk180, clock pulse clk270; The rising edge of described clock pulse clk90 postpones T/4 relative to clock pulse clk0 and arrives, the rising edge of described clock pulse clk180 postpones T/4 relative to clock pulse clk90 and arrives, the rising edge of described clock pulse clk270 postpones T/4 relative to clock pulse clk180 and arrives, and T is the cycle of clock pulse clk0, clk90, clk180, clk270;
Described phase discriminator, also comprise re-synchronization circuits for triggering, sampled data under the clock pulse clk0 exported by sample circuit circuits for triggering under clock pulse clk180 controls, the sampled data under clock pulse clk90 carry out synchronism output, and the sampled data under the clock pulse clk180 exported by sample circuit circuits for triggering under clock pulse clk0 controls, the sampled data under clock pulse clk270 carry out synchronism output, sampled data under clock pulse clk0 after the process of re-synchronization circuits for triggering and the sampled data under clock pulse clk90 are carried out XOR by decision circuit, sampled data under the clock pulse clk180 directly exported from the sampled data under the clock pulse clk90 of synchronous trigger circuit again and sample circuit circuits for triggering is carried out XOR, sampled data under clock pulse clk180 after the process of re-synchronization circuits for triggering and the sampled data under clock pulse clk270 are carried out XOR, by from the sampled data under the clock pulse clk270 of synchronous trigger circuit again with carry out XOR from the sampled data under the clock pulse clk0 of sample circuit circuits for triggering, obtain respectively adjudicating index signal Up1, Up2, Dn1, Dn2, two reception along circuits for triggering adjudicates enable couple of index signal Up1, Up2 along circuits for triggering output UP signal, and judgement index signal Dn1, Dn2 is enable two along circuits for triggering output DN signal, two along circuits for triggering reception judgement index signal Up1, enable couple of judgement index signal Dn1 along circuits for triggering synchronism output coupling UP signal and DN signal under clock pulse clk270 control, under clock pulse clk90 control, two reception along circuits for triggering adjudicates index signal Up2, enable couple of judgement index signal Dn2 along circuits for triggering synchronism output coupling UP signal and DN signal.
In such scheme, the 3rd multiplex electronics: the feedback clock signal that its sampling clock port accepts feedback clock generator exports, input receives high low logic level and output output difference sub-signal.Can there is larger loss in feedback clock signal generative process, the 3rd multiplexer is clamped down on and difference input signal, makes feedback clock signal have higher resolution for the next circuit, increases response device speed.
In such scheme, described feedback clock generator, comprises phase detecting circuit: receive and the first more reverse clock signal and differential signal, export the first comparison signal; Voltage boosting-reducing circuit: receive the first comparison signal, exports control voltage signal; Reset circuit: output switching signal is to voltage boosting-reducing circuit; Frequency dividing circuit: receive the first clock signal, exports the first clock signal of half frequency; Delay circuit: receive control voltage signal to adjust delay time, and receive the clock signal of frequency dividing circuit output, output feedack clock signal.Phase detecting circuit by the first clock signal comparison the 3rd multiplex electronics output differential signal of the reversion in a phase place, particularly, by the rising edge of the first clock signal of reversion and the edge of the differential signal of the 3rd multiplex electronics.The comparison signal exported when phase detecting circuit is logic high, namely illustrates that the first clock signal of reversion is not mated with the differential signal of the 3rd multiplex electronics.The reference time delay of delay circuit can impact control voltage scope, particularly, reduces the order of delay circuit, reduces delay time scope, can reduce circuit complexity and electric quantity consumption, and reduce noise and shake further; After shake reduces, can increase the acquisition time window applied multiplex electronics, data can pass through more quickly switching device more.
In such scheme, preferably, described reset circuit, comprises the first comparator: export the second comparison signal; Second comparator: export the 3rd comparison signal; First or door: receive the first comparison signal and the second comparison signal; First inverter of connecting successively with first or door, the second inverter and buffer; Second or door: its input is connected with first or the output of door and the output of the second inverter; 3rd inverter: its input connects the output of second or door; First triode: base stage connects the output of the 3rd inverter, the high electricity end of emitter connecting circuit; Second triode: base stage connects the output of second or door, the low electricity end of emitter connecting circuit; First node is the output of first or door, is connected to delay circuit; Section Point is the output of buffer, is connected to the output of voltage boosting-reducing circuit; 3rd node is the collector potential end of the first triode, is connected to the 3rd multiplex electronics; 4th node is reference voltage potential point.The control voltage level that the switching signal that reset circuit exports exports based on voltage boosting-reducing circuit.Voltage boosting-reducing circuit has high threshold voltage and low threshold voltage, when control voltage level is lower than low threshold voltage and higher than high threshold voltage, reset circuit closes voltage boosting-reducing circuit, and control voltage level is reset between low threshold voltage and high threshold voltage, particularly, 50% of supply voltage is reset to.High threshold voltage scope and low threshold voltage scope are respectively supply voltage 0 to 30% and 85% to 100%.Reset circuit is to the control of delay circuit, and can control further to window the time to the sampling of the first multiplex electronics, the system that improves is to the identification of data waveform and judgement speed.
In such scheme, preferably, second clock signal rate is 1/2nd of the first clock signal.The system clock of clock data recovery circuit is provided.
Compared with prior art, beneficial effect of the present invention is: modulate to control acquisition window width to collection clock by data-signal self feed back, obtains more reasonably parallel signal and turns serial signal self feed back modulation circuit structure; Data waveform rising time and trailing edge time significantly reduce; Fundamentally eliminate the situation producing mistake pairing, substantially reduce the burr that pure combinational logic produces.
Accompanying drawing explanation
Fig. 1 is model calling relation schematic diagram of the present invention;
Fig. 2 is the embodiment of reset circuit of the present invention;
Fig. 3 is the embodiment of delay circuit of the present invention;
Fig. 4 is the embodiment of phase discriminator of the present invention.
Embodiment
All features disclosed in this specification, or the step in disclosed all methods or process, except mutually exclusive feature, beyond step, all can combine by any way.
Below in conjunction with accompanying drawing, the present invention will be further described:
Fig. 1 is model calling relation schematic diagram of the present invention, a kind of serializer based on half rate clock restore circuit, first clock generator and second clock generator, consider concrete implementation environment, and the calibration pulse output of processor in electronic system can be used to replace.In signal conversion operation process, the first clock signal and serial signal are locked in the equivalent delay locked loop of feedback clock generator, and serial signal clock rate is the half of the first clock signal clock speed of the first clock signal clock speed or reversion.
Embodiment 1
Fig. 2 is the embodiment of reset circuit of the present invention, and in the present embodiment, inverter U4 and inverter U5 is the simplest time delay device, and described delay circuit can be selected to replace inverter U4 and inverter U5 to obtain better function of initializing.After replacement, 4th node is reference voltage input node, its size depends on the threshold voltage of comparator and the required setting of comparator of selecting, or door U3 the second comparison signal, the 3rd comparison signal that export of device U1 and comparator U2 based on the comparison, generate the first control signal, or the first control signal that door U3 exports is sent to first node.Delay circuit is by the first control signal time delay, and the reference voltage of the 4th node input is depended in time delay interval, and particularly, delay time depends on that the reference voltage extent of the 4th node input and reference voltage difference are loaded into the time used in the first control signal.
Embodiment 2
Fig. 3 is the embodiment of delay circuit of the present invention, the buffer U9-U12 of series connection, and classification time is access in tunable capacitor C1-C3; 5th node and the 7th node are input node, and the 6th node is output node; 7th node access voltage boosting-reducing circuit, the capacitance of voltage boosting-reducing control circui tunable capacitor, buffer U9-U12 produces phase delay.
Embodiment 3
Described voltage boosting-reducing circuit, i.e. BOOST circuit, can use spatial volume situation shared by circuit to carry out reducing replacement according to reality; As, when needing less circuit space volume, can change and elect charge pump as.Charge pump, its energy storage device can be electric capacity, and output is multiple series connection and the collector and emitter of the complementary triode of raceway groove about output symmetry, and input is the base stage of multiple triode, the logic realized as required adds certain gate in base stage, realizes charge pump; Relative to BOOST circuit, charge pump cloth plate bulk is relatively little, and circuit structure does not need inductance, and response speed is exceedingly fast.
Embodiment 4
Fig. 4 is the embodiment of phase discriminator of the present invention, sampled data D0 under clock pulse clk0, sampled data D90 under clock pulse clk90, sampled data D180 under clock pulse clk180 is the data sample point of continuous sampling three times, sampled data D180 in like manner under clock pulse clk180, sampled data D0 under sampled data D270 under clock pulse clk270, clock pulse clk0 is also the data sample point (D0 is now D360) of continuous sampling three times.Because in the half rate clock cycle (namely equaling two data cycles), there is the data sample point of two groups of continuous samplings three times: (D0, D90, and (D180 D180), D270, D0), therefore explain the subsequent treatment situation of these two groups of data sample points below respectively, thus be easier to understand the operation principle of phase discriminator.
The data sample point that first group of continuous sampling is three times: D0, D90, D180.Clock pulse clk0, clk90 and clk180 act on trigger 301 ~ 303 successively, and continuous three sampling input data data, therefore create three data sample point D0, D90, D180.Wherein D0 and D90 carries out xor operation generation judgement index signal Up1; D90 and D180 carries out xor operation and produces judgement index signal Dn1.To make signal Up1 and Dn1 in synchronization output and effectively, then requiring D0, D90 and D180 is in synchronization output and effectively, therefore the necessary re-synchronization of D0, D90 and D180 is in a clock signal.The present invention uses clk180 to act on trigger 311 and 312, re-synchronization D0 and D90, produces signal D0_1 and D90_1 after re-synchronization respectively, then in conjunction with D180, by XOR gate 321 and 322, creates judgement index signal Up1 and Dn1 respectively.Next clock after clk180 is along being clk270, and therefore to use clk270 to act on two along trigger 331 and 332 in the present invention, more synchronously once adjudicates index signal Up1 and Dn1, thus produces final UP and DN signal.
The data sample point that second group of continuous sampling is three times: D180, D270, D0.In like manner, clock pulse clk180, clk270 and clk0(clk0 is now clk360) act on trigger 303 successively, 304 and 301, continuous three sampling input data data, therefore create three data sample point D180, D270, D0(D0 is now D360).Wherein D180 and D270 carries out xor operation generation signal Up2; D270 and D0 carries out xor operation and produces signal Dn2.To make signal Up2 and Dn2 in synchronization output and effectively, then requiring D180, D270 and D0 is in synchronization output and effectively, therefore the necessary re-synchronization of D180, D270 and D0 is in a clock signal.The present invention uses clk0 to act on trigger 313 and 314, re-synchronization D180 and D270, produces D180_1 and D270_1 respectively, then is D360 in conjunction with D0(D0 now), by XOR gate 323 and 324, create Up2 and Dn2 signal respectively.Clk0(clk0 is now clk360) after next clock along being clk90, therefore to use clk90 to act on two along trigger 331 and 332 in the present invention, a more synchronous Up2 and Dn2 signal, thus produce final UP and DN signal.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, anyly belongs to those skilled in the art in the technical scope that the present invention discloses; the change that can expect easily or replacement, all should be encompassed within protection scope of the present invention.
Claims (4)
1., based on a serializer for half rate clock restore circuit, comprise parallel source signal, it is characterized in that, also comprise
First clock generator: export the first clock signal, for building signals collecting time window;
First multiplex electronics: the first clock signal that its sampling clock port accepts first clock generator exports, input receives parallel source signal and output exports mixed signal;
Feedback clock generator: receive the first clock signal of the first clock generator output to obtain reference clock, output feedack clock signal, for building time delayed signal acquisition time window;
Second multiplex electronics: the feedback clock signal that its sampling clock port accepts feedback clock generator exports, input receives the mixed signal of the first multiplex electronics output and output exports serial signal;
Second clock generator: export second clock signal, for building restoring signal acquisition time window;
Clock data recovery circuit: there is Semi-digital inside and outside ring structure, its inner ring road receives the second clock Signal reception serial signal that second clock generator exports, and exports the parallel signal relative to serial signal half frequency;
Described clock data recovery circuit, its inner ring road: comprising phase-locked loop, phase-locked loop exports multi-phase clock signal, the outer ring be connected with phase-locked loop: comprising the phase discriminator forming clock recovery loop, digital filter and phase interpolator, serial signal is inputted by phase discriminator input and multi-phase clock signal is inputted by phase interpolator;
Described phase discriminator, comprises sample circuit circuits for triggering, decision circuit, two along circuits for triggering and re-synchronization circuits for triggering, sample circuit circuits for triggering respectively under the control of the orthogonal each other clock pulse in four roads to sampling input data.
2. a kind of serializer based on half rate clock restore circuit according to claim 1, is characterized in that, also comprise
3rd multiplex electronics: the feedback clock signal that its sampling clock port accepts feedback clock generator exports, input receives high low logic level and output output difference sub-signal.
3. a kind of serializer based on half rate clock restore circuit according to claim 1, is characterized in that, described feedback clock generator, comprises
Phase detecting circuit: receive and the first more reverse clock signal and differential signal, export the first comparison signal;
Voltage boosting-reducing circuit: receive the first comparison signal, exports control voltage signal;
Reset circuit: output switching signal is to voltage boosting-reducing circuit;
Frequency dividing circuit: receive the first clock signal, exports the first clock signal of half frequency;
Delay circuit: receive control voltage signal to adjust delay time, and receive the clock signal of frequency dividing circuit output, output feedack clock signal.
4. a kind of serializer based on half rate clock restore circuit according to claim 1, is characterized in that, described orthogonal clock pulse, is produced or produced by the signal generator that can produce the orthogonal clock pulse each other of four roads by voltage controlled oscillator.
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| CN201610061974.XA CN105553470B (en) | 2016-01-29 | 2016-01-29 | A kind of serializer based on half rate clock restoring circuit |
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| CN201610061974.XA CN105553470B (en) | 2016-01-29 | 2016-01-29 | A kind of serializer based on half rate clock restoring circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107659392A (en) * | 2017-03-13 | 2018-02-02 | 广东高云半导体科技股份有限公司 | A kind of clock data recovery system |
| CN108331577A (en) * | 2017-12-27 | 2018-07-27 | 北京六合伟业科技股份有限公司 | Through non magnetic drill collar and MWD wireless communication systems and method in oil drilling |
| CN110945372A (en) * | 2017-06-15 | 2020-03-31 | 耐瑞唯信有限公司 | Method for detecting at least one glitch in an electrical signal and device for carrying out the method |
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| US20060078078A1 (en) * | 2004-10-07 | 2006-04-13 | Kawasaki Microelectronics, Inc. | Phase detector for comparing phases of data and a plurality of clocks |
| CN102801414A (en) * | 2012-08-23 | 2012-11-28 | 电子科技大学 | Bang-bang discriminator used for half speed rate clock data restoring circuit |
| CN205596095U (en) * | 2016-01-29 | 2016-09-21 | 成都科创谷科技有限公司 | Serializer based on half rate clock recovery circuit |
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| US20060062339A1 (en) * | 2004-09-23 | 2006-03-23 | Standard Microsystems Corporation | Linear half-rate clock and data recovery (CDR) circuit |
| US20060078078A1 (en) * | 2004-10-07 | 2006-04-13 | Kawasaki Microelectronics, Inc. | Phase detector for comparing phases of data and a plurality of clocks |
| CN102801414A (en) * | 2012-08-23 | 2012-11-28 | 电子科技大学 | Bang-bang discriminator used for half speed rate clock data restoring circuit |
| CN205596095U (en) * | 2016-01-29 | 2016-09-21 | 成都科创谷科技有限公司 | Serializer based on half rate clock recovery circuit |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107659392A (en) * | 2017-03-13 | 2018-02-02 | 广东高云半导体科技股份有限公司 | A kind of clock data recovery system |
| CN107659392B (en) * | 2017-03-13 | 2019-12-13 | 广东高云半导体科技股份有限公司 | clock data recovery system |
| CN110945372A (en) * | 2017-06-15 | 2020-03-31 | 耐瑞唯信有限公司 | Method for detecting at least one glitch in an electrical signal and device for carrying out the method |
| CN110945372B (en) * | 2017-06-15 | 2022-06-14 | 耐瑞唯信有限公司 | Method for detecting at least one spur in an electrical signal and device for carrying out said method |
| CN108331577A (en) * | 2017-12-27 | 2018-07-27 | 北京六合伟业科技股份有限公司 | Through non magnetic drill collar and MWD wireless communication systems and method in oil drilling |
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Effective date of registration: 20240822 Address after: No. 22, West Hanging Ear, Binjiang Village, Xinqiao Town, Jingjiang City, Taizhou City, Jiangsu Province, 214500 Patentee after: Jiang Kaiping Country or region after: China Address before: 214500 No. 68-10, north side of North Third Ring Road, Chengbei Park, Jingjiang Economic Development Zone, Taizhou City, Jiangsu Province Patentee before: Jiangsu Yongxin Hengye Auto Parts Technology Co.,Ltd. Country or region before: China |