CN103165570B - 具有晶体管区域互连的半导体设备 - Google Patents

具有晶体管区域互连的半导体设备 Download PDF

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CN103165570B
CN103165570B CN201210539484.8A CN201210539484A CN103165570B CN 103165570 B CN103165570 B CN 103165570B CN 201210539484 A CN201210539484 A CN 201210539484A CN 103165570 B CN103165570 B CN 103165570B
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transistor
region
layer
gate
interconnect layer
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CN103165570A (zh
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M·拉希德
I·Y·林
S·索斯
J·金
C·阮
M·泰拉比
S·约翰逊
S·坎格瑞
S·文卡特桑
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格罗方德半导体公司
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Abstract

本发明揭露一种具有晶体管区域互连的半导体设备,其中提供一种用于实现至少一个逻辑组件的半导体设备。该半导体设备包含半导体衬底,其具有形成于该半导体衬底上的第一晶体管与第二晶体管。所述晶体管各包含源极、漏极与栅极。沟槽硅化物层使该第一晶体管的源极或漏极中之一电气连接至该第二晶体管的源极或漏极中之一。

Description

具有晶体管区域互连的半导体设备

技术领域

[0001]本发明大体涉及半导体设备,且更特别的是,涉及半导体设备的晶体管区域互连(local interconnect) ο

背景技术

[0002]随着半导体设备的尺寸持续减小,制作标准单元库逻辑设备(例如,扫描D正反器(scan-D flip-flop)与多任务器)的能力变得越来越困难。特别是在20纳米(nm)节点的情形下,微影的限制导致标准单元库设备的缩放(scaling)不足。晶体管的交互耦合对于关键标准单元库设备的缩放很重要。若无交互耦合,逻辑缩放会占用更多半导体设备的面积。此夕卜,利用标准金属层的传统交互耦合也会占据大量的面积。由于会导致半导体设备更大或半导体设备的机能更少,所以这两种情形都不合意。

[0003]因此,最好提供晶体管的交互耦合而不依赖标准金属层即可产生标准单元库设备同时保留半导体设备面积。此外,由以下结合附图、背景技术及所描述的详细说明和随附权利要求书可明白本发明的其它合意特征及特性。

发明内容

[0004]本发明提供一种用于实现至少一个逻辑组件的半导体设备。在本发明的一实施例中,该半导体设备包含半导体衬底,其具有形成于该半导体衬底上的第一晶体管与第二晶体管。所述晶体管各包含源极、漏极与栅极。沟槽硅化物层使该第一晶体管的源极或漏极中之一电气连接至该第二晶体管的源极或漏极中之一。

[0005]在本发明的另一实施例,该半导体设备包含半导体衬底,其具有配置于该衬底上的第一晶体管与第二晶体管。所述晶体管各包含源极、漏极与栅极。第一 CB层电气连接至该第一晶体管的栅极。第二 CB层电气连接至该第二晶体管的栅极。CA层在第一端、第二端之间纵向延伸。该第一 CB层与该CA层的该第一端邻接地电气连接。该第二 CB层与该CA层的该第二端邻接地电气连接。

[0006]在本发明的又一态样,半导体设备包含半导体衬底,其具有配置于该衬底上的第一晶体管与第二晶体管。所述晶体管各包含栅极,其中,所述栅极大体相互平行地纵向延伸。CB层使该第一及该第二晶体管的栅极电气连接以及形成锯齿形状(zig-zag shape)。

附图说明

[0007]以下结合附图描述本发明,其中类似的组件用相同的组件符号表示,且

[0008]图1为半导体设备的一部份的侧视截面图;

[0009]图2为半导体设备的一个具体实施例的上视图,其显示晶体管的栅极、各个区域互连层及沟槽硅化物层;

[0010]图3为半导体设备的另一具体实施例的上视图,其显示配置于晶体管的栅极上方的金属层以及各个区域互连层;[0011 ]图4为半导体设备的第一具体实施例的部份上视图;

[0012]图5为半导体设备的第二具体实施例的部份上视图;

[0013]图6为半导体设备的第四具体实施例的部份上视图;

[0014]图7为根据图6的直线7-7绘出半导体设备的第四具体实施例的侧视截面图;

[0015]图8为半导体设备的第五具体实施例的部份上视图;

[0016]图9为半导体设备的第六具体实施例的部份上视图;以及

[0017]图10为根据图2的直线10-10绘出半导体设备的第七具体实施例的部份侧视图。

[0018] 主要组件符号说明

[0019] 20 半导体设备

[0020] 22 半导体衬底

[0021] 24 晶体管

[0022] 24a 第一晶体管

[0023] 24b 第二晶体管

[0024] 24c 第三晶体管

[0025] 24d 第四晶体管

[0026] 26、26a、26b 源极

[0027] 28、28a、28b 漏极

[0028] 30、30a_d 栅极

[0029] 31 线性条带

[0030] 31b 第一线性条带

[0031] 31b 第二线性条带

[0032] 32 间隙

[0033] 32a 第一间隙

[0034] 32b 第二间隙

[0035] 33 金属层

[0036] 34,36 区域互连层

[0037] 34 CA层

[0038] 34a 第一 CA层

[0039] 36 第二区域互连层

[0040] 36 CB层[0041 ] 36a 第一 CB层

[0042] 36b 第二 CB层

[0043] 37 沟槽硅化物层

[0044] 38 通孔

[0045] 40 第一端

[0046] 42 第二端

[0047] 44 中央

[0048] 44 绝缘层

[0049] 46 末端

[0050] 48 第二 CA层。

具体实施方式

[0051]以下的详细说明在本质上只是示范而非旨在限制本发明或本发明的应用或用途。此外,希望不受【背景技术】或【实施方式】中的任何理论约束。

[0052]在此描述半导体设备20,其显示于附图,其中类似的组件用相同的组件符号表示。本领域技术人员周知,半导体设备20可为集成电路(未个别编号)的一部份。

[0053]请参考图1,半导体设备20包含半导体衬底22。半导体设备20包含多个晶体管24。具体而言,在图示的具体实施例中,晶体管24为场效晶体管(FET),且更特别的是,金属氧化物半导体场效晶体管(MOSFET)。晶体管24各包含源极26、漏极28与栅极30。

[0054]源极26及漏极28均用本领域技术人员所习知的技术形成于衬底22中及/或上。在图示的具体实施例中,源极26及漏极28经形成为凸起源极26及漏极28,亦即,源极26及漏极28至少有一部份形成于衬底22上方。在显示于图1的配置中,凸起源极26及漏极28各高出衬底22约15纳米。不过,可替换地实现其它的尺寸。本领域技术人员明白可用嵌入式硅/锗(eSiGe)技术来形成凸起源极26及漏极28。当然,可实施其它的技术以形成凸起源极26及漏极28 ο此外,在其它具体实施例中(未显示),可能不使源极26及漏极28凸出衬底22。

[0055]栅极30通常使用本领域技术人员所习知的技术形成于衬底22上方。在图示的具体实施例中,配置衬底22上方的栅极30主要由常被称作多晶硅或以PolySi简称的复晶硅形成。不过,栅极30也可由其它的材料形成,例如,高k金属。在显示于图1的配置中,栅极30高出衬底22约35纳米。不过,可替换地实现栅极30的其它尺寸。

[0056] 参考图2可见,栅极30形成为大体相互平行的线性条带(linear strip)31。条带31中可形成间隙(gap)32使得沿着各个条带31可纵向配置一个以上的晶体管30。可用本领域技术人员容易明白的切割屏蔽技术(cut mask technique)来形成间隙32。

[0057]请参考图1及图3,半导体设备20包含配置于晶体管24的源极26、漏极28与栅极30上方的至少一个金属层33,如本领域技术人员所知。金属层33有助于设备20的各个逻辑组件与设备20的其它逻辑组件及设备20以外的其它系统电气通讯。本领域技术人员也明白,金属层33照惯例是以M1、M2等等标称。在显示于图1的配置中,配置高出衬底22约165纳米的一个金属层33 ο不过,可替换地实现金属层33的其它距离及尺寸。

[0058] 半导体设备20进一步包含至少一个区域互连层34、36以选择性地使晶体管24的源极26、漏极28与栅极30连接至其它晶体管24的其它源极26、漏极28与栅极30。至少一个区域互连层34、36也可选择性地连接至至少一个金属层33。至少一个区域互连层34、36配置于至少一个金属层33与衬底22之间。换言之,相对于衬底22,金属层33配置于至少一个区域互连层34、36上方。图示的具体实施例的至少一个区域互连层34主要由钨形成。在其它具体实施例中,至少一个区域互连层34、36主要由铜形成。不过,区域互连层34、36可由其它元素或化合物形成或包含。

[0059]以下描述显示于附图的各个半导体设备20实施例有不同的形状、排列(arrangement),以及至少一个区域互连层34、36的电气连接。第一区域互连层34在此被称作CA层34,以及第二区域互连层36在此被称作CB层36。当然,半导体设备20中可实现多个CA层34及多个CB层36以及也可实现其它的区域互连层(未显示)。通常,CA层(或数个)34电气连接至源极26或漏极28同时CB层(或数个)36电气连接至栅极30。不过,不应把这类配置视为限制。事实上,在下述具体实施例中的一些中,CA层(或数个)34及/或CB层(或数个)36可能不连接至源极26、漏极28或栅极30。

[0060]利用图示的具体实施例的CA、CB层34、36可产生各种标准单元,例如,扫描D正反器。在背景技术中,金属层常用来提供扫描D正反器的连接。利用CA、CB层34、36(经配置成比典型金属层还要靠近衬底),相比于背景技术的设备,所得扫描D正反器有减少的面积。

[0061 ]半导体设备20可进一步包含一个或多个沟槽硅化物层37。沟槽硅化物层37可用来使晶体管24的源极26及/或漏极28电气连接至CA或CB层34、36中的一个,通常为CA层,如图1所示。因此,沟槽硅化物层37夹在CA或CB层34、36中的一个与晶体管24的源极26或漏极28中的至少一个之间。沟槽硅化物层37的形成通过切割深至衬底22的电介质(未显示)沟槽(未个别编号)以及用自对准娃化物材料(salicide material)填满沟槽。例如,该自对准娃化物材料可为金属,例如镍、钴或钨。

[0062]图1配置的沟槽硅化物层37有约50纳米的高度。图1的CA层34用沟槽硅化物层34支撑以及有约40纳米的高度。图1的CB层36有约70纳米的高度。图1的CA层34及CB层36对于衬底22大体同高。此外,由图1可见,图示的具体实施例的CA、CB层34、36高出衬底22不超过105纳米。当然,在取决于任意多个因素的替代具体实施例中,沟槽硅化物层37、CA层34及CB层36的高度及尺寸可不同。

[0063] 半导体设备20可包含多个通孔38以选择性地提供CA或CB层34、36与至少一个金属层33的电气连接。因此,通孔38中的一个可配置于至少一个金属层33与CA或CB层34、36中的一者之间。通孔38主要由金属形成,例如铜。不过,也可使用其它的金属或导电材料。图1的配置的通孔38有约60纳米的高度。

[0064]在第一具体实施例中,如图4所示,半导体设备20至少包含第一晶体管24a与第二晶体管24b。半导体设备20包含CA层34与CB层36XA层34电气连接至第一晶体管24a的源极26a或漏极28a中的至少一者。CB层36电气连接至晶体管24a、24b的栅极30中的至少一者。取决于特定应用,CB层36可电气连接至晶体管24a、24b的栅极30。第一及CB层34、36也可相互电气连接。

[0065] 在第一具体实施例中,CA层34在第一端40和第二端42之间延伸。CB层36大体配置于CA层34在末端40、42之间的中央44。更特别的是,CB层36的末端46大体配置在CA层34的中央44。因此,从上面俯视,第一及CB层34、36形成一长‘ T ’形状。

[0066]半导体设备20的第二具体实施例与第一具体实施例实质类似,但是进一步包含配置在CA层34与第一晶体管24a的源极26或漏极28中的至少一者之间的沟槽硅化物层37。此排列也可再参考图1。

[0067]在第三具体实施例中,如图5所示,半导体设备20至少包含第一晶体管24a与第二晶体管24b。半导体设备20包含第一 CA层34a与CB层36。第一 CA层34a电气连接至第一晶体管24a的源极26a或漏极28a中的至少一者。CB层36电气连接至晶体管24a、24b的栅极30a、30b中的至少一者。取决于特定应用,CB层36可电气连接至晶体管24a、24b的栅极30a、30b。第一及CB层34、36也相互电气连接。

[0068] 在第三具体实施例中,如同第一具体实施例,CA层34在第一端40、第二端42之间延伸。不过,在第三具体实施例中,CB层36经配置成与末端40、42中的一个邻接。因此,从上面俯视,第一及CB层34、36形成一长‘ L ’形状。第三具体实施例的长‘ L ’形状允许把CB层36配置成与第二 CA层48分离以防CB层36与第二 CA层48之间的导电。

[0069]请参考图6及图7,半导体设备20的第四具体实施例包含形成于衬底22上的第一晶体管24a、第二晶体管24b及第三晶体管24c。所述晶体管24由第一晶体管24a至第三晶体管24c依序配置。设备20可进一步包含第四晶体管24d,其中,所述晶体管24由第一晶体管24a至第四晶体管24d依序配置。

[0070]第一CB层36a电气连接至第一晶体管24a的栅极30a,以及第二CB层36b电气连接至第三晶体管24c的栅极30CXA层34使第一 CB层36a与第二 CB层36b相互电气连接。因此,第一晶体管24a的栅极30与第三晶体管24c的栅极30c通过CB层36a、36b及CA层34相互电气连接。

[0071] CA层34与第二晶体管24b的栅极30b电气隔离。因此,CA层34形成跨过第二晶体管24b的栅极30b的“桥状物(bridge ),,或“跳线(jumper)”。一个或多个绝缘层44可夹在CA层34与第二晶体管24b的栅极30之间。一个或多个绝缘层44也可夹在CA层36与衬底22之间。

[0072]取决于特定逻辑组件的需要,第二 CB层36b也可电气连接至第四晶体管24d的栅极30。此外,CA层34也可电气连接至晶体管24a、24b、24c中的一个的源极26或漏极28中的至少一者。如图6及图7所示,相对于衬底22,CA层34及CB层34a、34b配置于晶体管24a、24b、24c、24d的栅极30上方。

[0073]在第五具体实施例中,半导体设备20包含半导体衬底22,其具有配置于衬底22上的第一晶体管24a及第二晶体管24b,如图8所示。第一 CB层36a电气连接至第一晶体管24a的栅极30a,以及第二CB层36b电气连接至第二晶体管24b的栅极30aXA层34在第一端40、第二端42之间纵向延伸。第一 CB层36a与CA层34的第一端40邻接地电气连接至CA层34。第二 CB层36b与CA层34的第二端42邻接地电气连接至CA层34。

[0074]第一晶体管24a的栅极30a纵向延伸成为第一线性条带31a的一部份,以及第二晶体管24b的栅极30b纵向延伸成为第二线性条带31b的一部份。第一、第二条带31a、31b大体相互平行以及彼此隔开。CA层34大体垂直于第一、第二 CB层36a、36b。因此,CA层34与条带31a、31b大体平行地延伸以及配置于条带31a、31b之间。因此,从上面俯视,CA层34及CB层36a、36b—起形成锯齿形状或大体S形状。

[0075]第五具体实施例的半导体设备20可进一步包含第三晶体管24c与第四晶体管24d。第三晶体管24c的栅极30c纵向延伸成为第一条带31a的一部份,以及第四晶体管24d的栅极30d纵向延伸成为第二条带31b的一部份。间隙32使第一晶体管24a的栅极30a与第三晶体管24c的栅极30c分离,以及使第二晶体管24b的栅极30与第四晶体管24d的栅极30分离。因此,第一、第二晶体管24a、24b的栅极30彼此在对角线的角落上,而CA层34延伸越过间隙32。

[0076]在第六具体实施例中,如图9所示,半导体设备20包含半导体衬底22,其具有第一晶体管24a与配置于衬底22上的第二晶体管24b。晶体管24a、24b的栅极30a、30b大体相互平行地纵向延伸。第一栅极30a形成为第一线性条带31a的一部份,以及第二栅极30b形成为第二线性条带31b的一部份。单一 CB层36电气连接至第一、第二晶体管24a、24b的栅极30。晶体管24a、24b的栅极30a、30b可能不直接相互邻接。因此,CB层36形成锯齿形以使晶体管24a、24b电气连接。

[0077]具体而言,如图9所示,设备20包含第三晶体管24c与第四晶体管24d。第三晶体管24c的栅极30c纵向延伸成为第一条带31a的一部份,以及第四晶体管24d的栅极30d纵向延伸成为第二条带31b的一部份。第一间隙32a使第一晶体管24a的栅极30a与第三晶体管24c的栅极30c分离。第二间隙32b使第二晶体管24b的栅极30b与第四晶体管24d的栅极30d分离。第六具体实施例的间隙32a、32b未彼此对齐。

[0078]请参考图2及图10,第七具体实施例的半导体设备20包含第一晶体管24a与第二晶体管24b。沟槽硅化物层37使第一晶体管24a的源极26a或漏极28a电气连接至第二晶体管24b的源极26b或漏极28b。具体而言,图10显示为η型FET的第一晶体管24a与为P型FET的第二晶体管24b,以及晶体管24a、24b的凸起漏极28a、28b经由沟槽硅化物层37相互电气连接。

[0079]第一晶体管24a的栅极30a与第二晶体管24b的栅极30b由共享线性条带31形成。因此,栅极30a、30b彼此呈线性地延伸。沟槽硅化物层37配置在栅极30a、30b的一侧。亦即,沟槽硅化物层37不越过栅极30a、30b或共享线性条带31同时仍使晶体管24a、24b的漏极28a、28b电气连接。换言之,沟槽硅化物层37不需要越过由线性条带31形成的“复合边界(polyboundary)”。此排列可用来产生扫描D正反器。相比于背景技术的设备,所得的扫描D正反器有减少的面积。当然,本领域技术人员明白,此排列可用来制作扫描D正反器以外的逻辑设备。

[0080]第七具体实施例的半导体设备20也可包含电气连接至晶体管24a、24b的各个栅极30a、30b的单边接触(未显示)。利用单边接触,亦即,不延伸遍与栅极30a、30b的整个宽度的接触,可减少沟槽娃化物层37与栅极30a、30b发生介质击穿(dielectric breakdown)的风险。

[0081] 尽管已用上文详细说明至少一示范具体实施例,然而应了解,仍有许多变体。也应了解,该(所述)示范具体实施例只是实施例而非旨在以任何方式限制本发明的范畴、适用性或配置。反而,上述详细说明是要让本领域技术人员有个方便的发展蓝图用来具体实现本发明的示范具体实施例,应了解,示范具体实施例提及的组件的功能及配置可做出不同的改变而不脱离如随附权利要求书及其合法等效物所述的范畴。

Claims (17)

1.一种半导体设备,包含: 半导体衬底; 形成于该半导体衬底上的第一晶体管及第二晶体管; 所述晶体管各包含源极、漏极与栅极; 沟槽硅化物层,其将该第一晶体管的该源极或该漏极之一电气连接至该第二晶体管的该源极或该漏极之一,其特征在于,该沟槽硅化物层至少部分嵌入该半导体衬底; 第一区域互连层,其电气连接且接触于该沟槽硅化物层;以及 第二区域互连层,其电气连接至该第一与第二晶体管的一个的栅极以及电气连接至该第一区域互连层。
2.如权利要求1所述的半导体设备,其中,该第一晶体管的该栅极与该第二晶体管的该栅极呈线性延伸。
3.如权利要求2所述的半导体设备,其中,该沟槽硅化物层配置在该第一及该第二晶体管的所述栅极的一侧上。
4.如权利要求1所述的半导体设备,其中,该沟槽硅化物层将该第一晶体管的该漏极电气连接至该第二晶体管的该漏极。
5.如权利要求4所述的半导体设备,其中,该第一晶体管为η型场效晶体管FET,以及该第二晶体管为P型FET。
6.如权利要求5所述的半导体设备,其中,该第一晶体管的该栅极与该第二晶体管的该栅极呈线性延伸。
7.如权利要求6所述的半导体设备,其中,该沟槽硅化物层配置在该第一及该第二晶体管的所述栅极的一侧上。
8.如权利要求1所述的半导体设备,进一步包含电气连接至所述晶体管的各个栅极的单边接触。
9.如权利要求1所述的半导体设备,进一步包含 配置在该第一区域互连层与该第二区域互连层上的金属层;以及配置在该第一区域互连层与该第二区域互连层上用于电气连接该第一区域互连层与该第二区域互连层的一个至该金属层的复数个通孔; 其中该复数个通孔的一个配置在该第一区域互连层与该第二区域互连层的一个与该金属层之间。
10.如权利要求1所述的半导体设备,其中,该沟槽硅化物层包含钨。
11.一种半导体设备,包含: 半导体衬底; 配置于该衬底上的第一晶体管、第二晶体管及第三晶体管,其中该第二晶体管配置于该第一晶体管与该第三晶体管之间; 所述晶体管各包含源极、漏极与栅极; 电气连接至该第一晶体管的该栅极的第一第二区域互连层; 电气连接至该第三晶体管的该栅极的第二第二区域互连层;以及 电气连接该第一与第二第二区域互连层的第一区域互连层;其中, 该第一与第三晶体管的该栅极互相电气连接且与该第二晶体管的栅极电气隔尚。
12.如权利要求11所述的半导体设备,其中,该第一、第二及第三晶体管的该栅极纵向延伸且相互平行。
13.如权利要求12所述的半导体设备,其中,该第一区域互连层的上表面、该第一第二区域互连层的上表面、以及该第二第二区域互连层的上表面彼此共平面。
14.如权利要求13所述的半导体设备,其中,该第一区域互连层于该衬底上延伸小于105纳米。
15.如权利要求14所述的半导体设备,进一步包含夹在该第一区域互连层与该第二晶体管的该栅极之间的绝缘层。
16.如权利要求15所述的半导体设备,进一步包含 包含栅极的第四晶体管; 其中,该第二第二区域互连层还电气连接至该第四晶体管的该栅极,藉此该第一、第三及第四晶体管彼此电气连接。
17.—种半导体设备,包含: 半导体衬底; 配置于该衬底上的第一晶体管及第二晶体管; 所述晶体管各包含源极、漏极与栅极; 其中所述第一晶体管的栅极沿着第一条带纵向延伸且所述第二晶体管的所述栅极沿着第二条带纵向延伸,其中,所述第一条带及第二条带相互平行地纵向延伸且互相分隔;电气连接至该第一晶体管的该栅极的第一第二区域互连层; 电气连接至该第二晶体管的该栅极的第二第二区域互连层; 电气连接该第一与第二第二区域互连层的第一区域互连层; 其中所述第一第二区域互连层电气连接至所述第一区域互连层邻近于所述第一区域互连层的第一端;其中所述第二第二区域互连层电气连接至所述第一区域互连层邻近于所述第一区域互连层的第二端;以及 其中所述第一区域互连层延伸平行于所述第一及第二条带且垂直于所述第一第二区域互连层以及所述第二第二区域互连层。
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