TWI574411B - 具有電晶體區域互連之半導體設備 - Google Patents

具有電晶體區域互連之半導體設備 Download PDF

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TWI574411B
TWI574411B TW101126924A TW101126924A TWI574411B TW I574411 B TWI574411 B TW I574411B TW 101126924 A TW101126924 A TW 101126924A TW 101126924 A TW101126924 A TW 101126924A TW I574411 B TWI574411 B TW I574411B
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transistor
layer
interconnect layer
gate
region
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TW201324777A (zh
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馬赫布卜 拉希德
艾琳Ｙ 林
史帝芬 壽思
傑夫 金
鎮 源
馬可 塔拉比亞
史考特 約翰遜
撒柏瑞瑪尼 肯格日
蘇雷什 芬卡特桑
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格羅方德半導體公司
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Description

具有電晶體區域互連之半導體設備
本發明大體有關於半導體設備，且更特別的是，有關於半導體設備的電晶體區域互連。
隨著半導體設備的尺寸持續減小，製作標準單元庫邏輯設備(例如，掃描D正反器(scan-D flip-flop)與多工器)的能力變得越來越困難。特別是在20奈米節點的情形下，微影的限制導致標準單元庫設備的縮放(scaling)不足。電晶體的交互耦合對於關鍵標準單元庫設備的縮放很重要。若無交互耦合，邏輯縮放會佔用更多半導體設備的面積。此外，利用標準金屬層的傳統交互耦合也會佔據大量的面積。由於會導致半導體設備更大或半導體設備的機能更少，所以這兩種情形都不合意。
因此，最好提供電晶體的交互耦合而不依賴標準金屬層即可產生標準單元庫設備同時保留半導體設備面積。此外，由以下結合附圖及以上描述的詳細說明和隨附申請專利範圍可明白本發明的其他合意特徵及特性。
提供一種用於實現至少一個邏輯元件的半導體設備。在本發明之一態樣中，該半導體設備包含半導體基板，其係具有形成於該半導體基板上的第一電晶體與第二電晶體。該等電晶體各包含源極、汲極及閘極。溝槽矽化物層使該第一電晶體的源極或汲極中之一者電氣連接至該第二 電晶體的源極或汲極中之一者。
在本發明之另一態樣，該半導體設備包含半導體基板，其係具有配置於該基板上的第一電晶體與第二電晶體。該等電晶體各包含源極、汲極及閘極。第一CB層電氣連接至該第一電晶體的閘極。第二CB層電氣連接至該第二電晶體的閘極。CA層在第一端、第二端之間縱向延伸。該第一CB層係與該CA層之該第一端鄰接地電氣連接。該第二CB層係與該CA層之該第二端鄰接地電氣連接。
在本發明之又一態樣，半導體設備包含半導體基板，其係具有配置於該基板上的第一電晶體與第二電晶體。該等電晶體各包含閘極，其中該等閘極大體相互平行地縱向延伸。CB層使該第一及該第二電晶體的閘極電氣連接以及形成鋸齒形狀。
以下的詳細說明在本質上只是示範而非旨在限制本發明或本發明的應用或用途。此外，此外，希望不受【先前技術】或【實施方式】之中的任何理論約束。
在此描述半導體設備20，其係圖示於附圖，其中類似的元件用相同的元件符號表示。熟諳此藝者周知，半導體設備20可為積體電路(未個別編號)之一部份。
請參考第1圖，半導體設備20包含半導體基板22。半導體設備20包含複數個電晶體24。具體言之，在圖示具體實施例中，電晶體24為場效電晶體(FET)，且更特別的是，金屬氧化物半導體場效電晶體(MOSFET)。電晶體24 各包含源極26、汲極28及閘極30。
源極26及汲極28均用熟諳此藝者所習知的技術形成於基板22中及/或上。在圖示具體實施例中，源極26及汲極28經形成為凸起源極26及汲極28，亦即，源極26及汲極28至少有一部份形成於基板22上方。在圖示於第1圖的組態中，凸起源極26及汲極28各高出基板22約15奈米。不過，可替換地實現其他的尺寸。熟諳此藝者明白可用嵌入式矽/鍺(eSiGe)技術來形成凸起源極26及汲極28。當然，可實施其他的技術以形成凸起源極26及汲極28。此外，在其他具體實施例中(未圖示)，可能不使源極26及汲極28凸出基板22。
閘極30通常使用熟諳此藝者所習知的技術形成於基板22上方。在圖示具體實施例中，配置基板22上方的閘極30主要由常被稱作多晶矽或以PolySi簡稱的複晶矽形成。不過，閘極30也可由其他的材料形成，例如，高k金屬。在圖示於第1圖的組態中，閘極30高出基板22約35奈米。不過，可替換地實現閘極30的其他尺寸。
參考第2圖可見，閘極30形成為大體相互平行的線性條帶(linear strip)31。條帶31中可形成間隙32使得沿著各個條帶31可縱向配置一個以上的閘極30。可用熟諳此藝者容易明白的切割遮罩技術(cut mask technique)來形成間隙32。
請參考第1圖及第3圖，半導體設備20包含配置於電晶體24之源極26、汲極28及閘極30上方的至少一個金 屬層33，如熟諳此藝者所知。金屬層33有助於設備20的各個邏輯元件與設備20的其他邏輯元件及設備20以外的其他系統電氣通訊。熟諳此藝者也明白，金屬層33照慣例是以M1、M2等等標稱。在圖示於第1圖的組態中，配置高出基板22約165奈米的一個金屬層33。不過，可替換地實現金屬層33的其他距離及尺寸。
半導體設備20更包含至少一個區域互連層34、36以選擇性地使電晶體24的源極26、汲極28及閘極30連接至其他電晶體24的其他源極26、汲極28及閘極30。至少一個區域互連層34、36也可選擇性地連接至至少一個金屬層33。至少一個區域互連層34、36配置於至少一個金屬層33與基板22之間。換言之，相對於基板22，金屬層33係配置於至少一個區域互連層34、36上方。圖示具體實施例的至少一個區域互連層34主要由鎢形成。在其他具體實施例中，至少一個區域互連層34、36主要由銅形成。不過，區域互連層34、36可由其他元素或化合物形成或包含。
以下描述圖示於附圖的各個半導體設備20實施例有不同的形狀、配置，以及至少一個區域互連層34、36的電氣連接。第一區域互連層34在此被稱作CA層34，以及第二區域互連層36在此被稱作CB層36。當然，半導體設備20中可實現多個CA層34及多個CB層36以及也可實現其他的區域互連層(未圖示)。通常，CA層(或數個)34電氣連接至源極26或汲極28同時CB層(或數個)36電氣連接至閘極30。不過，不應把這類組態視為限制。事實上，在下 述具體實施例中之一些中，CA層(或數個)34及/或CB層(或數個)36可能不連接至源極26、汲極28或閘極30。
利用圖示具體實施例的CA、CB層34、36可產生各種標準單元，例如，掃描D正反器。在先前技術中，金屬層常用來提供掃描D正反器的連接。利用CA、CB層34、36(經配置成比典型金屬層還要靠近基板)，相較於先前技術的設備，所得掃描D正反器有減少的面積。
半導體設備20更可包含一個或多個溝槽矽化物層37。溝槽矽化物層37可用來使電晶體24的源極26及/或汲極28電氣連接至CA或CB層34、36中之一個，通常為CA層，如第1圖所示。因此，溝槽矽化物層37夾在CA或CB層34、36中之一個與電晶體24的源極26或汲極28中之至少一個之間。溝槽矽化物層37的形成係藉由切割深至基板22的電介質(未圖示)溝槽(未個別編號)以及用自對準矽化物材料(salicide material)填滿溝槽。例如，該自對準矽化物材料可為金屬，例如鎳、鈷或鎢。
第1圖組態的溝槽矽化物層37有約50奈米的高度。第1圖的CA層34用溝槽矽化物層37支撐以及有約40奈米的高度。第1圖的CB層36有約70奈米的高度。第1圖的CA層34及CB層36對於基板22大體同高。此外，由第1圖可見，圖示具體實施例的CA、CB層34、36高出基板22不超過105奈米。當然，在取決於任意多個因素的替代具體實施例中，溝槽矽化物層37、CA層34及CB層36的高度及尺寸可不同。
半導體設備20可包含複數個通孔38以選擇性地提供CA或CB層34、36與至少一個金屬層33的電氣連接。因此，通孔38中之一個可配置於至少一個金屬層33與CA或CB層34、36中之一者之間。通孔38主要由金屬形成，例如銅。不過，也可使用其他的金屬或導電材料。第1圖之組態的通孔38有約60奈米的高度。
在第一具體實施例中，如第4圖所示，半導體設備20至少包含第一電晶體24a與第二電晶體24b。半導體設備20包含CA層34與CB層36。CA層34電氣連接至第一電晶體24a的源極26a或汲極28a中之至少一者。CB層36電氣連接至電晶體24a、24b的閘極30中之至少一者。取決於特定應用，CB層36可電氣連接至電晶體24a、24b的閘極30。第一及CB層34、36也可相互電氣連接。
在第一具體實施例中，CA層34在第一端40和第二端42之間延伸。CB層36大體配置於CA層34在末端40、42之間的中央44。更特別的是，CB層36的末端46大體配置在CA層34的中央44。因此，從上面俯視，CA及CB層34、36形成一長‘T’形狀。
半導體設備20的第二具體實施例與第一具體實施例實質類似，但是更包含配置在CA層34與第一電晶體24a的源極26或汲極28中之至少一者之間的溝槽矽化物層37。此配置也可再參考第1圖。
在第三具體實施例中，如第5圖所示，半導體設備20至少包含第一電晶體24a與第二電晶體24b。半導體設備 20包含第一CA層34a與CB層36。第一CA層34a電氣連接至第一電晶體24a的源極26a或汲極28a中之至少一者。CB層36電氣連接至電晶體24a、24b的閘極30a、30b中之至少一者。取決於特定應用，CB層36可電氣連接至電晶體24a、24b的閘極30a、30b。CA及CB層34、36也相互電氣連接。
在第三具體實施例中，如同第一具體實施例，CA層34在第一端40、第二端42之間延伸。不過，在第三具體實施例中，CB層36經配置成與末端40、42中之一個鄰接。因此，從上面俯視，CA及CB層34、36形成一長‘L’形狀。第三具體實施例的長‘L’形狀允許把CB層36配置成與第二CA層48分離以防CB層36與第二CA層48之間的導電。
請參考第6圖及第7圖，半導體設備20的第四具體實施例包含形成於基板22上的第一電晶體24a、第二電晶體24b及第三電晶體24c。該等電晶體24係由第一電晶體24a至第三電晶體24c依序配置。設備20更可包含第四電晶體24d，其中該等電晶體24係由第一電晶體24a至第四電晶體24d依序配置。
第一CB層36a電氣連接至第一電晶體24a的閘極30a，以及第二CB層36b電氣連接至第三電晶體24c的閘極30c。CA層34使第一CB層36a與第二CB層36b相互電氣連接。因此，第一電晶體24a的閘極30a與第三電晶體24c的閘極30c通過CB層36a、36b及CA層34相互電氣 連接。
CA層34與第二電晶體24b的閘極30b電氣隔離。因此，CA層34形成跨過第二電晶體24b之閘極30b的“橋狀物”或“跳線”。一個或多個絕緣層44可夾在CA層34與第二電晶體24b的閘極30之間。一個或多個絕緣層44也可夾在CA層36與基板22之間。
取決於特定邏輯元件的需要，第二CB層36b也可電氣連接至第四電晶體24d的閘極30。此外，CA層34也可電氣連接至電晶體24a、24b、24c中之一個的源極26或汲極28中之至少一者。如第6圖及第7圖所示，相對於基板22，CA層34及CB層36a、36b係配置於電晶體24a、24b、24c、24d的閘極30上方。
在第五具體實施例中，半導體設備20包含半導體基板22，其係具有配置於基板22上的第一電晶體24a及第二電晶體24b，如第8圖所示。第一CB層36a電氣連接至第一電晶體24a的閘極30a，以及第二CB層36b電氣連接至第二電晶體24b的閘極30b。CA層34在第一端40、第二端42之間縱向延伸。第一CB層36a與CA層34之第一端40鄰接地電氣連接至CA層34。第二CB層36b與CA層34之第二端42鄰接地電氣連接至CA層34。
第一電晶體24a的閘極30a縱向延伸成為第一線性條帶31a之一部份，以及第二電晶體24b的閘極30b縱向延伸成為第二線性條帶31b之一部份。第一、第二條帶31a、31b大體相互平行以及彼此隔開。CA層34大體垂直於第 一、第二CB層36a、36b。因此，CA層34與條帶31a、31b大體平行地延伸以及配置於條帶31a、31b之間。因此，從上面俯視，CA層34及CB層36a、36b一起形成鋸齒形狀或大體S形狀。
第五具體實施例的半導體設備20更可包含第三電晶體24c與第四電晶體24d。第三電晶體24c的閘極30c縱向延伸成為第一條帶31a之一部份，以及第四電晶體24d的閘極30d縱向延伸成為第二條帶31b之一部份。間隙32使第一電晶體24a的閘極30a與第三電晶體24c的閘極30c分離，以及使第二電晶體24b的閘極30與第四電晶體24d的閘極30分離。因此，第一、第二電晶體24a、24b的閘極30彼此在對角線的角落上，而CA層34延伸越過間隙32。
在第六具體實施例中，如第9圖所示，半導體設備20包含半導體基板22，其係具有第一電晶體24a與配置於基板22上的第二電晶體24b。電晶體24a、24b的閘極30a、30b大體相互平行地縱向延伸。第一閘極30a形成為第一線性條帶31a之一部份，以及第二閘極30b形成為第二線性條帶31b之一部份。單一CB層36電氣連接至第一、第二電晶體24a、24b的閘極30。電晶體24a、24b的閘極30a、30b可能不直接相互鄰接。因此，CB層36形成鋸齒形以使電晶體24a、24b電氣連接。
具體言之，如第9圖所示，設備20包含第三電晶體24c與第四電晶體24d。第三電晶體24c的閘極30c縱向延 伸成為第一條帶31a之一部份，以及第四電晶體24d的閘極30d縱向延伸成為第二條帶31b之一部份。第一間隙32a使第一電晶體24a的閘極30a與第三電晶體24c的閘極30c分離。第二間隙32b使第二電晶體24b的閘極30b與第四電晶體24d的閘極30d分離。第六具體實施例的間隙32a、32b未彼此對齊。
請參考第2圖及第10圖，第七具體實施例的半導體設備20包含第一電晶體24a與第二電晶體24b。溝槽矽化物層37使第一電晶體24a的源極26a或汲極28a電氣連接至第二電晶體24b的源極26b或汲極28b。具體言之，第10圖圖示為n型FET的第一電晶體24a與為p型FET的第二電晶體24b，以及電晶體24a、24b的凸起汲極28a、28b經由溝槽矽化物層37相互電氣連接。
第一電晶體24a的閘極30a與第二電晶體24b的閘極30b由共用線性條帶31形成。因此，閘極30a、30b彼此呈線性地延伸。溝槽矽化物層37配置在閘極30a、30b的一側。亦即，溝槽矽化物層37不越過閘極30a、30b或共用線性條帶31同時仍使電晶體24a、24b的汲極28a、28b電氣連接。換言之，溝槽矽化物層37不需要越過由線性條帶31形成的“複合邊界”。此配置可用來產生掃描D正反器。相較於先前技術的設備，所得之掃描D正反器有減少的面積。當然，熟諳此藝者明白，此配置可用來製作掃描D正反器以外的邏輯設備。
第七具體實施例的半導體設備20也可包含電氣連接 至電晶體24a、24b之各個閘極30a、30b的單邊接觸(未圖示)。利用單邊接觸，亦即，不延伸遍及閘極30a、30b之整個寬度的接觸，可減少溝槽矽化物層37與閘極30a、30b發生介質擊穿(dielectric breakdown)的風險。
儘管已用上文詳細說明至少一示範具體實施例，然而應瞭解，仍有許多變體。也應瞭解，該(等)示範具體實施例只是實施例而非旨在以任何方式限制本發明的範疇、適用性或組態。反而，上述詳細說明是要讓熟諳此藝者有個方便的發展藍圖用來具體實現本發明的示範具體實施例，應瞭解，示範具體實施例提及之元件的功能及配置可做出不同的改變而不脫離如隨附申請專利範圍及其合法等效物所述的範疇。
20‧‧‧半導體設備
22‧‧‧半導體基板
24‧‧‧電晶體
24a‧‧‧第一電晶體
24b‧‧‧第二電晶體
24c‧‧‧第三電晶體
24d‧‧‧第四電晶體
26、26a、26b‧‧‧源極
28、28a、28b‧‧‧汲極
30、30a至30d‧‧‧閘極
31‧‧‧線性條帶
31a‧‧‧第一線性條帶
31b‧‧‧第二線性條帶
32‧‧‧間隙
32a‧‧‧第一間隙
32b‧‧‧第二間隙
33‧‧‧金屬層
34‧‧‧CA層
34a‧‧‧第一CA層
36‧‧‧CB層
36a‧‧‧第一CB層
36b‧‧‧第二CB層
37‧‧‧溝槽矽化物層
38‧‧‧通孔
40‧‧‧第一端
42‧‧‧第二端
44‧‧‧中央
46‧‧‧末端
48‧‧‧第二CA層
以下結合附圖描述本發明，其中類似的元件用相同的元件符號表示。
第1圖為半導體設備之一部份的側視截面圖；第2圖為半導體設備之一個具體實施例的上視圖，其係圖示電晶體的閘極、各個區域互連層及溝槽矽化物層；第3圖為半導體設備之另一具體實施例的上視圖，其係圖示配置於電晶體之閘極上方的金屬層以及各個區域互連層；第4圖為半導體設備之第一具體實施例的部份上視圖；第5圖為半導體設備之第三具體實施例的部份上視圖； 第6圖為半導體設備之第四具體實施例的部份上視圖；第7圖根據第6圖之直線7-7繪出半導體設備之第四具體實施例的側視截面圖；第8圖為半導體設備之第五具體實施例的部份上視圖；第9圖為半導體設備之第六具體實施例的部份上視圖；以及第10圖根據第2圖之直線10-10繪出半導體設備之第七具體實施例的部份側視圖。
20‧‧‧半導體設備
22‧‧‧半導體基板
24a‧‧‧第一電晶體
24b‧‧‧第二電晶體
28a、28b‧‧‧汲極
30a、30b‧‧‧閘極
31‧‧‧線性條帶
32‧‧‧間隙
37‧‧‧溝槽矽化物層

Claims (8)

  1. 一種半導體設備，係包含：半導體基板；配置於該基板上的第一電晶體及第二電晶體；該等電晶體各包含源極、汲極及閘極；電氣連接至該第一電晶體之該閘極的第一之第二區域互連層；電氣連接至該第二電晶體之該閘極的第二之第二區域互連層；以及在第一端及第二端之間縱向延伸的第一區域互連層；其中，該第一之第二區域互連層係與該第一區域互連層之該第一端電氣連接；該第二之第二區域互連層係與該第一區域互連層之該第二端電氣連接；該第一電晶體之該閘極係沿著第一線縱向延伸，以及該第二電晶體之該閘極係沿著第二線縱向延伸，其中，該第一線及該第二線大體相互平行以及彼此隔開；以及該第一區域互連層係對於該等線大體平行地延伸並大體垂直該第一之第二區域互連層與該第二之第二區域互連層；以及其中該第一之第二區域互連層縱向延伸越過該第一電晶體之該閘極，該第二之第二區域互連層縱向延伸越過該第二電晶體之該閘極。
  2. 如申請專利範圍第1項所述之半導體設備，其中，該第一區域互連層係配置於該等閘極之間。
  3. 如申請專利範圍第2項所述之半導體設備，其中，該第一區域互連層定義對於該等線平行地延伸的長度大於對於該等線平行地延伸的該等第二區域互連層的長度。
  4. 如申請專利範圍第3項所述之半導體設備，更包含具有沿著該第一線縱向延伸之閘極的第三電晶體，以及具有沿著該第二線縱向延伸之閘極的第四電晶體。
  5. 如申請專利範圍第4項所述之半導體設備，其中，該第一及該第三電晶體的該等閘極係以間隙而分離，以及該第二及該第四電晶體的該等閘極係以間隙而分離。
  6. 如申請專利範圍第5項所述之半導體設備，其中，該第一區域互連層係延伸越過該間隙。
  7. 如申請專利範圍第1項所述之半導體設備，其中，該第一區域互連層於該基板上方延伸小於105奈米。
  8. 一種半導體設備，係包含：半導體基板；配置於該基板上的第一電晶體及第二電晶體；該等電晶體各包含源極、汲極及閘極；電氣連接至該第一電晶體之該閘極的第一之第二區域互連層；電氣連接至該第二電晶體之該閘極的第二之第二區域互連層；以及在第一端及第二端之間縱向延伸的第一區域互連 層；其中，該第一之第二區域互連層係與該第一區域互連層之該第一端電氣連接；至少一溝槽矽化物層使該第一電晶體和該第二電晶體其中一個的該源極及/或該汲極電氣連接至該第一區域互連層，其中，該溝槽矽化物層夾在該第一區域互連層以及與該第一電晶體和該第二電晶體其中一個的該源極及/或該汲極之間；該第二之第二區域互連層係與該第一區域互連層之該第二端電氣連接；該第一電晶體之該閘極係沿著第一線縱向延伸，以及該第二電晶體之該閘極係沿著第二線縱向延伸，其中，該第一線及該第二線大體相互平行以及彼此隔開；以及該第一區域互連層係對於該等線大體平行地延伸並大體垂直該第一之第二區域互連層與該第二之第二區域互連層；以及其中該第一之第二區域互連層縱向延伸越過該第一電晶體之該閘極，該第二之第二區域互連層縱向延伸越過該第二電晶體之該閘極。
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