CN103140923B - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN103140923B
CN103140923B CN201280002335.6A CN201280002335A CN103140923B CN 103140923 B CN103140923 B CN 103140923B CN 201280002335 A CN201280002335 A CN 201280002335A CN 103140923 B CN103140923 B CN 103140923B
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Prior art keywords
semiconductor packages
connecting rod
strip
joint pad
chip
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CN201280002335.6A
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CN103140923A (zh
Inventor
陈南璋
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MediaTek Inc
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MediaTek Inc
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Abstract

本发明提供一种半导体封装结构。半导体封装结构（10）包括芯片接合垫（14）；第一半导体芯片（12a），安置于该芯片接合垫（14）上；多个引线，该多个引线（16）包含多个电源引线并且沿该芯片接合垫（14）外围边缘设置；至少一个连接杆（142），用于支撑该芯片接合垫（14）；第一电源条（160a），设置于该连接杆（142）的一侧；第二电源条（160b），设置于该连接杆（142）的另一侧；以及连接件（28），跨过该连接杆（142）并将该第一电源条（160a）与该第二电源条（160b）电性连接。本发明所提出的半导体封装结构，能够改善电源供应变化以及抑制电源噪声。

Description

半导体封装
交叉引用
本申请享有2011年09月30日提出的申请号为61/541，235的美国临时申请以及2012年09月26日提出的申请号为13/626，899的美国专利申请的优先权，上述申请的全文作为本申请的引用基础。
技术领域
本发明是有关于集成电路封装技术，特别是有关于一种具有电源条(powerbar)或电源环(powerring)的引线框架的半导体封装，该封装能够改善电源供应变化以及抑制电源噪声。
背景技术
半导体芯片（Semiconductordie）通常封装入塑料封装以在恶劣环境下提供保护，并且塑料封装能够使得半导体芯片与基底（substrate）或电路板之间电性连接。这种集成电路（integratedcircuit）封装典型地包括金属基底或引线框架（leadframe）、安装在引线框架的芯片接合垫（diepad）上的半导体芯片以及将半导体芯片上的接合垫电性耦接至引线框架的内部引线的接合线。引线框架、接合线以及半导体芯片典型地封装于塑封料中。
后端封装产业的技术发展趋势可以概括为“更小空间拥有更多功能的发展趋势”。集成电路芯片（integratedcircuitchip）复杂度越来越高，使得引线框架封装的外部连接引脚的数目增加。由于引脚数增加，封装的成本也相应地增加。
进一步来说，由于半导体芯片集成度和性能的增加，输入/输出信号的电源噪声的影响是显著的。因此，在芯片操作期间需要提供稳定的供应电压。此外，在某些情况下，从芯片上的接合垫延伸的一些接合线接合至封装中引线框架的单一内部引线。改善接合至单一信号引线的拥挤引线导致可靠性和合格率问题。
由上述可知，在封装产业中强烈需要提供合算的改进的半导体封装结构和引线框架封装，使其特别适合高速半导体芯片，并能够改善电源供应变化和抑制电源噪声。
发明内容
有鉴于此，本发明提出一种半导体封装。
依据本发明一实施方式，提供一种半导体封装，包括：芯片接合垫，第一半导体芯片，安置于芯片接合垫上；多个引线，该多个引线包含多个电源引线并且沿该芯片接合垫外围边缘设置；至少一个连接杆，用于支撑芯片接合垫；第一电源条，设置于该连接杆的一侧；第二电源条，设置于该连接杆的另一侧；以及跨过连接杆的连接件，将第一电源条与第二电源条电性连接。
依据本发明另一实施方式，提供一种半导体封装，包括：芯片接合垫，至少一个半导体芯片安置于该芯片接合垫上；多个内部引线，在第一水平面上并且沿该芯片接合垫的外围边缘设置；多个连接杆，用于支撑芯片接合垫；以及围绕芯片接合垫的电源环。电源环包括在该多个连接杆之间延伸的多个电源条。且该多个电源条通过跨过该多个连接杆的多个连接件电性连接在一起。
本发明所提出的半导体封装结构，能够改善电源供应变化以及抑制电源噪声。
在参阅随后具体实施方式的不同图示与详尽描述后，本领域的技术人员便可了解本发明的上述内容与其他发明目的。
附图说明
附上附图以进一步理解本发明，并将其纳入构成本发明的一部分。附图和相关描述用于举例说明本发明的实施方式，并对本发明的原理进行解释。在附图中:
图1为根据本发明实施方式的引线框架封装的俯视示意图；
图2为图1中引线框架封装的相关部分的放大俯视图；
图3为沿图1中I-I’线的剖面示意图；
图4为根据本发明另一实施方式的引线框架封装的相关部分的放大俯视图；以及
图5为根据本发明另一实施方式的引线框架的剖面图。
需要注意的是，所有的图形都是示意性的。为了能更清楚和方便说明起见，附图的部分的相关尺寸或比例均被放大或缩小。相同的参考符号通常用于修改和不同的实施方式中相同或相似特征之间的引用。
具体实施方式
如上所述，本发明提供了一种改进的半导体封装，其适用于（但不限于）薄型方型扁平式(Low-ProfileQuadFlatPack，LQFP)封装、薄四方扁平(ThinQuadFlatPack，TQFP)封装、方形扁平无引脚封装(QuadFlatNon-leaded，QFN)封装、双边扁平无引脚(DualFlatNo-lead，DFN)封装、多区域(multi-zone)方形扁平无引脚封装、多芯片覆晶(multi-dieflip-chip)封装以及其他应用的封装技术。
请参考图1~图3。图1为根据本发明实施方式的引线框架封装10的俯视示意图。图2为图1中引线框架封装10的相关部分的放大俯视图。图3为沿图1中I-I’线的剖面示意图。如图1~图3所示，一般说来，引线框架封装10包括至少一个半导体芯片12a，安装于芯片接合垫14上，并且通过使用粘着剂24（例如，银膏或环氧树脂）粘附于芯片接合垫14的顶面14a。根据本发明一个实施例，芯片接合垫14的底面14b置于封装体内且表面是暴露的。芯片接合垫14的暴露的底面14b有助于消散半导体芯片12a产生的热量，这就是暴露型芯片接合垫或片盘（E-pad）结构。典型地，芯片接合垫14的暴露的底面14b可以电性连接至印刷电路板（printedcircuitboard，PCB）的接地层（groundlayer）。根据本发明一个实施例，四条细长的连接杆(connectingbar)142a～142d分别从引线框架封装10的四角向内延伸以支撑芯片接合垫14。引线16包括内部引线116和外部引线126，且沿芯片接合垫14的外围边缘设置，并用于提供半导体芯片12a与其他装置（例如，电路板）之间的电性连接。半导体芯片12a以及包括芯片接合垫14和内部引线116的引线框架均封装于塑封料30中。
根据本发明一个实施例，半导体芯片12a可以为（但不限于）电视芯片或用于数字电视应用的系统芯片(system-on-a-chip)。根据本发明一个实施例，引线框架封装10可以进一步包括半导体芯片12b。半导体芯片12a和半导体芯片12b并行放置于芯片接合垫14的同一平面（例如，顶面14a）。举例来说，半导体芯片12b可以是（但不限于）内存技术标准为DDR2或DDR3的动态随机存取存储器（DRAM）芯片。根据本发明一个实施例，半导体芯片12b可以位于与半导体芯片12a相比距离双层印刷电路板的核心电源轨VCCK（图未示）更远的位置。根据本发明一个实施例，多行(row)接合垫123可以沿半导体芯片12a有效的顶面121的四个侧边布置。
根据本发明一个实施例，内部引线116沿芯片接合垫14的外围边缘设置于第一水平面。引线框架封装10可以进一步包括接地条(groundbar)130，布置在从第一水平面下沉至较低的第二水平面上，并且该第二水平面的位置在内部引线116和芯片接合垫14之间，以及多个下沉分流条144(tiebar)将接地条130与芯片接合垫14连接在一起。根据一个实施例，接地条130沿芯片接合垫14至少一个外围边缘延伸并且整体连接于连接杆142（举例来说，该连接杆142包括连接杆142a~142d）中的一个连接杆。因此，接地条130、连接杆142和芯片接合垫14具有相同的电压等级（即接地电平）。
在图1中，举例来说，引线框架封装10包括第一接地条130a，沿芯片接合垫14的一个外围边缘部分延伸，第二接地条130b沿芯片接合垫14的两个外围边缘部分延伸，第三接地条130c沿芯片接合垫14的两个外围边缘部分延伸，以使第一接地条、第二接地条和第三接地条部分包围芯片接合垫14。第一接地条130a具有连接第一连接杆142a的末端，且第一接地条130a由下沉分流条144a整体连接至芯片接合垫14。间断（discontinuity）或缺口132在第一接地条130a和第二接地条130b之间形成。第二接地条130b由下沉分流条144b整体连接至芯片接合垫14并且整体连接至第二连接杆142b。同样的，在第二接地条130b和第三接地条130c之间提供间断或缺口132。第三接地条130c由下沉分流条144c整体连接至芯片接合垫14并且整体连接至第三连接杆142c。在这种情况下，在半导体芯片12b周围不提供接地条。
根据一个实施例，引线框架封装10进一步包括电源条(powerbar)160，置于一个连接杆142（举例来说，该连接杆142包括连接杆142a~142d）的任何一侧，而且不与连接杆142接触。即，电源条160与连接杆142电性隔离且提供具有与连接杆142的接地电平的不同电压电平的电源信号。根据一个实施例，举例来说，电源条160与在第一水平面的内部引线116齐平且沿芯片接合垫14的外围边缘延伸。每一个电源条160分别整体连接至至少一个电源引线(powerlead)16a，该电源引线16a指定用于供应电源电压（例如，核心电源）。
在图1中，举例来说，第一电源条160a在第一连接杆142a与第二连接杆142b之间延伸，而且大体上平行于第一接地条130a。第一电源条160a整体连接至电源引线16a。第二电源条160b在第二连接杆142b和第三连接杆142c之间延伸，而且大体上平行于第二接地条130b。第二电源条160b整体连接至两条电源引线16a。第一电源条160a通过使用跨过第二连接杆142b的连接件(connectionmember)28电性连接至第二电源条160b。举例来说，连接件28可以包括接合线、传导带、或0值电阻（即，0Ω电阻），或其他类似物。连接件28不与第二连接杆142b接触。第三电源条160c在第三连接杆142c与第四连接杆142d之间延伸，而且大体上平行于第三接地条130c。第三电源条160c整体连接至单一电源引线16a。同样的，第二电源条160b通过跨过第三连接杆142c的连接件28电性连接至第三电源条160c。
第四电源条160d在第一连接杆142a与第四连接杆142d之间，而且大体上沿芯片接合垫14的三个外围边缘延伸。第四电源条160d部分包围芯片接合垫14且设置于临近半导体芯片12b。如图1所示，第四电源条160d电性连接至三条电源引线16a。第四电源条160d通过使用跨过第四连接杆142d的连接件28电性连接至第三电源条160c。也就是说，第一连接杆142a的一侧设有第一电源条160a，另一侧设有第四电源条160d；第二连接杆142b的一侧设有第二电源条160b，另一侧设有第一电源条160a；第三连接杆142c的一侧设有第三电源条160c，另一侧设有第二电源条160b；第四连接杆142d的一侧设有第四电源条160d，另一侧设有第三电源条160c。选择性地，可将解耦电容50安置在第四电源条160d和第四连接杆142d之间用于抑制电源噪声。同样的，第四电源条160d可以通过使用跨过第一连接杆142a的连接件28电性连接至第一电源条160a。可以选择解耦电容50安置在第四电源条160d和第一连接杆142a之间用于抑制电源噪声。根据本实施例，第一电源条、第二电源条、第三电源条和第四电源条可以电性连接在一起，以形成可以完全包围芯片接合垫14的连续的电源环，该电源环可以降低电源阻抗和电源噪声。然而，应该理解在某些时候第一电源条、第二电源条、第三电源条以及第四电源条可以不必全部电性耦接在一起。
根据一个实施方式，在半导体芯片12a上的接合垫(bondpad)123，其被认为是输入/输出接合垫（I/Opad），通常包括接地接合垫(groundpad)123a、电源接合垫(powerpad)123b以及信号接合垫(signalpad)123c等。接合垫123通过接合线(bondwire)18电性耦接至相对应的接地条130、内部引线116或电源条160。举例来说，接地接合垫123a通过接合线18a电性耦接至接地条130，电源接合垫123b通过接合线18b电性耦接电源条160，并且信号接合垫123c通过接合线18c电性耦接至内部引线116。由于电源条的较大区域可以接合更多接合线，因此可以改善接合至单一信号引线的拥挤引线导致的可靠性和合格率问题。
图4为根据本发明另一实施方式的引线框架封装的相关部分的放大俯视图。图5为根据本发明另一实施方式的引线框架的剖面图。其中相同或相似的区域、层以及元件指定相同或相似的编号。如图4和图5所示，连接杆142具有下沉结构(downsetstructure)242。在电源引线16a和电源条160之间提供下沉结构260。使得电源条160能够与接地条130共面，即电源条160中至少一个电源条与接地条130齐平。解耦电容50a安置在电源条160和下沉连接杆142之间且解耦电容50b安置在电源条160和接地条130之间。
总之，本发明至少包括如下优点：1）由于更多的电源引线可以接合在电源条的较大区域上，可以获得低电源阻抗。2）由于将解耦电容纳入封装使得解耦路径较短。3）由于减轻了电源条上的电源引线密度而获得更高的封装合格率。4）由于增加额外的电源环来减少电源阻抗，可实现使用较少的电源引线。
虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，当可做些许更动与润饰，因此本发明的保护范围应当以权利要求书所界定的保护范围为准。

Claims (20)

1.一种半导体封装，其特征在于，包括：
芯片接合垫；
第一半导体芯片，安置于该芯片接合垫上；
多个引线，该多个引线包含多个电源引线并且沿该芯片接合垫外围边缘设置；
至少一个连接杆，用于支撑该芯片接合垫；
第一电源条，设置于该连接杆的一侧；
第二电源条，设置于该连接杆的另一侧；以及
连接件，跨过该连接杆并将该第一电源条与该第二电源条电性连接；
其中，通过该连接件连接的该第一电源条与该第二电源条是等电位的。
2.根据权利要求1所述的半导体封装，其特征在于，
该第一电源条整体连接于该多个电源引线的至少其中之一。
3.根据权利要求1所述的半导体封装，其特征在于，
该第二电源条整体连接于该多个电源引线的至少其中之一。
4.根据权利要求1所述的半导体封装，其特征在于，
该第一电源条和该第二电源条均与该连接杆电性隔离。
5.根据权利要求1所述的半导体封装，其特征在于，
该连接件包括至少一个接合线、传导带、或0值电阻。
6.根据权利要求1所述的半导体封装，其特征在于，包括，
第二半导体芯片，安置于该芯片接合垫上。
7.根据权利要求1所述的半导体封装，其特征在于，包括，
至少一个接地条，沿该芯片接合垫的外围边缘部分延伸。
8.根据权利要求7所述的半导体封装，其特征在于，
该接地条整体连接于该连接杆。
9.根据权利要求7所述的半导体封装，其特征在于，
该接地条由下沉分流条整体连接至该芯片接合垫。
10.根据权利要求7所述的半导体封装，其特征在于，
该第一电源条和该第二电源条的至少其中之一与该接地条齐平。
11.根据权利要求10所述的半导体封装，其特征在于，
至少一个解耦电容安置于该第一电源条和该第二电源条的至少其中之一与该接地条之间。
12.根据权利要求1所述的半导体封装，其特征在于，
该第一电源条和该第二电源条均与该引线的内部引线齐平。
13.根据权利要求1所述的半导体封装，其特征在于，包括，
至少一个解耦电容，安置于该连接杆与该第一电源条和该第二电源条的至少其中之一之间。
14.根据权利要求1所述的半导体封装，其特征在于，
该多个引线包括多个内部引线，该多个内部引线在第一水平面上并且沿该芯片接合垫外围边缘设置；
该半导体封装进一步包括，
至少一个接地条，布置在从该第一水平面下沉至第二水平面上，并且该第二水平面的位置在该多个内部引线和该芯片接合垫之间；
以及多个下沉分流条，将该至少一个接地条与该芯片接合垫连接在一起。
15.一种半导体封装，其特征在于，
芯片接合垫；
至少一个半导体芯片，安置于该芯片接合垫上；
多个内部引线，该多个内部引线在第一水平面上并且沿该芯片接合垫外围边缘设置；
多个连接杆，用于支撑该芯片接合垫；以及
围绕该芯片接合垫的电源环，其中该电源环包括在该多个连接杆之间延伸的多个电源条，且该多个电源条通过跨过该多个连接杆的多个连接件而电性连接在一起；
其中，通过该多个连接件连接的该多个电源条是等电位的。
16.根据权利要求15所述的半导体封装，其特征在于，
该电源环与该多个内部引线齐平。
17.根据权利要求15所述的半导体封装，其特征在于，
该电源环从该第一水平面下沉至第二水平面。
18.根据权利要求15所述的半导体封装，其特征在于，
该多个电源条与该多个连接杆电性隔离。
19.根据权利要求15所述的半导体封装，其特征在于，
至少一个解耦电容安置在该多个电源条中的一个电源条与该多个连接杆中的一个连接杆之间。
20.根据权利要求15所述的半导体封装，其特征在于，包括，
至少一个接地条，布置在从该第一水平面下沉至第二水平面上，并且该第二水平面的位置在该多个内部引线和该芯片接合垫之间，
以及多个下沉分流条，将该至少一个接地条与该芯片接合垫连接在一起。
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