CN103118483B - 电子组件 - Google Patents
电子组件 Download PDFInfo
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- CN103118483B CN103118483B CN201310002010.4A CN201310002010A CN103118483B CN 103118483 B CN103118483 B CN 103118483B CN 201310002010 A CN201310002010 A CN 201310002010A CN 103118483 B CN103118483 B CN 103118483B
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- 239000000758 substrate Substances 0.000 claims abstract description 71
- 239000010410 layer Substances 0.000 claims description 63
- 239000011469 building brick Substances 0.000 claims description 32
- 239000012790 adhesive layer Substances 0.000 claims description 24
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 20
- 229910052737 gold Inorganic materials 0.000 claims description 18
- 239000010931 gold Substances 0.000 claims description 18
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 230000001788 irregular Effects 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 6
- 235000012431 wafers Nutrition 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000000354 decomposition reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000012447 hatching Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000001962 electrophoresis Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
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- H—ELECTRICITY
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- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
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- G—PHYSICS
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13458—Terminal pads
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- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
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- H05K3/36—Assembling printed circuits with other printed circuits
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- H05K3/361—Assembling flexible printed circuits with other printed circuits
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- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
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- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
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- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
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- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
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- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4046—Through-connections; Vertical interconnect access [VIA] connections using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
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- H05K1/11—Printed elements for providing electric connections to or between printed circuits
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- H05K1/18—Printed circuits structurally associated with non-printed electric components
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- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
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- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
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Abstract
一种电子组件,包括一第一基板、至少一第一导电垫及多个第二导电垫。第一基板包括至少一基材层以及布设于基材层上的至少一导电线路层。第一导电垫设置于第一基板,且第一导电垫与导电线路层电性绝缘,第一导电垫上具有多个第一孔洞。这些第二导电垫设置于第一基板,且与导电线路层电性连接。
Description
技术领域
本发明是关于一种电子组件,特别是一种基板具有导电垫的电子组件。
背景技术
针对多媒体社会的急速进步,液晶显示器(LiquidCrystalDisplay,简称LCD)已经广泛地应用于中、小型可携式电视、影像电话、摄录放影机、笔记型电脑、桌上型显示器、平板电脑以及投影彩色电视等。
液晶显示器是包括有一显示模块,显示模块是包括一显示面板以及连接于显示面板的一电路板,电路板可透过搭接的方式来与显示面板达成电性连接的关系。详细来说,电路板上会设置有多个包括金箔层的导电垫,导电垫上设置有一导电胶,电路板透过导电胶而与连接于显示面板的一软性电路连接单元结合。并且于实务上,电路板上的这些导电垫仅有部分是与电路板的一线路层电性连接。而其余未与线路层电性连接的导电垫,则并无实质上的电性效果而可称为伪垫(DummyPad)。但由于金价上扬,且因伪垫一样包括有金箔层,如此将造成电路板的成本不必要地增加。
因此,便有将电路板取消设置伪垫的设计出现。但如此一来,当导电胶粘附于电路板上时,电路板上取消伪垫的区域与设有导电垫的区域之间便具有高度差的存在。如此,将造成导电胶于作业阶段贴附不良,进而影响电路板与软性电路连接单元于后续加工制程上的不良率。
发明内容
本发明在于提供一种电子组件,由此减少电路板的用金量以降低电路板的成本。
本发明所公开的电子组件,包括一第一基板、至少一第一导电垫及多个第二导电垫。第一基板包括至少一基材层以及布设于基材层上的至少一导电线路层。第一导电垫设置于第一基板,且第一导电垫与导电线路层电性绝缘,第一导电垫上具有多个第一孔洞。这些第二导电垫设置于第一基板,且电性连接导电线路层。
另包括一导电胶层,设置于该第一导电垫及所述第二导电垫上。
该导电胶层与该第一导电垫的接触面积为A,该导电胶层位于所述第一孔洞上的面积为B,且33%≤A/(A+B)≤60%。
该导电胶层与该第一导电垫的接触面积为A,该导电胶层位于所述第一孔洞上的面积为B,且33%≤A/(A+B)≤45%
另包括一第二基板以及一晶片,该晶片设置于该第二基板上,该第二基板叠设于该导电胶层上。
该第二基板为一软性电路板。
另包括一面板,连接该第二基板远离该第一基板的一端。
至少一该第二导电垫具有多个第二孔洞。
所述第一孔洞的外形为正圆孔、椭圆孔、矩形孔或不规则孔。
该第一基板为一印刷电路板。
该第一基板包括多个该基材层及多个该导电线路层,所述基材层及所述导电线路层是交错堆叠。
该第一导电垫或所述第二导电垫包括依序堆叠的一铜层、一镍层及一金层。
根据上述本发明所公开的电子组件,是通过第一导电垫(伪垫)上设置多个第一孔洞,以用以降低第一导电垫的整体体积,进而减少第一导电垫的含金量。如此,使得电子组件的成本得以降低。
有关本发明的特征、实作与功效,兹配合附图作最佳实施例详细说明如下。
附图说明
图1A为根据本发明一实施例的电子组件的结构组合图。
图1B为根据图1A的电子组件的结构分解图。
图1C为根据图1A的1C剖面线的剖视图。
图2A为根据图1B的第一导电垫的结构平面图。
图2B为根据本发明另一实施例的第一导电垫的结构平面图。
图2C为根据本发明另一实施例的第一导电垫的结构平面图。
图3为根据图1B的第一导电垫与导电胶层的叠合示意图。
图4为根据本发明另一实施例的第二导电垫的结构平面图。
附图标记说明
10电子组件
11第一基板
111基材层
112导电线路层
12第一导电垫
12a第一导电垫
12b第一导电垫
121第一孔洞
121a第一孔洞
121b第一孔洞
13第二导电垫
13a第二导电垫
131金层
132镍层
133铜层
134a第二孔洞
14导电胶层
15第二基板
16晶片
17面板
具体实施方式
请参照图1A至图2A,图1A为根据本发明一实施例的电子组件的结构组合图,图1B为根据图1A的电子组件的结构分解图,图1C为根据图1A的1C剖面线的剖视图,图2A为根据图1B的第一导电垫的结构平面图。
本实施例的电子组件10以平板电脑或液晶屏幕内的显示模块为例,但不以此为限。电子组件10包括一第一基板11、至少一第一导电垫12及多个第二导电垫13,其中第一导电垫12及第二导电垫13设置于第一基板11上。
第一基板11可为一印刷电路板(PrintedCircuitBoard,PCB),但不以此为限。第一基板11包括至少一基材层111以及布设于基材层111上的至少一导电线路层112。导电线路层112可电性连接于第一基板11上的多个电子元件(未绘示),如电容、电阻、电感等。
就本实施例而言,第一基板11包括多个基材层111及多个导电线路层112,这些基材层111及这些导电线路层112交错堆叠。上述基材层111的材质可以是但不限于玻璃纤维,而上述导电线路层112的材质可以是但不限于铜材。需注意的是,本实施例的第一基板11以包括多个基材层111及多个导电线路层112为例,但基材层111及导电线路层112的数量非用以限定本发明。譬如在其他实施例当中,第一基板也可以仅包括单一基材层以及布设于此基材层的单一导电线路层。
第一导电垫12设置于第一基板11,且第一导电垫12与导电线路层112电性绝缘。在其他实施例中,第一导电垫12可与导电线路层112位于同一层,但不以此为限。因此,第一导电垫12并未电性连接于第一基板11上的电子元件,故可将第一导电垫12视为第一基板11上的伪垫(DummyPad)。需注意的是,本实施的第一导电垫12的数量以一个为例,但第一导电垫12的数量非用以限定本发明。
第一导电垫12的外型大致为矩形,但不以此为限,且第一导电垫12上具有多个第一孔洞121。这些第一孔洞121可以阵列的方式等间隔排列或是随机排列,本发明并不加以限制,且这些第一孔洞121的外型可为正圆孔,如图2A所示。需注意的是,第一孔洞121的外型非用以限定本发明。举例来说,在其他实施例当中,第一导电垫12a上的这些第一孔洞121a的外型也可为椭圆孔,如图2B所示。或者,在其他实施例当中,第一导电垫12b上的这些第一孔洞121b的外型也可为矩形孔,如图2C所示。或者,在其他实施例当中,第一导电垫12b上的这些第一孔洞121b的外型也可为不规则形的孔洞。
多个第二导电垫13设置于第一基板11上,且这些第二导电垫13电连接导电线路层112,使得第二导电垫13与第一基板11上的电子元件之间具有电性连接的关系。
更进一步来说,如图1C所示,每一第二导电垫13可包括依序堆叠于导电线路层112上的一铜层133、一镍层132及一金层131,在其他实施例中,铜层133可与导电线路层112为同一层,但不以此为限。铜层133、镍层132及金层131可以印刷、电镀、电泳、电浆辅助沉积或蒸镀等的方式形成于第一基板11上。此外,本实施例的第一导电垫12的材质也可与第二导电垫13相同,亦即第一导电垫12也可包括依序堆叠的铜层、镍层及金层。
根据上述,由于第一导电垫12与第二导电垫13皆包括有金层,故在第一导电垫12及第二导电垫13相同厚度的情况下,减少第一导电垫12或第二导电垫13的面积可让所使用的金量减少,以降低电子组件10的成本。因此,本实施例系通过第一导电垫12上设置多个第一孔洞121,以降低第一导电垫12的整体面积,以减少第一导电垫12所使用的金量。并且,由于第一导电垫12为伪垫而不需提供电性连接的功效,因此这些第一孔洞121的设置并不会影响电子组件10的电性品质。
此外,在本实施例中,电子组件10另可包括一导电胶层14,导电胶层14可以是异方性导电胶(AnisotropicConductiveFilm,ACF)。导电胶层14设置于第一导电垫12及这些第二导电垫13上。请同时参照图3,图3系为根据图1B的第一导电垫与导电胶层的叠合示意图。其中导电胶层14与第一导电垫12的接触面积为A(即网线区域),而导电胶层14位于这些第一孔洞121上的面积为B,且33%≤A/(A+B)≤60%。其中,若A/(A+B)的值越小,代表单位区域内的第一导电垫12的面积越小,故第一导电垫12用金量也越少。因此,在其他实施例中,A与B之间的关系式更可以是33%≤A/(A+B)≤45%,以降低第一导电垫12用金量,进而更有效地降低电子组件10的成本。并且由于本实施例的第一导电垫12系以设置第一孔洞121的方式来减少用金量,而非是取消整个第一导电垫12。故当导电胶层14设置于第一导电垫12及第二导电垫13上时,并不会有高低差的问题出现,以避免产生导电胶层14贴附不良的问题。
此外,在本实施例中,电子组件10另可包括一第二基板15以及一晶片16。第二基板15可以是一软性电路板(FlexPrintedCircuit,FPC),晶片16可透过晶粒软模封装(ChiponFilm,COF)技术而设置于第二基板15上。此外,第二基板15更叠设于导电胶层14上,以使第一基板11的导电线路层112透过导电胶层14以及第二导电垫13而与第二基板15以及晶片16达成电性连接的关系。
此外,在本实施例中,电子组件10另可包括一面板17,面板17可以是但不限于一液晶显示面板,面板17连接于第二基板15远离第一基板11的一端。
请接着参照图4,图4系为根据本发明另一实施例的第二导电垫的结构平面图。为了减少电子组件10的整体用金量,在其他时实施例中,更可使至少一第二导电垫13a上设置有多个第二孔洞134a。只要第二导电垫13a上的第二孔洞134a的数量与大小控制得宜,在不影响第二导电垫13a的电性效果下,同样可达到降低用金量的功效。
根据上述一实施例的电子组件,系通过第一导电垫(伪垫)上设置多个第一孔洞,以降低第一导电垫的整体体积,进而减少第一导电垫的用金量。如此,使得电子组件的成本得以降低。并且,由于第一导电垫并未取消而不会使导电胶层设置于第一基板上时出现高低差的问题,以避免产生导电胶层贴附不良的问题。
虽然本发明以前述的较佳实施例公开如上,然其并非用以限定本发明,任何本领域技术人员在不脱离本发明的精神和范围内,当可作些许的更动与润饰,因此本发明的专利保护范围以权利要求书为准。
Claims (9)
1.一种电子组件,包括:
一第一基板,包括至少一基材层以及布设于该基材层上的至少一导电线路层;
至少一第一导电垫,设置于该第一基板,且该第一导电垫与该导电线路层电性绝缘,该第一导电垫上具有多个第一孔洞;以及
多个第二导电垫,设置于该第一基板,且电性连接该导电线路层;以及
一导电胶层,设置于该第一导电垫及所述第二导电垫上;
该导电胶层与该第一导电垫的接触面积为A,该导电胶层位于所述第一孔洞上的面积为B,且33%≤A/(A+B)≤45%。
2.如权利要求1所述的电子组件,其特征在于,另包括一第二基板以及一晶片,该晶片设置于该第二基板上,该第二基板叠设于该导电胶层上。
3.如权利要求2所述的电子组件,其特征在于,该第二基板为一软性电路板。
4.如权利要求2所述的电子组件,其特征在于,另包括一面板,连接该第二基板远离该第一基板的一端。
5.如权利要求1所述的电子组件,其特征在于,至少一该第二导电垫具有多个第二孔洞。
6.如权利要求1所述的电子组件,其特征在于,所述第一孔洞的外形为正圆孔、椭圆孔、矩形孔或不规则孔。
7.如权利要求1所述的电子组件,其特征在于,该第一基板为一印刷电路板。
8.如权利要求1所述的电子组件,其特征在于,该第一基板包括多个该基材层及多个该导电线路层,所述基材层及所述导电线路层是交错堆叠。
9.如权利要求1所述的电子组件,其特征在于,该第一导电垫或所述第二导电垫包括依序堆叠的一铜层、一镍层及一金层。
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