WO2022170703A1 - 短路棒、显示面板以及显示装置 - Google Patents

短路棒、显示面板以及显示装置 Download PDF

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Publication number
WO2022170703A1
WO2022170703A1 PCT/CN2021/098132 CN2021098132W WO2022170703A1 WO 2022170703 A1 WO2022170703 A1 WO 2022170703A1 CN 2021098132 W CN2021098132 W CN 2021098132W WO 2022170703 A1 WO2022170703 A1 WO 2022170703A1
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WO
WIPO (PCT)
Prior art keywords
layer
shorting bar
conductive layer
metal
insulating layer
Prior art date
Application number
PCT/CN2021/098132
Other languages
English (en)
French (fr)
Inventor
肖邦清
李懿
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US17/425,617 priority Critical patent/US11852934B2/en
Publication of WO2022170703A1 publication Critical patent/WO2022170703A1/zh

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Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136254Checking; Testing
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306Details
    • G02F1/1309Repairing; Testing
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136227Through-hole connection of the pixel electrode to the active element through an insulation layer
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136259Repairing; Defects
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136259Repairing; Defects
    • G02F1/136263Line defects
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136222Colour filters incorporated in the active matrix substrate

Definitions

  • the present application relates to the technical field of display devices, and in particular, to a shorting bar, a display panel and a display device.
  • the defective products after each process are intercepted in time, and there will be an inspection stage after each process;
  • the shorting bar design will be used for box detection, so that the data lines of each sub-pixel are shorted together, and the panel is checked for color shift, bad lines and other problems.
  • the shorting bar is disconnected from the data lines in the panel by laser cutting to form a floating line.
  • the shorting bar designed for narrow-bezel liquid crystal displays is usually set in the OLB (outer lead bonding) area.
  • OLB outer lead bonding
  • the shorting remaining in the OLB area The bar traces easily introduce external static electricity into the COF (chip on film), which causes electrostatic explosion to the COF and reduces the anti-ESD (Electro-Static discharge) capability of the display panel.
  • the present application provides a shorting bar, a display panel and a display device to solve the problem of electrostatic explosion caused by test wires.
  • the present application provides a shorting bar, which includes a plurality of test wires, and each of the test wires includes:
  • a metal wiring disposed on the insulating layer, and the metal wiring is at least partially exposed in the via hole;
  • a conductive layer at least a part of the conductive layer is placed in the via hole and covers the exposed metal trace, and the conductive layer is a peelable conductive layer.
  • the thickness of the conductive layer is in the range of 0.5-0.7 ⁇ m.
  • the size of the via hole ranges from 8 to 30 ⁇ m.
  • the number of the via holes is multiple, and the multiple via holes are arranged at intervals.
  • the distance between two adjacent via holes ranges from 5 to 10 ⁇ m.
  • the shapes of the plurality of via holes may be at least one of a circle, a rectangle and a triangle.
  • the conductive layer is a transparent conductive layer
  • the transparent conductive layer is made of indium tin oxide, antimony-doped tin oxide, aluminum-doped zinc oxide, or indium-doped zinc oxide.
  • the via hole includes a first hole
  • the metal trace includes a first metal layer
  • the insulating layer includes a first insulating layer
  • the shorting bar further includes:
  • a first insulating layer disposed on the base substrate
  • the first metal layer is disposed on the first insulating layer.
  • the shorting bar further comprises:
  • a color resist layer disposed on the first metal layer, the first hole is opened on the color resist layer and the first insulating layer, and the first metal layer is at least partially exposed in the first hole middle;
  • the conductive layer is disposed on the exposed first metal layer.
  • the color resist layer includes a plurality of color resists of different colors.
  • the first metal layer is made of one or more metals selected from molybdenum, chromium, aluminum, and copper.
  • the via hole further includes a second hole
  • the insulating layer includes a second insulating layer
  • the shorting bar further includes a second metal layer
  • the second insulating layer is disposed between the first metal layer and the color resist layer;
  • the second metal layer is disposed on the second insulating layer
  • the second hole is opened on the color resist layer and the second insulating layer, and the second metal layer is at least partially exposed in the second hole;
  • the conductive layer covers the color resist layer, and the first metal layer and the second metal layer are communicated through the conductive layer.
  • the second metal layer is made of one or more metals selected from molybdenum, chromium, aluminum, and copper.
  • the material of the base substrate includes glass, silicon dioxide, polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene terephthalate, polyimide One or more of amine or polyurethane.
  • the shorting bar further comprises:
  • the test terminal is connected to the test wire, the test terminal includes a plurality of sub-test terminals, and the plurality of the sub-test terminals are arranged at intervals.
  • the plurality of sub-test terminals include a red color test terminal, a green color test terminal, a blue color test terminal and a common electrode test terminal on the upper plate, and two of the sub-test terminals The two sides are respectively connected to the test traces through the data lines.
  • the present application also provides a display panel, which includes a shorting bar, and the shorting bar includes:
  • a metal wiring disposed on the insulating layer, and the metal wiring is at least partially exposed in the via hole;
  • a conductive layer at least a part of the conductive layer is placed in the via hole and covers the exposed metal trace, and the conductive layer is a peelable conductive layer.
  • the thickness of the conductive layer ranges from 0.5 to 0.7 ⁇ m.
  • the size of the via hole ranges from 8 to 30 ⁇ m.
  • the present application further provides a display device comprising the display panel of claim 17 .
  • the beneficial effects of the present application are as follows: by arranging via holes on the test traces, the metal traces of the test traces are exposed in the via holes, and an erasable conductive layer is arranged on the metal traces, and the conductive layer It can prevent the metal traces of the test traces from being corroded by water vapor before the test in a box.
  • the conductive layer is an erasable conductive layer.
  • the metal traces are exposed to the air through the vias, so that the metal traces are oxidized and corroded in the air, thereby increasing the resistance of the metal traces, so that static electricity is directly released on the metal traces of the test traces to prevent static electricity blast damage, which is conducive to improving the yield of the product.
  • FIG. 1 is a schematic structural diagram of a shorting bar provided in an embodiment of the present application.
  • FIG. 2 is a schematic cross-sectional structure diagram of a conductive layer covering a shorting bar according to an embodiment of the present application.
  • FIG. 3 is a schematic cross-sectional structural diagram of a shorting bar covering a conductive layer according to another embodiment of the present application.
  • FIG. 4 is a schematic cross-sectional structure diagram of the shorting bar peeling off the conductive layer provided by the embodiment of the present application.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, features defined as “first”, “second” may expressly or implicitly include one or more of said features. In the description of the present application, “plurality” means two or more, unless otherwise expressly and specifically defined.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be mechanical connection, electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction of two elements relation.
  • installed should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be mechanical connection, electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction of two elements relation.
  • a first feature "on” or “under” a second feature may include direct contact between the first and second features, or may include the first and second features Not directly but through additional features between them.
  • the first feature being “above”, “over” and “above” the second feature includes the first feature being directly above and obliquely above the second feature, or simply means that the first feature is level higher than the second feature.
  • the first feature is “below”, “below” and “below” the second feature includes the first feature being directly below and diagonally below the second feature, or simply means that the first feature has a lower level than the second feature.
  • an embodiment of the present application provides a shorting bar, including a plurality of test wires 100 , and the plurality of test wires 100 are arranged at intervals, wherein each test wire 100 includes a base substrate 11 , the insulating layer 20 , the via hole 40 and the conductive layer 30 .
  • the base substrate 11, wherein the base substrate 11 may be a glass substrate or a flexible substrate.
  • the material of the base substrate 11 includes one or more of glass, silicon dioxide, polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene terephthalate, polyimide or polyurethane.
  • the test trace 100 is provided with a metal trace 10
  • the test trace 100 is provided with a via hole 40
  • the metal trace 10 is at least partially exposed in the via hole 40 .
  • a conductive layer 30, at least part of the conductive layer 30 is placed in the via hole 40 and covers the exposed metal trace 10, the conductive layer 30 covers the metal trace 10 and extends the via hole
  • the conductive layer 30 is a peelable conductive layer 30 .
  • the strippable conductive layer 30 can be an indium tin oxide (ITO) film. Specifically, the strippable conductive layer 30 can be stripped from the insulating layer 20 , and the strippable conductive layer 30 is used to make the metal traces 10
  • the vias 40 are exposed to oxidation to increase resistance, and the strippable conductive layer 30 can be stripped from the metal traces 10 by scraping or rubbing with alcohol.
  • the via hole 40 is provided on the test wiring 100 , so that the metal wiring 10 of the test wiring 100 is exposed in the via hole 40 , and the erasable metal wiring 10 is provided on the metal wiring 10 .
  • the conductive layer 30, the conductive layer 30 can prevent the metal traces 10 of the test traces 100 from being corroded by water vapor before the box test, the conductive layer 30 is an erasable conductive layer, after the box test is completed, by directly rubbing
  • the metal traces 10 of the test traces 100 are exposed to the air through the vias 40 , so that the metal traces 10 are oxidized and corroded in the air, thereby increasing the resistance of the metal traces 10 , so that the static electricity is directly released on the metal wiring 10 of the test wiring 100 to prevent electrostatic explosion, thereby helping to improve the yield of the product.
  • the conductive layer 30 is a transparent conductive layer.
  • the transparent conductive layer 30 can also be made of antimony doped oxide. Made of tin, aluminum doped zinc oxide or indium doped zinc oxide.
  • the thickness of the conductive layer 30 is in the range of 0.5-0.7 ⁇ m.
  • the thickness of the conductive layer 30 may be 0.5 ⁇ m, and the thickness of the conductive layer 30 may also be 0.7 ⁇ m.
  • the thickness of the conductive layer 30 is controlled, that is, the thickness of the conductive layer 30 is set to be relatively thin, which is conducive to the subsequent erasing of the conductive layer 30.
  • the conductive layer 30 can be peeled off from the metal conductor by scraping or alcohol erasing. Line 10.
  • the size of the via hole 40 is in the range of 8-30 ⁇ m.
  • the size of the via hole 40 may be 8 ⁇ m, 15 ⁇ m or 30 ⁇ m, etc.
  • the number of the via holes 40 is multiple. As shown in FIG. 1 , the multiple via holes 40 are arranged at intervals along the length direction of the test trace 100 .
  • the arrangement of the plurality of vias 40 is beneficial to increase the exposed area of the metal trace 10 in the air, thereby facilitating the subsequent increase in the resistance of the metal trace 10 , so that static electricity is released on the test trace 100 , thereby improving the test trace 100 's resistance.
  • the antistatic ability is beneficial to improve the yield of the product. It can be understood that the shape of the via hole 40 may be at least one of a circle, a rectangle, and a triangle, which is not specifically limited in this embodiment.
  • the distance between two adjacent via holes 40 ranges from 5 to 10 ⁇ m.
  • the distance between two adjacent via holes 40 may be 5 ⁇ m, 8 ⁇ m, or 10 ⁇ m.
  • the via hole 40 includes the first hole 401 , each of the metal traces 10 includes a first trace, and the insulating layer 20 includes a first trace.
  • the insulating layer 21 , the test wiring 100 further includes a first metal layer 101 and a color resist layer 51 .
  • the first wiring is disposed in the first metal layer 101 .
  • the first insulating layer 21 is disposed on the base substrate 11 , the first metal layer 101 is disposed on the first insulating layer 21 , and the color resist layer 51 is disposed on the first insulating layer 21 above, the first hole 401 is opened on the color resist layer 51 and the first insulating layer 21, the conductive layer 30 is provided on the color resist layer 51, and the conductive layer 30 also passes through the color resist layer 51.
  • the first hole 401 is disposed on the first metal layer 101 .
  • the function of the first hole 401 is to remove the color resist layer 51 and the material of each insulating layer on the first metal layer 101 and the second metal layer 102, so that the first metal layer 101 (first trace) is exposed in the in the first hole 401 .
  • the color resist layer 51 includes a plurality of color resists, such as a red color resist R, a green color resist G, a blue color resist B, and the like.
  • the via hole 40 further includes the second hole 402
  • each of the metal traces 10 further includes a second trace
  • the insulating layer 20 includes the second insulating layer 22
  • the test The trace 100 further includes a second metal layer 102 .
  • the second insulating layer 22 is disposed between the first metal layer 101 and the color resist layer 51 , and specifically, the color resist layer 51 is disposed on the second insulating layer 22 ;
  • the second metal layer 102 is disposed on the second insulating layer 22 , and the second wiring is disposed in the second metal layer 102 .
  • the first metal layer 101 , the second metal layer 102 and the color resist layer 51 are all made of conductive materials, and the layers are insulated. Specifically, as shown in FIG. 3 , the base substrate 11 and the A first insulating layer 21 is arranged between the first metals, a second insulating layer 22 is arranged between the first metal layer 101 and the second metal layer 102, and the second insulating layer 22 is arranged on the on the second metal layer 102 . A third insulating layer 23 is further disposed between the second metal layer 102 and the color resist layer 51 .
  • the second hole 402 is opened on the color resist layer 51 and the second insulating layer 22 .
  • the function of the second hole 402 is to remove the material of the color resist layer 51 and each insulating layer on the metal, so that the second metal layer 102 (second trace) is exposed in the second hole 402 .
  • the conductive layer 30 covers the color resist layer 51 , and the conductive layer 30 is disposed on the exposed second metal layer 102 through the second hole 402 .
  • the second metal layer 102 is connected through the conductive layer 30 .
  • the conductive layer 30 covers the inner wall of the second hole 402 .
  • the via hole 40 includes a first hole 401 and a second hole 402
  • the metal trace 10 may further include a first trace and a second trace, and the first trace and all
  • the second traces are arranged in layers, the first traces and the second traces are exposed in the first hole 401 and the second hole 402 respectively, and the conductive layer 30 covers the color resist layer 51, On the inner wall of the first hole 401 and the inner wall of the second hole 402 , this arrangement enables the first wiring and the second wiring to be electrically connected through the conductive layer 30 .
  • the conductive layer 30 covers and protects the resistance of the metal wiring 10 to reduce the resistance of the metal wiring 10, which is conducive to panel display.
  • the first wiring The first wiring and the second wiring are exposed to the air to oxidize the metal to increase the resistance, which is beneficial to the anti-static discharge capability and improves the yield of the product.
  • the first metal layer 101 and the second metal layer 102 may be made of one or more metals selected from molybdenum, chromium, aluminum, and copper.
  • the first metal layer 101 may be made of Made of a single layer of copper, the first metal layer 101 can also be made of molybdenum/aluminum or molybdenum/aluminum/molybdenum multilayer laminates.
  • the shorting bar further includes a test terminal 200 , and the test terminal (Test Pad) is connected to a plurality of test wires 100 .
  • the test terminal 200 includes a plurality of sub-test terminals 201, and the plurality of the sub-test terminals 201 are arranged at intervals, and the number of the sub-test terminals 201 is 4, which are respectively a red pixel color test terminal and a green pixel color A test terminal, a blue pixel color test terminal, and a common electrode test terminal on the upper board, two sides of the sub-test terminal 201 are respectively connected to the test wire 100 through data lines.
  • the red pixel test terminal is electrically connected to the data line of the red pixel through the test wire 100
  • the green pixel test terminal is electrically connected to the data wire of the green pixel through the test wire 100
  • the blue pixel test terminal is connected to the blue pixel through the test wire 100.
  • the data lines of the pixels are electrically connected
  • the upper plate common electrode test terminal is connected to the upper plate common electrode of the color filter substrate corresponding to the three pixels of red, green and blue through the test wire 100 .
  • the embodiment of the present application further provides a display panel including the shorting bar, for example, the display panel may be a liquid crystal display panel. Since the display panel has the shorting bar, it has all the same beneficial effects, and the present invention will not repeat it here.
  • the display panel includes a display area and a non-display area adjacent to it.
  • the non-display area is provided with wirings
  • the display area is provided with a plurality of data lines and scan lines
  • the wiring includes connection with the data lines and the scan lines. wiring.
  • the shorting bar includes a plurality of test wires 100. When the test wires 100 are applied to the display panel, they are generally fabricated in the non-display area of the display panel, passing through the data lines and scan lines of the display area of the display panel and the wires in the display panel. Wiring is connected. By connecting the wiring to the shorting bar, and inputting the signal to the test terminal 200 of the shorting bar through the picture detector, the picture test of the display panel can be performed. The part where the signal line is connected to the display panel wiring is cut off with a laser, so that the display panel can be used for the next step of assembling the drive circuit module.
  • Embodiments of the present application further provide a display device, where the display device includes the display panel. Since the display device has the above-mentioned display panel, it has all the same beneficial effects, which will not be repeated in the present invention.
  • the embodiments of the present application do not specifically limit the application of the display device, which may be a TV, a notebook computer, a tablet computer, a wearable display device (such as a smart bracelet, a smart watch, etc.), a mobile phone, a virtual reality device, an enhanced Any product or component with display function, such as reality equipment, vehicle display, advertising light box, etc.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本申请提供一种短路棒、显示面板以及显示装置,所述短路棒包括测试走线,每个测试走线包括:衬底基板;绝缘层,设置于衬底基板上,绝缘层上开设有过孔;金属走线,设置于所述绝缘层上,所述金属走线至少部分显露于所述过孔中;导电层,至少部分所述导电层置于过孔内,并覆盖于显露的金属走线上,所述导电层为可剥离导电层。

Description

短路棒、显示面板以及显示装置 技术领域
本申请涉及显示器件技术领域,尤其涉及一种短路棒、显示面板以及显示装置。
背景技术
随着显示技术的不断发展,人们对显示器件的要求越来越高。推动了电子产品朝向窄边框、多功能和低功耗等方向发展,尤其随着窄边框的电子产品的实现,使得显示屏在面积不变的情况下,具有屏占比更高,视觉效果更好等特点,因此窄边框电子产品越来越受到青睐。
在显示面板的制造工艺过程中,例如液晶显示面板,为了保证产品质量,及时拦截每个制程工艺后的不良品,每个制程结束后都会有检测阶段;特别是在成盒之后,通过点亮液晶面板显示器,观察液晶的显示效果,所以成盒检测会用到短路棒(shorting bar)设计,使各子像素的数据线分别短接在一起,检查面板是否有色偏,线不良等问题。检查完毕后,shorting bar用激光切割的方式断开与面板内数据线的连接,形成浮接(floating)线路。
窄边框的液晶显示器设计的shorting bar通常设置在OLB(外引脚贴合,outer lead bonding)区域,对于窄边框的显示面板产品而言,在无边框保护的情况下,残留在OLB区域的shorting bar走线容易将外部静电导入COF(覆晶薄膜,chip on film)内部,对COF造成静电炸伤,降低了显示面板的抗ESD(静电释放,Electro-Static discharge)能力。
技术问题
本申请提供一种短路棒、显示面板以及显示装置,以解决测试走线造成的静电炸伤的问题。
技术解决方案
第一方面,本申请提供一种短路棒,其包括多条测试走线,每条所述测试走线包括:
衬底基板;
绝缘层,设置于所述衬底基板上,所述绝缘层上开设有过孔;
金属走线,设置于所述绝缘层上,所述金属走线至少部分显露于所述过孔中;
导电层,至少部分所述导电层置于所述过孔内,并覆盖于显露的所述金属走线上,所述导电层为可剥离导电层。
在本申请所述的短路棒中,所述导电层的厚度范围为0.5-0.7μm。
在本申请所述的短路棒中,所述过孔的尺寸大小范围为8-30μm。
在本申请所述的短路棒中,所述过孔的数量为多个,所述多个过孔间隔设置。
在本申请所述的短路棒中,沿所述测试走线的长度方向,相邻两个所述过孔之间的距离范围为5-10μm。
在本申请所述的短路棒中,所述多个过孔的形状可以为圆形,矩形以及三角形中的至少一种。
在本申请所述的短路棒中,所述导电层为透明导电层,所述透明导电层由氧化铟锡、锑掺杂氧化锡、铝掺杂氧化锌或者铟掺杂氧化锌制成。
在本申请所述的短路棒中,所述过孔包括第一孔,所述金属走线包括第一金属层,所述绝缘层包括第一绝缘层,所述短路棒还包括:
第一绝缘层,设置于所述衬底基板上;
第一金属层,设置于所述第一绝缘层上。
在本申请所述的短路棒中,所述短路棒还包括:
色阻层,设置于所述第一金属层上,所述第一孔开设于所述色阻层和所述第一绝缘层上,所述第一金属层至少部分显露于所述第一孔中;
所述导电层设置于显露的所述第一金属层上。
在本申请所述的短路棒中,色阻层包括多个不同颜色的色阻。
在本申请所述的短路棒中,所述第一金属层采用钼、铬、铝、铜中的一种或多种金属制成。
在本申请所述的短路棒中,所述过孔还包括第二孔,所述绝缘层包括第二绝缘层,所述短路棒还包括第二金属层;
所述第二绝缘层设置于所述第一金属层和所述色阻层之间;
所述第二金属层设置于所述第二绝缘层上;
所述第二孔开设于所述色阻层和所述第二绝缘层上,所述第二金属层至少部分显露于所述第二孔;
所述导电层覆盖于所述色阻层上,所述第一金属层和所述第二金属层通过所述导电层连通。
在本申请所述的短路棒中,所述第二金属层采用钼、铬、铝、铜中的一种或多种金属制成。
在本申请所述的短路棒中,所述衬底基板的材质包括玻璃、二氧化硅、聚乙烯、聚丙烯、聚苯乙烯、聚乳酸、聚对苯二甲酸乙二醇酯、聚酰亚胺或聚氨酯中的一种或多种。
在本申请所述的短路棒中,所述短路棒还包括:
测试端子,与所述测试走线连接,所述测试端子包括多个子测试端子,多个所述子测试端子间隔设置。
在本申请所述的短路棒中,多个所述子测试端子包括红像素色测试端子,绿像素色测试端子、蓝像素色测试端子以及上板共电极测试端子,所述子测试端子的两侧分别通过数据线与测试走线连接。
第二方面,本申请还提供一种显示面板,其包括短路棒,所述短路棒包括:
衬底基板;
绝缘层,设置于所述衬底基板上,所述绝缘层上开设有过孔;
金属走线,设置于所述绝缘层上,所述金属走线至少部分显露于所述过孔中;
导电层,至少部分所述导电层置于所述过孔内,并覆盖于显露的所述金属走线上,所述导电层为可剥离导电层。
在本申请所述的显示面板中,所述导电层的厚度范围为0.5-0.7μm。
在本申请所述的显示面板中,所述过孔的尺寸大小范围为8-30μm。
第三方面,本申请还提供一种显示装置,其包括如权利要求17所述的显示面板。
有益效果
本申请的有益效果为:通过在测试走线上设置过孔,使得测试走线的金属走线上显露于所述过孔中,并在金属走线上设置可擦除的导电层,导电层可以防止测试走线的金属走线在成盒测试之前被水汽腐蚀,所述导电层为可擦除导电层,在成盒测试完毕后,通过直接擦除所述导电层,使测试走线的金属走线通过所述过孔暴露在空气中,以使金属走线在空气中被氧化腐蚀,以此增加金属走线的电阻,使静电直接在测试走线的金属走线上释放,防止静电炸伤,从而有利于提高产品的良率。
附图说明
下面结合附图,通过对本申请的具体实施方式详细描述,将使本申请的技术方案及其它有益效果显而易见。
图1为本申请实施例提供的短路棒的结构示意图。
图2为本申请实施例提供的短路棒的覆盖导电层的剖面结构示意图。
图3为本申请又一实施例提供的短路棒覆盖导电层的剖面结构示意图。
图4为本申请实施例提供的短路棒剥离导电层的剖面结构示意图。
本发明的实施方式
下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整地描述。显然,所描述的实施例仅仅是本申请一部分实施例,而不是全部的实施例。基于本申请中的实施例,本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本申请保护的范围。
在本申请的描述中,需要理解的是,术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本申请和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本申请的限制。此外,术语“第一”、“第二”仅用于描述目的,而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此,限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中,“多个”的含义是两个或两个以上,除非另有明确具体的限定。
在本申请的描述中,需要说明的是,除非另有明确的规定和限定,术语“安装”、“相连”、“连接”应做广义理解,例如,可以是固定连接,也可以是可拆卸连接,或一体地连接;可以是机械连接,也可以是电连接或可以相互通讯;可以是直接相连,也可以通过中间媒介间接相连,可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言,可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中,除非另有明确的规定和限定,第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触,也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且,第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方,或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方,或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开,下文中对特定例子的部件和设置进行描述。当然,它们仅仅为示例,并且目的不在于限制本申请。此外,本申请可以在不同例子中重复参考数字和/或参考字母,这种重复是为了简化和清楚的目的,其本身不指示所讨论各种实施方式和/或设置之间的关系。此外,本申请提供了的各种特定的工艺和材料的例子,但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
请参考图1-图3,本申请实施例提供一种短路棒,包括多条测试走线100,所述多条测试走线100间隔设置,其中,每条测试走线100包括衬底基板11、绝缘层20、过孔40以及导电层30。
衬底基板11,其中衬底基板11可为玻璃基板或者柔性衬底。衬底基板11的材质包括玻璃、二氧化硅、聚乙烯、聚丙烯、聚苯乙烯、聚乳酸、聚对苯二甲酸乙二醇酯、聚酰亚胺或聚氨酯中的一种或多种。
绝缘层20,所述测试走线100内设置有金属走线10,所述测试走线100上开设有过孔40,所述金属走线10至少部分显露于所述过孔40中。
导电层30,至少部分所述导电层30置于所述过孔40内,覆盖于显露的所述金属走线10上,所述导电层30覆盖于金属走线10上并延伸所述过孔40的内壁和绝缘层20上,所述导电层30为可剥离导电层30。所述可剥离导电层30可以为氧化铟锡(ITO)薄膜,具体地,所述可剥离导电层30可以从绝缘层20上剥离,所述可剥离导电层30用于使金属走线10在过孔40中暴露以氧化增加电阻,所述可剥离导电层30可以通过刮除或者酒精擦除的方式剥离于金属走线10。
本申请实施例提供的短路棒通过在测试走线100上设置过孔40,使得测试走线100的金属走线10显露于所述过孔40中,并在金属走线10上设置可擦除的导电层30,导电层30可以防止测试走线100的金属走线10在成盒测试之前被水汽腐蚀,所述导电层30为可擦除导电层,在成盒测试完毕后,通过直接擦除所述导电层30,使测试走线100的金属走线10通过所述过孔40暴露在空气中,以使金属走线10在空气中被氧化腐蚀,以此增加金属走线10的电阻,使静电直接在测试走线100的金属走线10上释放,防止静电炸伤,从而有利于提高产品的良率。
可以理解的是,在一些实施例中,所述导电层30为透明导电层,所述透明导电层30除了可以由氧化铟锡制成,所述透明导电层30由还可以由锑掺杂氧化锡、铝掺杂氧化锌或者铟掺杂氧化锌制成。
在一些实施例中,所述导电层30的厚度范围为0.5-0.7μm,示例性地,所述导电层30的厚度可以为0.5μm,所述导电层30的厚度也可以为0.7μm,通过控制所述导电层30的厚度,即将所述导电层30厚度设置得比较薄,有利于后续将导电层30擦除,所述导电层30可以通过刮除或者酒精擦除的方式剥离于金属走线10。
在一些实施例中,所述过孔40的大小范围为8-30μm。例如,所述过孔40的大小可以为8μm、15μm或30μm等,所述过孔40开设得越大,则有金属走线10在空气中的暴露面积越大,有利于增加金属走线10的电阻。
在一些实施例中,所述过孔40的数量为多个,如图1所示,在所述测试走线100的长度方向上,所述多个过孔40间隔设置。多个过孔40的设置有利于提高金属走线10在空气中的暴露面积,从而有利于后续增加金属走线10的电阻,使得静电在测试走线100上释放,从而提高测试走线100的抗静电能力,有利于提高产品的良率。可以理解的是,所述过孔40的形状可以为圆形,矩形以及三角形等中的至少一种,本实施例在此不作具体限定。
在一些实施例中,沿所述测试走线100的长度方向,相邻两个所述过孔40之间的距离范围为5-10μm。示例性地,相邻两个所述过孔40的间距可以为5μm、可以为8μm,也可以为10μm。在过孔40尺寸一定时,所述过孔40的数量越多,剥离所述导电层30后测试走线100裸露的金属也就会越多,金属走线10氧化的面积越大,电阻越大,越有利于抗静电炸伤(ESD)。
在一些实施例中,如图3和图4所示,所述过孔40包括所述第一孔401,每条所述金属走线10包括第一走线,所述绝缘层20包括第一绝缘层21,所述测试走线100还包括第一金属层101和色阻层51。第一走线设置于第一金属层101中。
所述第一绝缘层21设置于所述衬底基板11上,所述第一金属层101设置于所述第一绝缘层21上,所述色阻层51设置于所述第一绝缘层21上,所述第一孔401开设于所述色阻层51和所述第一绝缘层21上,所述导电层30设置于所述色阻层51上,所述导电层30还通过所述第一孔401设置于所述第一金属层101上。其中,所述第一孔401的作用是去除第一金属层101和第二金属层102上面的色阻层51和各个绝缘层的材料,使得第一金属层101(第一走线)显露于所述第一孔401中。色阻层51包括多个色阻,例如红光色阻R、绿光色阻G、蓝光色阻B等。
在一些实施例中,所述过孔40还包括所述第二孔402,每条所述金属走线10还包括第二走线,所述绝缘层20包括第二绝缘层22,所述测试走线100还包括第二金属层102。
所述第二绝缘层22设置于所述第一金属层101和所述色阻层51之间,具体地,所述色阻层51设置于所述第二绝缘层22上;
所述第二金属层102设置于所述第二绝缘层22上,所述第二走线设置于所述第二金属层102中。
其中,第一金属层101、第二金属层102和色阻层51都是由导电材料制成,各层之间绝缘设置,具体地,如图3所示,所述衬底基板11和所述第一金属之间设置有第一绝缘层21,所述第一金属层101和所述第二金属层102之间设置有第二绝缘层22,所述第二绝缘层22设置于所述第二金属层102上。所述第二金属层102和所述色阻层51之间还设置有第三绝缘层23。
所述第二孔402开设于所述色阻层51上和所述第二绝缘层22上。其中,所述第二孔402的作用是去除金属上面的色阻层51和各个绝缘层的材料,使得第二金属层102(第二走线)显露于所述第二孔402中。
所述导电层30覆盖于所述色阻层51上,且所述导电层30通过所述第二孔402设置于显露的所述第二金属层102上,所述第一金属层101和所述第二金属层102通过所述导电层30连通,具体地,所述导电层30覆盖于所述第二孔402的内壁。
在本实施例中,所述过孔40包括第一孔401和第二孔402,所述金属走线10还可以包括第一走线和第二走线,且所述第一走线和所述第二走线分层设置,所述第一走线和所述第二走线分别显露于第一孔401和第二孔402中,所述导电层30覆盖于所述色阻层51、第一孔401的内壁以及第二孔402的内壁上,该设置方式可使所述第一走线和所述第二走线通过所述导电层30电性连接。通过将所述第一走线和所述第二走线分层设置,通过导电层30覆盖保护有利于减小金属走线10的电阻,有利于面板显示,剥离导电层30后,所述第一走线和所述第二走线暴露于空气中,使金属氧化从而增加电阻,有利于越有利于抗静电释放能力,有利于提高产品的良率。
示例性地,所述第一金属层101、所述第二金属层102可以采用钼、铬、铝、铜中的一种或多种金属制成,示例性地,第一金属层101可以采用单层铜制成,第一金属层101也可以采用钼/铝或者钼/铝/钼多层叠层制成。
在一些实施例中,如图1所示,所述短路棒还包括测试端子200,所述测试端子(Test Pad)与多条测试走线100连接。示例性地,所述测试端子200包括多个子测试端子201,多个所述子测试端子201间隔设置,所述子测试端子201的数量为4个,分别为红像素色测试端子,绿像素色测试端子、蓝像素色测试端子以及上板共电极测试端子,所述子测试端子201的两侧分别通过数据线与测试走线100连接。其中,红像素测试端子通过测试走线100与红色像素的数据线电连接,绿像素测试端子通过测试走线100与绿色像素的数据线电连接,蓝像素测试端子通过测试走线100与蓝色像素的数据线电连接,上板共电极测试端子通过测试走线100与红、绿、蓝三个像素对应的彩膜基板的上板共电极连接。
为了更好地实施例本申请的短路棒,本申请实施例还提供一种显示面板,包括所述的短路棒,示例性地,所述显示面板可以液晶显示面板。由于该显示面板具有所述短路棒,因此具有全部相同的有益效果,本发明在此不再赘述。
具体地,显示面板包括显示区和与其相邻非显示区,非显示区上设置有配线,显示区上设置有多条数据线和扫描线,而配线则包括与数据线和扫描线连接的配线。短路棒包括多条测试走线100,测试走线100应用于显示面板上时,一般是制作于在显示面板的非显示区,通过显示面板的显示区的数据线和扫描线与显示面板中的配线相连接。通过将配线与短路棒连接,并通过画面检测机将信号输入到短路棒的测试端子200,便可以对显示面板进行画面测试,画面测试结束后,对于通过画面测试的显示面板良品,只需要用激光将信号线与显示面板配线连接的部分切断,以便该显示面板用于进行下一步的驱动电路模块组装。
本申请实施例还提供一种显示装置,所述显示装置包括所述的显示面板。由于该显示装置具有上述显示面板,因此具有全部相同的有益效果,本发明在此不再赘述。本申请实施例对于所述显示装置的适用不做具体限制,其可以是电视机、笔记本电脑、平板电脑、可穿戴显示设备(如智能手环、智能手表等)、手机、虚拟现实设备、增强现实设备、车载显示、广告灯箱等任何具有显示功能的产品或部件。
在上述实施例中,对各个实施例的描述都各有侧重,某个实施例中没有详述的部分,可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种短路棒、显示面板以及显示装置进行了详细介绍,本文中应用了具体个例对本申请的原理及实施方式进行了阐述,以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想;本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种短路棒,其包括多条测试走线,每条所述测试走线包括:
    衬底基板;
    绝缘层,设置于所述衬底基板上,所述绝缘层上开设有过孔;
    金属走线,设置于所述绝缘层上,所述金属走线至少部分显露于所述过孔中;
    导电层,至少部分所述导电层置于所述过孔内,并覆盖于显露的所述金属走线上,所述导电层为可剥离导电层。
  2. 根据权利要求1所述的短路棒,其中,所述导电层的厚度范围为0.5-0.7μm。
  3. 根据权利要求1所述的短路棒,其中,所述过孔的尺寸大小范围为8-30μm。
  4. 根据权利要求1所述的短路棒,其中,所述过孔的数量为多个,所述多个过孔间隔设置。
  5. 根据权利要求4所述的短路棒,其中,沿所述测试走线的长度方向,相邻两个所述过孔之间的距离范围为5-10μm。
  6. 根据权利要求4所述的短路棒,其中,所述多个过孔的形状可以为圆形,矩形以及三角形中的至少一种。
  7. 根据权利要求1所述的短路棒,其中,所述导电层为透明导电层,所述透明导电层由氧化铟锡、锑掺杂氧化锡、铝掺杂氧化锌或者铟掺杂氧化锌制成。
  8. 根据权利要求1所述的短路棒,其中,所述过孔包括第一孔,所述金属走线包括第一金属层,所述绝缘层包括第一绝缘层,所述短路棒还包括:
    第一绝缘层,设置于所述衬底基板上;
    第一金属层,设置于所述第一绝缘层上。
  9. 根据权利要求8所述的短路棒,其中,所述短路棒还包括:
    色阻层,设置于所述第一金属层上,所述第一孔开设于所述色阻层和所述第一绝缘层上,所述第一金属层至少部分显露于所述第一孔中;
    所述导电层设置于显露的所述第一金属层上。
  10. 根据权利要求9所述的短路棒,其中,色阻层包括多个不同颜色的色阻。
  11. 根据权利要求8所述的短路棒,其中,所述第一金属层采用钼、铬、铝、铜中的一种或多种金属制成。
  12. 根据权利要求9所述的短路棒,其中,所述过孔还包括第二孔,所述绝缘层包括第二绝缘层,所述短路棒还包括第二金属层;
    所述第二绝缘层设置于所述第一金属层和所述色阻层之间;
    所述第二金属层设置于所述第二绝缘层上;
    所述第二孔开设于所述色阻层和所述第二绝缘层上,所述第二金属层至少部分显露于所述第二孔;
    所述导电层覆盖于所述色阻层上,所述第一金属层和所述第二金属层通过所述导电层连通。
  13. 根据权利要求12所述的短路棒,其中,所述第二金属层采用钼、铬、铝、铜中的一种或多种金属制成。
  14. 根据权利要求1所述的短路棒,其中,所述衬底基板的材质包括玻璃、二氧化硅、聚乙烯、聚丙烯、聚苯乙烯、聚乳酸、聚对苯二甲酸乙二醇酯、聚酰亚胺或聚氨酯中的一种或多种。
  15. 根据权利要求1所述的短路棒,其中,所述短路棒还包括:
    测试端子,与所述测试走线连接,所述测试端子包括多个子测试端子,多个所述子测试端子间隔设置。
  16. 根据权利要求15所述的短路棒,其中,多个所述子测试端子包括红像素色测试端子,绿像素色测试端子、蓝像素色测试端子以及上板共电极测试端子,所述子测试端子的两侧分别通过数据线与测试走线连接。
  17. 一种显示面板,其包括短路棒,所述短路棒包括:
    衬底基板;
    绝缘层,设置于所述衬底基板上,所述绝缘层上开设有过孔;
    金属走线,设置于所述绝缘层上,所述金属走线至少部分显露于所述过孔中;
    导电层,至少部分所述导电层置于所述过孔内,并覆盖于显露的所述金属走线上,所述导电层为可剥离导电层。
  18. 根据权利要求17所述的显示面板,其中,所述导电层的厚度范围为0.5-0.7μm。
  19. 根据权利要求17所述的显示面板,其中,所述过孔的尺寸大小范围为8-30μm。
  20. 一种显示装置,其包括如权利要求17所述的显示面板。
PCT/CN2021/098132 2021-02-10 2021-06-03 短路棒、显示面板以及显示装置 WO2022170703A1 (zh)

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CN113870699B (zh) * 2021-09-09 2023-06-16 惠科股份有限公司 显示面板及其测试端子
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