CN103117250A - 用于载具剥离的方法 - Google Patents
用于载具剥离的方法 Download PDFInfo
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- CN103117250A CN103117250A CN2012101950214A CN201210195021A CN103117250A CN 103117250 A CN103117250 A CN 103117250A CN 2012101950214 A CN2012101950214 A CN 2012101950214A CN 201210195021 A CN201210195021 A CN 201210195021A CN 103117250 A CN103117250 A CN 103117250A
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Abstract
本发明公开了一种方法,该方法包括:对包括多个管芯的复合晶圆进行切割,其中,在进行切割步骤时所述复合晶圆接合在载具上。在切割步骤之后,将所述复合晶圆设置于胶带上。然后从所述复合晶圆和所述第一胶带上剥离所述载具。本发明还涉及用于载具剥离的方法。
Description
技术领域
本发明涉及半导体技术领域,更具体地,本发明涉及一种用于载具剥离的方法。
背景技术
在集成电路的制造业中,涉及晶圆并且晶圆被用于形成集成电路或用于到在其上接合管芯。晶圆通常因为太薄而不能承受制造过程例如研磨中施加的压力。因此,在制造过程中,载具被用于机械支撑晶圆以防止破裂。在某些的制造阶段,需要从晶圆上剥离载具。在载具剥离之后,可能需要对晶圆进行一些剩下的加工(例如研磨)。然而,没有载具的支撑,晶圆可能易于弯曲,因此可能很难进行接下来的加工步骤例如研磨。
发明内容
为了解决现有技术中所存在的问题,根据本发明的一个方面,提供了一种方法,所述方法包括:
对包括多个管芯的复合晶圆进行切割,其中,在进行切割步骤时所述复合晶圆接合在载具上;
在所述切割步骤之后,将所述复合晶圆设置于第一胶带上;以及
从所述复合晶圆和所述第一胶带上剥离所述载具。
在一实施例中,所述复合晶圆包括晶圆,其中所述多个管芯中的每一个都包括所述晶圆的一个芯片和接合到所述晶圆上的多个封装元件中的一个封装元件,并且其中在所述切割步骤之后,所述晶圆中的各芯片相互分离。
在一实施例中,所述复合晶圆还包括模制在所述晶圆上的聚合物,所述聚合物设置在所述多个封装元件之间的间隙中,及在所述切割步骤之后,所述多个管芯通过所述聚合物的未切割部分而彼此相连。
在一实施例中,所述方法还包括:在剥离所述载具的步骤之后,将所述第一胶带切割成与所述复合晶圆大体相同的尺寸;以及对所述复合晶圆进行研磨以将所述多个管芯相互分离,其中在所述研磨步骤期间已经切割的所述第一胶带保持设置在所述复合晶圆上。
在一实施例中,所述方法还包括:在所述研磨步骤之后,将第二胶带设置于所述多个管芯上,其中所述第一胶带与所述第二胶带在所述多个管芯的相对的两侧;和从所述复合晶圆上卸下所述第一胶带。
在一实施例中,所述方法还包括:在所述切割步骤之前,将所述载具设置到附加胶带上,其中所述载具位于所述复合晶圆与所述附加胶带之间,在所述切割步骤期间,所述载具保持附接至所述附加胶带;和
在所述设置于第一胶带的步骤之前,从所述复合晶圆和所述载具上剥离所述附加胶带。
根据本发明的另一个方面,一种方法包括:
对复合晶圆进行切割以在所述复合晶圆中形成沟槽,所述复合晶圆包括晶圆及接合到所述晶圆上的封装元件,其中所述沟槽穿透所述晶圆并延伸进入填充所述封装元件之间空隙的聚合物中,并且其中在所述切割步骤期间,所述复合晶圆接合在载具上;
将所述复合晶圆设置于第一胶带上;
从所述复合晶圆和所述第一胶带上剥离所述载具;
研磨所述复合晶圆以将所述复合晶圆分离成相互完全独立的多个管芯;
在所述研磨步骤之后,将第二胶带设置于所述多个管芯上;和
在设置所述第二胶带的步骤之后,卸下所述第一胶带。
在一实施例中,在所述切割步骤之后以及在所述研磨步骤之前,所述多个管芯通过所述聚合物未切割层而相互连接,以及通过所述研磨步骤去除所述聚合物的所述未切割层。
在一实施例中,在所述切割步骤之后以及在所述研磨步骤之前,粘附层将所述载具与所述复合晶圆接合,以及其中在所述切割步骤期间未切割到所述粘附层。
在一实施例中,所述晶圆是内含无源器件的插入式晶圆,及所述封装元件包括器件管芯。
在一实施例中,所述方法还包括:在所述切割步骤之前,将所述载具设置于第三胶带上,其中所述载具位于所述复合晶圆和所述第三胶带之间,以及其中在所述切割步骤期间,所述载具保持附接至所述第三胶带;和,在设置所述第一胶带的步骤之前,从所述复合晶圆和所述载具上剥离所述第三胶带。
在一实施例中,所述载具包括玻璃载具。
根据本发明的又一个方面,一种方法包括:
在复合晶圆的第一侧上形成连接件,其中载具接合到所述复合晶圆的第二侧,及所述第一侧和所述第二侧是所述复合晶圆的相对的两侧;
从所述第一侧切割所述复合晶圆以形成沟槽,其中所述沟槽穿透所述复合晶圆中的晶圆并延伸进入所述复合晶圆的模塑料中;
将所述复合晶圆设置于第一胶带上,其中所述连接件与所述第一胶带接触;
从所述复合晶圆和所述第一胶带上剥离所述载具;和
在所述剥离步骤之后,将所述复合晶圆分离成各自独立的管芯。
在一实施例中,分离所述复合晶圆的步骤包括进行研磨以去除选自大体包括以下层的组中的层:与所述各自独立的管芯互连的所述模塑料的层,将所述载具接合到所述晶圆的接合层,以及它们的组合。
在一实施例中,在所述切割的步骤之后,所述沟槽穿透所述模塑料。
在一实施例中,在所述切割的步骤之后,所述沟槽未穿透所述模塑料。
在一实施例中,将所述复合晶圆分离成各自独立的管芯的步骤包括从所述复合晶圆的所述第二侧对所述复合晶圆进行研磨,由于所述研磨步骤,与所述各自独立的管芯互连的那部分模塑料被去除。
在一实施例中,所述晶圆是内含无源器件的插入式晶圆,并且其中所述复合晶圆还包括接合所述插入式晶圆的器件管芯,所述模塑料设置在所述器件管芯之间的间隙中。
在一实施例中,所述方法还包括:在从所述复合晶圆和所述第一胶带上剥离所述载具的步骤后,和在将所述复合晶圆分离成各自独立的管芯的步骤之前,将所述第一胶带切割成与所述复合晶圆形状接近的形状。
在一实施例中,将所述复合晶圆分离成各自独立的管芯的步骤包括研磨,并且在所述研磨期间,所述第一胶带附接至所述复合晶圆。
附图说明
为更完整地理解实施例及其优点,现将结合附图进行的以下描述作为参考,其中:
图1到图9是根据各种实施例的在封装件制造的中间阶段的截面图。
具体实施方式
下面详细讨论本发明各实施例的制造和使用。然而,本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式,而不用于限制本发明的范围。
本发明提供了根据不同实施例的封装工艺。示出了形成封装的中间阶段,讨论了各实施例的变化。在本申请中,对于各种视图及示例说明的实施例,相似的参考数字用于表示相似的元件。
图1至图9示出了根据一些示例性实施例的在封装制造的中间阶段的截面图。参考图1,示出了晶圆20。晶圆20可包括多个芯片22(也称为晶片或管芯),多个芯片22相互之间可以是相同的。晶圆20还可包括衬底24,衬底24可以是半导体衬底或电介质衬底。在一些实施例中,衬底24是硅衬底,但是衬底24也可以是由其它半导体材料(例如碳化硅、硅锗、III-V复合半导体或类似材料)形成。在一示例性实施例中,晶圆20是器件晶圆,该器件晶圆可包括在其中具有有源器件例如晶体管(未示出)的集成电路28。集成电路28用虚线示出,以表示可能形成,或可能未形成集成电路。在之后的图中,尽管集成电路28可能存在,但是未示出该集成电路28。在可选实施例中,晶圆20可包括其它不合有源器件的封装元件。例如,晶圆20可以是插入式晶圆、封装衬底带、封装衬底晶圆、或类似物。在另一些实施例中,晶圆20不包括有源器件,但是可包括无源器件(也用28示出),如电阻和电容器,或者也没有无源器件。
在一些实施例中,晶圆20包括穿过衬底的通孔(也称为硅通孔TSV或通孔)30,该通孔从衬底的一侧延伸到相对的另一侧。晶圆20也可包括金属层32(有时称为再分配层),在该金属层中包括金属线和通孔(未示出)。在晶圆20的一侧形成连接件34,该连接件34可通过金属层32以及通孔30电连接于集成电路28和/或连接件36。连接件34和连接件36形成在晶圆20的相对的表面上,并且可包括焊球、焊接凸点、与锡帽在其上结合的金属柱,和类似物。在一些示例性实施例中,连接件36是焊球。虽然未示出,但是再分配层可以和连接件36形成在衬底24的同一侧上。
封装元件40通过连接件34接合到晶圆的芯片22上。封装元件40可以是在其中包括有源电路(例如晶体管,未示出)的器件管芯,或者可以是包括接合到插入件/封装件衬底上的器件管芯的封装件。虽然示出了每个芯片22都具有接合在其上的两个封装元件40,但是在可选实施例中,可在每个芯片22上接合一个封装元件或两个以上封装元件。在封装元件40和芯片22之间的空间里填充底部填充物35。聚合物42模制在晶圆20上,并且封装元件40模制在聚合物42内。在一些实施例中,聚合物42包括模塑料、模塑底部填充物(Molding Underfill,MUF),或相类似物质。在整个说明书中,晶圆20、封装元件40,和聚合物42结合在一起称为复合晶圆100。
复合晶圆100接合到载具46上,例如通过接合层48,该接合层48可以是由例如有机物形成的粘附层。在连接件36和再分配层(如存在)的形成期间,再分配层和连接件36位于衬底24的同侧,载具46可机械支撑晶圆20。在一些实施例中,载具46是玻璃载具。
参考图2,载具46与覆在上面的复合晶圆100一起设置到切割胶带50上。如图3所示,进行切割管芯的步骤,例如使用刀片49,以形成沟槽54。沟槽54可延伸进入晶圆20的切割道中。沟槽54具有足够的深度以延伸到晶圆20底面之下,因此晶圆20中的各芯片22相互分离。沟槽54还延伸进入聚合物42,并延伸进入封装元件40之间的空间内。在一些实施例中,沟槽54的底部54A和载具46的顶面46A之间的距离T可在大约10um到大约30um之间,因而保留了边缘部分而不至于不合期望地切割到载具46。因此,在沟槽54的底部54A和载具46的顶面46A之间,至少是接合层48的底层未切割到,并且可能接合层48的底层完全未切割到。此外,可能聚合物42的底层未切割到。在一些实施例中,沟槽54延伸进入聚合物42但是没有延伸进入接合层48。在可选实施例中,如虚线所示,沟槽54的底部54A大体上和接合层48的顶面48A在同一水平面。在其它一些实施例中,也如虚线所示,沟槽54延伸进入接合层48。
参考图4,载具46和覆在上面的复合晶圆100从切割胶带50上取下。接下来,如图5所示,复合晶圆100胶在胶带58上。胶带58可足够厚以使连接件36可以压入胶带58中并受胶带58保护。胶带58具有足够的胶力,因而它可固定住复合晶圆100,复合晶圆基本上相互分离。在一些实施例中,胶带58是紫外线(UV)胶带。
图6示出了载具46的剥离。可通过例如激光剥离技术进行该剥离,其中激光穿透载具46投射在接合层48上。于是接合层48分解,从而去除载具46。
参考图7,将胶带58切割成与复合晶圆100大体相同的尺寸。从上往下看的胶带58的形状可以大体上与从上往下看的复合晶圆100的形状一样。因此,可将胶带58和复合晶圆100结合起来视为晶圆来对待,并可以如对晶圆一样进行输送和加工。
如图7所示,在复合晶圆100上进行研磨以去除接合层48的残渣(如果有)。为实施该研磨步骤,可用吸头(未示出)吸住胶带58并将胶带58输送至吸盘(chuck table)55上。吸盘55可通过真空将胶带58和覆在上面的元件固定在合适的地方。然后可进行研磨,例如,使用砂轮59研磨。因为在图3所示的步骤中已将晶圆20切割开,只有很薄的一层42/48与芯片22互连,因而释放了复合晶圆100上的应力。图7中的结构可大体上是平坦的,且显著减少了复合晶圆100的弯曲。因此,在胶带58和复合晶圆100的输送期间,可通过真空将胶带58牢固地吸到吸头上。而且,吸盘55也可以牢固地固定住胶带58和复合晶圆100。进行研磨直到去除了那部分使复合晶圆100粘成一体的聚合物42(如存在),以致芯片22和覆在上面的封装元件40完全分离成为管芯60。
参考图8,将胶带58和管芯60设置到切割胶带62上,并且管芯60粘附于切割胶带62。然后从管芯60上去除胶带58。在实施例中,其中胶带58是UV胶带,可将UV光投射在胶带58上以致胶带58不再有粘性,然后能够去除胶带58。在图9所示的最终结构中,各管芯60相互分离,并且粘附于于切割胶带62。然后各管芯60可与切割胶带62一同输送以进行下一步封装。
常规加工中,在剥离载具后,晶圆很薄可能会弯曲,这不利地使得薄晶圆不能固定到吸盘上,进一步地不能自动输送晶圆因为用真空不能吸住它。在本发明实施例中,采用在剥离之前进行切割的方案,在该方案中,在晶圆从各自的载具剥离之前就已对晶圆切隔,显著降低了晶圆的弯曲。因此,在没有了晶圆弯曲的顾虑的情况下,可自动进行之后的加工。
根据一些实施例,一种方法,包括:对包括多个管芯的复合晶圆进行切割,其中在进行切割的步骤时复合晶圆接合在载具上。在切割的步骤之后,将复合晶圆设置于第一胶带上。然后从复合晶圆和第一胶带上剥离载具。
根据其它实施例,一种方法,包括:对复合晶圆进行切割以在复合晶圆中形成沟槽,该复合晶圆包括晶圆及与接合到晶圆上的封装元件。所述沟槽穿透所述晶圆并延伸进入到填充封装元件之间间隙的聚合物中。在切割的步骤期间,复合晶圆接合在载具上。该方法还包括将复合晶圆设置于第一胶带上;从所述复合晶圆和第一胶带上剥离载具,并研磨复合晶圆以将所述复合晶圆分离成为相互完全分离的多个管芯。在研磨的步骤之后,将第二胶带设置在多个管芯上。在设置第二胶带的步骤之后,卸下第一胶带。
根据又一些实施例,一种方法,包括:在复合晶圆的第一侧上形成连接件,其中,载具接合到复合晶圆的第二侧上,并且其中所述第一侧与第二侧是复合晶圆的相对的两侧。从所述第一侧切割复合晶圆以形成沟槽,其中所述沟槽穿透复合晶圆中的晶圆并延伸进入到复合晶圆中的模塑料中。将复合晶圆固定到第一胶带上,其中连接件接触第一胶带。从复合晶圆和第一胶带上剥离载具。在所述剥离的步骤之后,复合晶圆分离成各自独立的管芯。
尽管已经详细地描述了本发明及其优点,但应该理解为,在不背离所附权利要求限定的本发明主旨和范围的情况下,可以做各种不同的改变,替换和更改。而且,本申请的范围并不旨在仅限于本说明书中描述的工艺、机器、制造,材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解,通过本发明,现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造,材料组分、装置、方法或步骤根据本发明可以被使用。因此,所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。此外,每项权利要求构成单独的实施例,并且多个权利要求和实施例的组合在本发明的范围内。
Claims (10)
1.一种方法,所述方法包括:
对包括多个管芯的复合晶圆进行切割,其中,在进行切割步骤时所述复合晶圆接合在载具上;
在所述切割步骤之后,将所述复合晶圆设置于第一胶带上;以及
从所述复合晶圆和所述第一胶带上剥离所述载具。
2.根据权利要求1所述的方法,其中所述复合晶圆包括晶圆,其中所述多个管芯中的每一个都包括所述晶圆的一个芯片和接合到所述晶圆上的多个封装元件中的一个封装元件,并且其中在所述切割步骤之后,所述晶圆中的各芯片相互分离。
3.根据权利要求2所述的方法,其中所述复合晶圆还包括模制在所述晶圆上的聚合物,所述聚合物设置在所述多个封装元件之间的间隙中,及在所述切割步骤之后,所述多个管芯通过所述聚合物的未切割部分而彼此相连。
4.根据权利要求1所述的方法,所述方法还包括:
在剥离所述载具的步骤之后,将所述第一胶带切割成与所述复合晶圆大体相同的尺寸;以及
对所述复合晶圆进行研磨以将所述多个管芯相互分离,其中在所述研磨步骤期间已经切割的所述第一胶带保持设置在所述复合晶圆上。
5.一种方法,所述方法包括:
对复合晶圆进行切割以在所述复合晶圆中形成沟槽,所述复合晶圆包括晶圆及接合到所述晶圆上的封装元件,其中所述沟槽穿透所述晶圆并延伸进入填充所述封装元件之间空隙的聚合物中,并且其中在所述切割步骤期间,所述复合晶圆接合在载具上;
将所述复合晶圆设置于第一胶带上;
从所述复合晶圆和所述第一胶带上剥离所述载具;
研磨所述复合晶圆以将所述复合晶圆分离成相互完全独立的多个管芯;
在所述研磨步骤之后,将第二胶带设置于所述多个管芯上;和
在设置所述第二胶带的步骤之后,卸下所述第一胶带。
6.根据权利要求5所述的方法,其中在所述切割步骤之后以及在所述研磨步骤之前,所述多个管芯通过所述聚合物未切割层而相互连接,以及通过所述研磨步骤去除所述聚合物的所述未切割层。
7.根据权利要求5所述的方法,其中在所述切割步骤之后以及在所述研磨步骤之前,粘附层将所述载具与所述复合晶圆接合,以及其中在所述切割步骤期间未切割到所述粘附层。
8.根据权利要求5所述的方法,其中所述晶圆是内含无源器件的插入式晶圆,及所述封装元件包括器件管芯。
9.一种方法,所述方法包括:
在复合晶圆的第一侧上形成连接件,其中载具接合到所述复合晶圆的第二侧,及所述第一侧和所述第二侧是所述复合晶圆的相对的两侧;
从所述第一侧切割所述复合晶圆以形成沟槽,其中所述沟槽穿透所述复合晶圆中的晶圆并延伸进入所述复合晶圆的模塑料中;
将所述复合晶圆设置于第一胶带上,其中所述连接件与所述第一胶带接触;
从所述复合晶圆和所述第一胶带上剥离所述载具;和
在所述剥离步骤之后,将所述复合晶圆分离成各自独立的管芯。
10.根据权利要求9所述的方法,其中分离所述复合晶圆的步骤包括进行研磨以去除选自大体包括以下层的组中的层:
与所述各自独立的管芯互连的所述模塑料的层,将所述载具接合到所述晶圆的接合层,以及它们的组合。
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104835747A (zh) * | 2015-04-02 | 2015-08-12 | 苏州晶方半导体科技股份有限公司 | 一种芯片封装方法 |
CN105321840A (zh) * | 2014-07-14 | 2016-02-10 | 矽品精密工业股份有限公司 | 切割用载具及切割方法 |
CN106067438A (zh) * | 2015-04-23 | 2016-11-02 | 日月光半导体制造股份有限公司 | 载具以及将半导体元件附接到载具的方法与半导体方法 |
CN108122838A (zh) * | 2017-12-13 | 2018-06-05 | 上海华虹宏力半导体制造有限公司 | 半导体器件制备工艺 |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8816500B2 (en) * | 2012-12-14 | 2014-08-26 | Infineon Technologies Ag | Semiconductor device having peripheral polymer structures |
TWI494410B (zh) * | 2013-04-10 | 2015-08-01 | Hon Hai Prec Ind Co Ltd | 膠帶 |
US9252054B2 (en) | 2013-09-13 | 2016-02-02 | Industrial Technology Research Institute | Thinned integrated circuit device and manufacturing process for the same |
US9478453B2 (en) | 2014-09-17 | 2016-10-25 | International Business Machines Corporation | Sacrificial carrier dicing of semiconductor wafers |
US10032662B2 (en) * | 2014-10-08 | 2018-07-24 | Taiwan Semiconductor Manufacturing Company | Packaged semiconductor devices and packaging methods thereof |
US10368442B2 (en) * | 2015-03-30 | 2019-07-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit structure and method of forming |
JP7075791B2 (ja) * | 2018-03-20 | 2022-05-26 | 株式会社ディスコ | 半導体パッケージの製造方法 |
KR102174928B1 (ko) * | 2019-02-01 | 2020-11-05 | 레이저쎌 주식회사 | 멀티 빔 레이저 디본딩 장치 및 방법 |
TW202101647A (zh) | 2019-06-20 | 2021-01-01 | 美商康寧公司 | 用於產線後段處理的載具 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1650420A (zh) * | 2002-07-12 | 2005-08-03 | 赋权新加坡私人有限公司 | 用于保持晶片上的接合焊垫超洁净的方法和晶片 |
US20060099735A1 (en) * | 2004-11-03 | 2006-05-11 | Hui-Lung Chou | Method for wafer level stack die placement |
US20080003720A1 (en) * | 2006-06-30 | 2008-01-03 | Daoqiang Lu | Wafer-level bonding for mechanically reinforced ultra-thin die |
US20100244284A1 (en) * | 2009-03-27 | 2010-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for ultra thin wafer handling and processing |
Family Cites Families (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4811082A (en) | 1986-11-12 | 1989-03-07 | International Business Machines Corporation | High performance integrated circuit packaging structure |
US4990462A (en) | 1989-04-12 | 1991-02-05 | Advanced Micro Devices, Inc. | Method for coplanar integration of semiconductor ic devices |
US5075253A (en) | 1989-04-12 | 1991-12-24 | Advanced Micro Devices, Inc. | Method of coplanar integration of semiconductor IC devices |
US5380681A (en) | 1994-03-21 | 1995-01-10 | United Microelectronics Corporation | Three-dimensional multichip package and methods of fabricating |
US6002177A (en) | 1995-12-27 | 1999-12-14 | International Business Machines Corporation | High density integrated circuit packaging with chip stacking and via interconnections |
US6213376B1 (en) | 1998-06-17 | 2001-04-10 | International Business Machines Corp. | Stacked chip process carrier |
US6281042B1 (en) | 1998-08-31 | 2001-08-28 | Micron Technology, Inc. | Structure and method for a high performance electronic packaging assembly |
US6271059B1 (en) | 1999-01-04 | 2001-08-07 | International Business Machines Corporation | Chip interconnection structure using stub terminals |
US6461895B1 (en) | 1999-01-05 | 2002-10-08 | Intel Corporation | Process for making active interposer for high performance packaging applications |
US6229216B1 (en) | 1999-01-11 | 2001-05-08 | Intel Corporation | Silicon interposer and multi-chip-module (MCM) with through substrate vias |
US6243272B1 (en) | 1999-06-18 | 2001-06-05 | Intel Corporation | Method and apparatus for interconnecting multiple devices on a circuit board |
US6355501B1 (en) | 2000-09-21 | 2002-03-12 | International Business Machines Corporation | Three-dimensional chip stacking assembly |
KR100364635B1 (ko) | 2001-02-09 | 2002-12-16 | 삼성전자 주식회사 | 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법 |
KR100394808B1 (ko) | 2001-07-19 | 2003-08-14 | 삼성전자주식회사 | 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법 |
KR100435813B1 (ko) | 2001-12-06 | 2004-06-12 | 삼성전자주식회사 | 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법 |
DE10200399B4 (de) | 2002-01-08 | 2008-03-27 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Erzeugung einer dreidimensional integrierten Halbleitervorrichtung und dreidimensional integrierte Halbleitervorrichtung |
US6661085B2 (en) | 2002-02-06 | 2003-12-09 | Intel Corporation | Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack |
US6975016B2 (en) | 2002-02-06 | 2005-12-13 | Intel Corporation | Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof |
US6887769B2 (en) | 2002-02-06 | 2005-05-03 | Intel Corporation | Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same |
US6762076B2 (en) | 2002-02-20 | 2004-07-13 | Intel Corporation | Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices |
US6600222B1 (en) | 2002-07-17 | 2003-07-29 | Intel Corporation | Stacked microelectronic packages |
US6790748B2 (en) | 2002-12-19 | 2004-09-14 | Intel Corporation | Thinning techniques for wafer-to-wafer vertical stacks |
US6908565B2 (en) | 2002-12-24 | 2005-06-21 | Intel Corporation | Etch thinning techniques for wafer-to-wafer vertical stacks |
US6924551B2 (en) | 2003-05-28 | 2005-08-02 | Intel Corporation | Through silicon via, folded flex microelectronic package |
US6946384B2 (en) | 2003-06-06 | 2005-09-20 | Intel Corporation | Stacked device underfill and a method of fabrication |
US7320928B2 (en) | 2003-06-20 | 2008-01-22 | Intel Corporation | Method of forming a stacked device filler |
KR100537892B1 (ko) | 2003-08-26 | 2005-12-21 | 삼성전자주식회사 | 칩 스택 패키지와 그 제조 방법 |
US7345350B2 (en) | 2003-09-23 | 2008-03-18 | Micron Technology, Inc. | Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias |
KR100621992B1 (ko) | 2003-11-19 | 2006-09-13 | 삼성전자주식회사 | 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지 |
JP4307284B2 (ja) * | 2004-02-17 | 2009-08-05 | 三洋電機株式会社 | 半導体装置の製造方法 |
KR100570514B1 (ko) | 2004-06-18 | 2006-04-13 | 삼성전자주식회사 | 웨이퍼 레벨 칩 스택 패키지 제조 방법 |
KR100618837B1 (ko) | 2004-06-22 | 2006-09-01 | 삼성전자주식회사 | 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법 |
US7307005B2 (en) | 2004-06-30 | 2007-12-11 | Intel Corporation | Wafer bonding with highly compliant plate having filler material enclosed hollow core |
US7087538B2 (en) | 2004-08-16 | 2006-08-08 | Intel Corporation | Method to fill the gap between coupled wafers |
US7317256B2 (en) | 2005-06-01 | 2008-01-08 | Intel Corporation | Electronic packaging including die with through silicon via |
US7557597B2 (en) | 2005-06-03 | 2009-07-07 | International Business Machines Corporation | Stacked chip security |
US7402515B2 (en) | 2005-06-28 | 2008-07-22 | Intel Corporation | Method of forming through-silicon vias with stress buffer collars and resulting devices |
US7432592B2 (en) | 2005-10-13 | 2008-10-07 | Intel Corporation | Integrated micro-channels for 3D through silicon architectures |
US7528494B2 (en) | 2005-11-03 | 2009-05-05 | International Business Machines Corporation | Accessible chip stack and process of manufacturing thereof |
US7410884B2 (en) | 2005-11-21 | 2008-08-12 | Intel Corporation | 3D integrated circuits using thick metal for backside connections and offset bumps |
US7402442B2 (en) | 2005-12-21 | 2008-07-22 | International Business Machines Corporation | Physically highly secure multi-chip assembly |
US7279795B2 (en) | 2005-12-29 | 2007-10-09 | Intel Corporation | Stacked die semiconductor package |
US7576435B2 (en) | 2007-04-27 | 2009-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low-cost and ultra-fine integrated circuit packaging technique |
KR101213175B1 (ko) | 2007-08-20 | 2012-12-18 | 삼성전자주식회사 | 로직 칩에 층층이 쌓인 메모리장치들을 구비하는반도체패키지 |
-
2011
- 2011-11-16 US US13/298,014 patent/US8629043B2/en active Active
-
2012
- 2012-06-13 CN CN201210195021.4A patent/CN103117250B/zh active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1650420A (zh) * | 2002-07-12 | 2005-08-03 | 赋权新加坡私人有限公司 | 用于保持晶片上的接合焊垫超洁净的方法和晶片 |
US20060099735A1 (en) * | 2004-11-03 | 2006-05-11 | Hui-Lung Chou | Method for wafer level stack die placement |
US20080003720A1 (en) * | 2006-06-30 | 2008-01-03 | Daoqiang Lu | Wafer-level bonding for mechanically reinforced ultra-thin die |
US20100244284A1 (en) * | 2009-03-27 | 2010-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for ultra thin wafer handling and processing |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105321840A (zh) * | 2014-07-14 | 2016-02-10 | 矽品精密工业股份有限公司 | 切割用载具及切割方法 |
CN104835747A (zh) * | 2015-04-02 | 2015-08-12 | 苏州晶方半导体科技股份有限公司 | 一种芯片封装方法 |
CN106067438A (zh) * | 2015-04-23 | 2016-11-02 | 日月光半导体制造股份有限公司 | 载具以及将半导体元件附接到载具的方法与半导体方法 |
CN108122838A (zh) * | 2017-12-13 | 2018-06-05 | 上海华虹宏力半导体制造有限公司 | 半导体器件制备工艺 |
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