CN103094257A - 具有屏蔽结构的3d芯片封装 - Google Patents

具有屏蔽结构的3d芯片封装 Download PDF

Info

Publication number
CN103094257A
CN103094257A CN2012104173886A CN201210417388A CN103094257A CN 103094257 A CN103094257 A CN 103094257A CN 2012104173886 A CN2012104173886 A CN 2012104173886A CN 201210417388 A CN201210417388 A CN 201210417388A CN 103094257 A CN103094257 A CN 103094257A
Authority
CN
China
Prior art keywords
chamber
semiconductor device
carrier substrates
crystal grain
screen
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2012104173886A
Other languages
English (en)
Other versions
CN103094257B (zh
Inventor
A·伯格蒙特
U·斯瑞达
J·埃卢尔
Y-S·A·孙
E·西蒙斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Maxim Integrated Products Inc
Original Assignee
Maxim Integrated Products Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Maxim Integrated Products Inc filed Critical Maxim Integrated Products Inc
Publication of CN103094257A publication Critical patent/CN103094257A/zh
Application granted granted Critical
Publication of CN103094257B publication Critical patent/CN103094257B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12043—Photo diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

本发明公开了一种具有屏蔽结构的3D芯片封装，该3D芯片封装包括载体基底，所述载体基底具有形成在其中的第一腔和第二腔。第一结构在所述第一腔中至少部分地附着到所述载体基底，并且第二结构在所述第二腔中至少部分地附着到所述载体基底，其中第一和第二结构包括电子电路。屏蔽层可设置在所述载体基底与第一结构和/或第二结构之间，以使所述第一结构和/或所述第二结构以电绝缘、磁绝缘、光绝缘或热绝缘方式的至少一种绝缘。在一些实施例中，所述屏蔽层可为用于将第一结构和第二结构介电耦合的介电屏蔽层。所述第一结构和所述第二结构可为同构或异构的。

Description

具有屏蔽结构的3D芯片封装
背景技术
可利用集成到单个IC芯片中的两层或更多层电子元件构造三维集成电路（3D IC）。这些元件可利用芯片上信号传输（on-chip signaling）竖直地和/或水平地通信。单片3D IC可包括在单个半导体晶圆上的多个层中建立的相关布线和电子元件，所述单个半导体晶圆随后被切割成多个3D IC。晶圆上晶圆3D IC可包括在两个或更多个半导体晶圆上建立的电子元件，所述两个或更多个半导体晶圆可随后被对齐、键合和切割成多个3D IC。可在键合之前在晶圆中建立竖直连接和/或在键合之后在叠堆中创建竖直连接。例如，穿透性硅通孔（TSV）可穿透有源层之间和/或有源层与外部焊垫之间的硅基底。晶圆上晶粒（die）3D IC可包括在两个半导体晶圆上建立的电子元件。可将一个晶圆切割，并且独立的切块可对齐和键合到第二晶圆的晶粒部位上。可在键合之前或之后执行TSV创建。晶粒上晶粒3D IC可包括在多个切块上建立的电子元件，可随后将所述多个切块对齐和键合。可在键合之前或之后完成TSV创建。
发明内容
公开了一种3D芯片封装，其包括载体基底，所述载体基底具有形成在其中的第一腔和第二腔。第一结构（例如，晶粒、在半导体晶圆上建造的IC、离散电子元件等等）在第一腔中至少部分地附着到载体基底，并且第二结构（例如，晶粒、在半导体晶圆上建造的IC、离散电子元件等等）在第二腔中至少部分地附着到载体基底，其中第一和第二结构包括电子电路。屏蔽层可设置在所述载体基底与第一结构和/或第二结构之间，以使所述第一结构和/或所述第二结构以电绝缘、磁绝缘、光绝缘或热绝缘方式的至少一种绝缘。在一些实施例中，所述屏蔽层可为用于将第一结构和第二结构介电耦合的介电屏蔽层。第一结构和第二结构可为同构的（例如，二者均包括数字电路或模拟电路）或异构的（例如，一个包括数字电路而另一个包括模拟电路）。
该发明内容被提供用以通过简化的形式介绍构思的选择，该构思的选择在下面的详细说明中将进一步描述。本发明内容不旨在识别要求保护的主题的关键特征或重要特征，也不旨在用于帮助确定要求保护的主题的范围。
附图说明
参照附图描述具体实施方式。在具体实施方式和附图中的不同实例中使用的相同的标号可指代相似或相同的对象。
图1是根据本发明实施方式的一个实例示出3D芯片封装的示意性横截面侧视图，所述3D芯片封装包括附着到载体基底上的第一和第二IC结构，其中屏蔽层设置在载体基底与第一IC结构和/或第二IC结构之间。
图2是图1中所示的3D芯片封装的俯视平面图。
图3是根据本发明实施方式的一个实例示出形成3D芯片封装的方法的流程图，所述3D芯片封装包括附着到载体基底上的第一和第二IC结构，其中屏蔽层设置在载体基底与第一IC结构和/或第二IC结构之间。
图4是根据本发明实施方式的一个实例示出载体基底的示意性横截面侧视图，所述载体基底包括镀敷有屏蔽层的腔。
图5是根据本发明实施方式的一个实例示出多个IC结构的示意性横截面侧视图，所述多个IC结构附着到载体并镀敷有屏蔽层。
具体实施方式
概述
可利用集成到单个芯片中的多层电子元件构造3D IC。然而，当不同元件被封装在一起时，可导致电和/或磁串扰。例如，快速开关数字IC和高电压开关IC可产生电串扰。相似地，高电流开关IC可产生磁串扰。此外，与安装在印刷电路板（PCB）上的相似元件相比，3D IC的元件可被布置为彼此更靠近。例如，3D IC的元件可按照约二微米（2μm）和五微米（5μm）之间的平均距离分离，而安装在PCB上的元件可按照约五十微米（50μm）和一百微米（100μm）之间的平均距离分离。这种紧密靠近可混合（增加）元件之间产生的电和/或磁串扰。
在系统芯片（SoC）应用中，例如，开关电路可与灵敏模拟晶粒共封装，并可产生可干涉模拟晶粒的功能的可观的噪声。噪声可从有源电路穿过基底电容耦合到相邻的射频（RF）/模拟电路，从而影响其性能。此外，大电流开关可导致磁耦合到相邻的封装电路布线，从而例如在3D IC构造中导致不期望的电流，在3D IC构造中，高电流开关调节器电路在灵敏高性能模数（A/D）转换器或传感器信号调节电路旁被封装。
在3D IC实施方式中，热也可从一个元件传递到另一元件。此外，传感器元件可被从附近的传输元件接收的不期望的信号影响。例如，光传感元件可从相邻的光透射元件接收到不期望的干涉。另外，来自IC元件上的传输电路的信号可被下层基底材料吸收，而不从3D IC芯片向外导向。这些信号穿过基底的传输可导致不期望地干涉载体基底的元件以及安装在基底上的相邻的元件。
为了将3D IC元件彼此电分离，可将硅插入物插入元件之间。这些插入物可被金属镀层覆盖，所述金属镀层诸如溅射在每个插入物背侧上的金或铝。可随后将插入物附着到处理基底（handling substrate）上，在所述处理基底上安装有多种元件。然而，在该构造中，金属镀层可仅被设置在每个晶粒的两侧上，而不设置在晶粒与处理基底之间。因此，可仍然发生穿过基底的耦合和/或信号损失。
因此，描述了包括附着到公共载体基底上的两个或更多个离散IC结构的三维（3D）芯片封装。芯片封装包括一个或多个屏蔽层，其中屏蔽腔衬（shielded cavity lining）设置在一个或多个IC结构周围。屏蔽腔可提供电屏蔽、磁屏蔽、光屏蔽和/或热屏蔽。例如，屏蔽腔可用于减少或消除相邻的IC结构中的两个二极管之间的闩锁效应。按照该方式，低噪声互补金属氧化物半导体（CMOS）晶粒可在单个芯片上与包括高电压工业电路的晶粒等结合。在实施方式中，3D芯片封装可实现为单片3D IC、晶圆上晶圆3DIC、晶圆上晶粒3D IC或晶粒上晶粒3D IC。
包围封装电路的厚的磁和/或电屏蔽层减少或消除了交叉耦合。例如，电屏蔽物、金属屏蔽物可用作法拉第罩（Faraday cage），它可以接地。这种屏蔽可为电子电路提供绝缘，所述电子电路可以其它方式作为天线，其可受到来自电磁辐射的不期望的影响。此外，这种屏蔽可提供对外部磁场的隔离，所述外部磁场诸如附近装置的电路产生的磁场、地球磁场等。
半导体芯片封装可用于其中在IC之间的基底耦合要求隔离的应用中，所述应用包括功率应用、射频（RF）应用、数字应用和灵敏模拟晶粒应用，包括医学应用（例如，超声波IC）和工业应用（例如，高功率开关IC）。半导体芯片封装可提供各频率下的多个部件的电和/或磁屏蔽。例如，在具有异构封装结构（heterogeneously packaged structure）的实施方式中，灵敏结构可被屏蔽以不受噪声开关结构的影响。这种屏蔽可利用例如感应器、高电流开关元件等实施。因此，半导体芯片封装可实现组装的元件之间的非常少的寄生交互作用（parasitic interaction）。
半导体芯片封装也可提供元件之间的光和/或热屏蔽。例如，屏蔽可减少或消除光传感元件从光透射元件接收不期望的干涉。此外，屏蔽可减少或消除下层基底材料对光信号的吸收。例如，来自发光二极管（LED）的光可被IC结构和载体基底之间的屏蔽反射，从而增大芯片封装产生的光信号的所得的信噪比。在另一情况下，所述屏蔽可作为用于从IC结构驱散热并且可能用于减少或消除附近IC结构接收到的热的散热器。
通过提供在单个芯片封装中容纳多个IC结构的屏蔽腔集成，芯片封装的所希望的功能可通过例如多个较小切块而非一个较大的、更复杂的晶粒提供。当生产元件晶粒时，这种尺寸的减小可允许产率增大，其可减小总成本、工艺复杂度等等。此外，分离的IC元件可在被一起结合在3D IC芯片封装中之前被优化和/或可通过具有不同技术专业技能的不同的制造商提供。例如，一个晶粒上的双极晶体管可与另一晶粒上的CMOS电路分开优化。另外，可利用不同基底材料形成不同的IC元件（例如，一个IC结构可形成在硅基底上，而另一IC结构可形成在氮化镓基底上，等等）。
在一些实施例中，3D芯片封装可包括异构元件（例如，大小、复杂度、功能、信号类型等不同的IC结构）。例如，3D芯片封装可包括具有数字电路的一个或多个结构和具有模拟电路的一个或多个结构。在其它实施例中，3D芯片封装可包括同构元件（例如，至少在大小、复杂度、功能、信号类型等方面基本上相似的IC结构）。例如，3D芯片封装可包括具有模拟电路的两个或更多个结构或者具有数字电路的两个或更多个结构。
如本文所用，术语“IC结构”和“包括电子电路的结构”意指具有两个或更多个电端子/引线的电子元件，所述两个或更多个电端子/引线连接在一起以创建具有特定功能的电子电路。所述结构的实例包括但不一定限于：IC元件，诸如在半导体晶圆上建立的IC、在随后被独立化以产生晶粒的半导体晶圆上建立IC以及离散的电子元件，所述离散的电子元件包括但不一定限于：放大器、加速计、天线、电容器、二极管、滤光片、熔断器、液晶二极管（LCD）、LED、有机LED（OLED）、磁感应器、磁力计、忆阻器、振荡器、光敏电阻、无线电接收器、电阻器、传感器、开关、热敏电阻、换能器、变压器、晶体管、波导等等。
如本文所用，术语“载体基底”意指由半导体材料构成的基底，所述半导体材料诸如但不一定限于：硅、二氧化硅、氧化铝、蓝宝石、锗、砷化镓（GaAs）、硅和锗的合金和/或磷化铟（InP）。此外，针对本发明，载体基底可形成为半导体或电绝缘体，并且可包括半导体和绝缘材料二者的层。例如，在实施方式中，载体基底可利用诸如氧化硅的绝缘体形成，一层诸如硅的半导体材料形成在所述载体基底上。可在半导体材料中建造诸如晶体管和二极管的电元件。在其它实施方式中，载体基底可形成为电介质。在实施方式中，载体基底可与半导体晶圆独立设置。例如，载体基底可实现为晶粒。
示例实施方式
图1和图2示出了示例3D芯片封装，诸如半导体芯片封装100，其具有载体基底102，所述载体基底102具有形成在其中的第一腔104和第二腔106。第一IC结构（例如，第一晶粒108）至少部分地在第一腔104中附着到载体基底102（即，设置在由载体基底102的顶表面限定的平面下方，延伸到由载体基底102的顶表面限定的平面，和/或延伸到载体基底102的顶表面限定的平面以外）。第二IC结构（例如，第二晶粒110）至少部分地在第二腔106中附着到载体基底102。屏蔽层（例如，第一金属层112）被设置在载体基底102与第一IC结构和/或第二IC结构之间，从而至少基本上将IC结构绝缘。例如，第一晶粒108和/或第二晶粒110可电绝缘、磁绝缘、光绝缘和/或热绝缘。第一金属层112可为用于将第一晶粒108和第二晶粒110介电耦合的介电屏蔽层。在一些实施例中，半导体芯片封装100包括设置在第一晶粒108和/或第二晶粒110之上的另一屏蔽层（例如，第二金属层114），以进一步使IC结构绝缘。
诸如第一金属层112的一个或多个电和/或磁屏蔽层可沉积在载体基底102与第一晶粒108和/或第二晶粒110之间。在实施例中，第一金属层112可用于屏蔽与载体基底102相邻的第一晶粒108和/或第二晶粒110的多达五个侧部。此外，诸如第二金属层114的一个或多个电和/或磁屏蔽层可沉积在半导体芯片封装100的顶部，在第一晶粒108和/或第二晶粒110上方。例如，第二金属层114可包围第一晶粒108和/或第二晶粒110的多个电路之间的金属引线和/或互连。在实施例中，第一金属层112和第二金属层114可用于屏蔽第一晶粒108和/或第二晶粒110的多达六个侧部。当额外的器件堆叠在第一晶粒108和/或第二晶粒110的顶部上时，这可以是有用的。
通过在半导体芯片封装100上形成金属屏蔽层使其基本包围第一晶粒108和/或第二晶粒110，可抑制电和/或磁场与相邻的灵敏IC的寄生耦合。在实施例中，第一金属层112和/或第二金属层114可由高电导率金属镀层（例如，金、铝，等等）、高磁导率金属镀层或者具有高电导率和高磁导率二者的金属镀层形成。在一些情况下，第一金属层112和/或第二金属层114可接地（即，连接到半导体芯片封装100的地，诸如接地面、接地垫116，等等）以形成用于电屏蔽的法拉第罩。在其它情况下，第一金属层112和/或第二金属层114可“漂浮”在半导体芯片封装100上（即，不直接接地）。
第一金属层112和/或第二金属层114可由以下材料形成，所述材料包括但不一定限于：由以下金属：铝（Al）、金（Au）、银（Ag）、铜（Cu）或其它高电导率金属，形成的金属膜。在实施例中，第一金属层112和/或第二金属层114的厚度可在大约一微米和五微米之间（1μm-5μm）。此外，金属层可被图案化。在提供磁屏蔽的实施方式中，第一金属层112和/或第二金属层114可由具有高磁导率/“软”磁特性的材料（即，可被磁化但往往不保持被磁化的材料）形成，所述材料诸如镍铁（例如，Ni80Fe20）或类似金属。
在一些构造中，第一金属层112和/或第二金属层114的厚度可根据操作频率而变化，并且在数字或开关IC中产生可观的电压或电流的位置，所述厚度可为在最大操作频率或一些更高的谐振频率下的磁透入深度的约两倍（2x）厚。例如，在一些构造中，金属厚度可在约二微米和十微米之间（2μm-10μm）的范围内。然而，仅通过举例的方式提供该范围，并不意味着成为本发明的限制。因此，可使用其它金属厚度。
第一晶粒108和/或第二晶粒110可包括一个或多个传输元件，诸如可见光LED、红外线LED，等等。此外，第一晶粒108和/或第二晶粒110可包括一个或多个接收元件，诸如光传感器（例如，可见光传感器、红外线传感器，等等）。在实施例中，第一晶粒108和/或第二晶粒110可包括波导。半导体芯片封装100可包括设置在第一晶粒108与第一腔104之间和/或第二晶粒110与第二腔106之间的填料118。填料118可包括胶层，所述胶层用于相对于载体基底表面将晶粒平面化。在实施例中，填料118的厚度可被选择为填充晶粒和腔周围的间隙并且使间隙变平。
第一晶粒108和/或第二晶粒110可与载体基底102绝缘并且可彼此绝缘，以及与外部装置、电场、磁场等绝缘。例如，在实施例中，第一金属层112可被构造为用于使第一晶粒108与第二晶粒110热绝缘的散热器。此外，第一金属层112可连接到导电柱120以使热传导离开IC结构。另外，第一金属层112可包括用于防止或减少光装置产生的光渗透到载体基底102中的反射表面。反射表面可反射基本上全部的入射辐射或它们的一部分。如本文所用，术语“反射表面”意指反射和半反射表面二者，包括这样的表面，所述表面被构造为反射具有一个波长的辐射，同时允许另一波长的辐射渗透所述表面。例如，第一晶粒108可包括LED。第一金属层112还可防止光到达第二晶粒110。例如，第二晶粒110可包括光传感器，当两个切块在载体基底102被布置为靠的很近时，该光传感器可以其它方式接收来自包括LED的第一晶粒108产生的光的干涉。
在实施例中，第一晶粒108和/或第二晶粒110可包括光电探测器（例如，光电二极管、光电晶体管或被构造为检测可见光光谱和/或红外线光谱中的电磁辐射的另一装置）。在实施例中，在载体基底102与第一晶粒108和/或第二晶粒110之间形成有屏蔽层的反射表面可包括：滤光片（滤波器），诸如阻挡滤光片（例如，被构造为减少红外光的传输同时允许可见光通过的红外线阻挡滤光片）；彩色选择滤光片（color pass filter）（例如，被构造为过滤有限波长光谱范围内的可见光的彩色滤光片，所述过滤即通过阻挡（例如，吸收或反射）一个波长光谱范围内的可见光同时允许另一波长光谱范围内的可见光通过滤光片）；干涉滤光片（例如，被构造为过滤红外光的红外线截止干涉滤光片或者允许特定波长范围内的可见光通过的滤光片）。在实施例中，可利用各种沉积技术形成彩色选择滤光片，所述技术诸如旋涂法和/或光图案化（例如，针对吸收滤光片构成）。同样，针对彩色干涉滤光片构成可使用合适的溅射和镀敷技术。此外，缓冲层可形成在载体基底102的表面上以封闭装入彩色选择滤光片和为彩色选择滤光片提供保护。缓冲层可由诸如苯并环丁烯（BCB）聚合物等的聚合物材料构成。然而，根据构思也可使用其它缓冲材料。
示例制造工艺
以下讨论描述了用于制造3D芯片封装的示例技术，所述3D芯片封装包括具有形成在其中的两个或更多个腔的载体基底，其中IC结构在腔附着到所述载体基底，并且在载体基底与一个或多个IC结构之间进行屏蔽。图3示出了在示例实施方式中用于制造3D芯片封装的工艺300，所述3D芯片封装诸如图1和图2中所示并在以上描述的3D芯片封装100。
在图示工艺300中，第一腔和第二腔可形成在载体基底中（方框310）。例如，参见图4，第一腔104和第二腔106可通过湿蚀刻（各向同性或各向异性）、干蚀刻、激光消融或其它各种技术（包括其它消融技术）等形成在载体基底102中。在实施例中，第一腔104和/或第二腔106可形成为正方形（例如，如图1中所示）或梯形（例如，如图4中所示）。
在一些实施方式中，一个或多个屏蔽层和/或介电层可随后形成在第一腔和/或第二腔中（方框320）。例如，继续参照图4，通过利用物理气相沉积（PVD）、化学气相沉积、或其它各种镀敷技术（诸如电镀和/或无电镀），第一金属层112可沉积在第一腔104和/或第二腔106内侧。在一些情况下，屏蔽层可被涂敷到整个载体基底102，并随后被蚀刻掉从而留下屏蔽层的一个或多个部分，诸如留下形成在第一腔104和/或第二腔106中的屏蔽层。此外，可通过留下在第一腔104和第二腔106之间的屏蔽层的连接部分（诸如用于介电耦合等）将屏蔽层的多个部分连接在一起。
在其它实施方式中，一个或多个屏蔽层可形成在第一IC结构和/或第二IC结构上（方框322）。例如，参见图5，第一金属层112可沉积（涂布）在第一晶粒108和/或第二晶粒110的背侧上。在实施例中，在施加第一金属层112的过程中，第一晶粒108和/或第二晶粒110可保持在载体122上。在另一实施方式中，一个或多个屏蔽层可形成在第一腔和/或第二腔中，并形成在第一IC结构和/或第二IC结构上（方框320和322）。例如，继续参照图4和图5，一个第一金属层112可沉积在第一腔104内侧，并且另一第一金属层112可沉积（涂布）在第一晶粒108的背侧。此外，一个第一金属层112可沉积在第一腔104的内侧，并且另一第一金属层112可沉积（涂布）在第二晶粒110的背侧。在一些实施方式中，一个或多个屏蔽层可连接到一个或多个导电柱（方框324）。例如，参见图1和图2，第一金属层112可连接到延伸到载体基底102中的导电柱120，以使热传导离开第一晶粒108和/或第二晶粒110。
导电柱120可形成为包括铜或另一导电材料的小间距柱，其形成在第一晶粒108、第二晶粒110和/或载体基底102上。在实施例中，柱120可通过干膜抗蚀剂光刻工艺形成。干膜抗蚀剂光刻工艺可包括在第一晶粒108、第二晶粒110和/或载体基底102上形成诸如铜的导电材料的种子层。然后，可将干膜层合到种子层上。接着，可使用负性光刻胶工艺将柱120的形状曝光（photoexpose）到干膜上并在种子层上创建孔。然后，可通过将导电材料沉积到干膜的孔中而将柱120从底部向上电镀。应该注意的是，仅通过举例的方式提供干膜抗蚀剂光刻工艺，而不意味着成为本发明的限制。因此，可利用其它制造技术、导电材料等形成柱120。
接着可在第一腔和/或第二腔中形成填料（方框330）。例如，继续参照图1和图2，填料118可被布置在第一晶粒108与第一腔104之间和/或第二晶粒110与第二腔106之间。应该注意的是，虽然在附图中示出了填料118被布置在第一晶粒108与第一腔104之间以及在第二晶粒110与第二腔106之间，但是在其它实施方式中，根据本发明的3D芯片封装可不包括在IC结构及其对应腔之间的填料。因此，IC结构可与屏蔽层直接接触。然后，第一IC结构可在第一腔内至少部分地附着到载体基底（方框340）。接着，第二IC结构可在第二腔内至少部分地附着到载体基底（方框350）。例如，继续参照图1和图2，第一晶粒108和/或第二晶粒110可通过湿蚀刻、干蚀刻或通过其它各种切割技术成型。此外，基于晶粒成型、腔蚀刻技术等等，第一晶粒108和第二晶粒110可通过具有多种定位精度的拾放工具、自对齐技术、自组装技术等组装到第一腔104和第二腔106中。
介电层可随后形成在载体基底的顶表面上（方框360）。例如，继续参照图1和图2，介电层124可在第一晶粒108和第二晶粒110之上沉积在载体基底102上。接着，互连金属镀层可形成在第一IC结构和第二IC结构之间，以将它们连接在一起（方框370）。例如，继续参照图1和图2，互连金属镀层126可由与第一金属层112和/或第二金属层114相同的材料形成，并沉积在第一晶粒108和/或第二晶粒110上，从而连接到半导体芯片封装100中包括的IC。在实施例中，与第一晶粒108和/或第二晶粒110的连接可通过利用引线键合、焊料凸点等等提供。然后，一个或多个屏蔽层可形成在第一IC结构和/或第二IC结构上（方框380）。例如，继续参照图1和图2，第二金属层114可沉积在半导体芯片封装100上。接着，钝化层可形成在互连金属镀层上（方框390）。例如，继续参照图1和图2，钝化层128可沉积在半导体芯片封装100上。
结论
虽然已经用针对结构性特征和/或工艺操作在语言上描述了主题，但是应该理解，在权利要求中限定的主题不一定限于上述具体特征或作用。另外，上述具体特征和作用作为实施权利要求的示例的形式被公开。

Claims (20)

1.一种器件，其包括：
载体基底，限定第一腔和第二腔；
第一结构，在所述第一腔中至少部分地附着到所述载体基底，所述第一结构包括电子电路；
第二结构，在所述第二腔中至少部分地附着到所述载体基底，所述第二结构包括电子电路；以及
屏蔽层，设置在所述载体基底与所述第一结构或所述第二结构的至少一个之间，以至少基本上使所述第一结构或所述第二结构的至少一个以电绝缘、磁绝缘、光绝缘或热绝缘方式的至少一种绝缘。
2.根据权利要求1所述的半导体器件，其特征在于，所述屏蔽层被构造为用于使所述第一结构与所述第二结构热绝缘的散热器。
3.根据权利要求2所述的半导体器件，其特征在于，所述屏蔽层连接到导电柱，以使热传导离开所述第一结构或所述第二结构的至少一个。
4.根据权利要求1所述的半导体器件，其特征在于，所述屏蔽层包括用于反射所述第一结构或所述第二结构的至少一个产生的光的反射表面。
5.根据权利要求1所述的半导体器件，其特征在于，还包括设置在所述第一结构或所述第二结构的至少一个的上方的第二屏蔽层。
6.根据权利要求1所述的半导体器件，其特征在于，所述第一结构和所述第二结构是同构的。
7.根据权利要求1所述的半导体器件，其特征在于，所述第一结构和所述第二结构是异构的。
8.根据权利要求4所述的半导体器件，其特征在于，所述第一结构包括数字电路，并且所述第二结构包括模拟电路。
9.根据权利要求4所述的半导体器件，其特征在于，所述第一结构包括发光器件，并且所述第二结构包括光传感器件。
10.一种方法，包括：
在载体基底中形成第一腔和第二腔；
将第一结构在所述第一腔中至少部分地附着到所述载体基底，所述第一结构包括电子电路；
将第二结构在所述第二腔中至少部分地附着到所述载体基底，所述第二结构包括电子电路；以及
在所述载体基底与所述第一结构或所述第二结构的至少一个之间形成屏蔽层，以至少基本上使所述第一结构或所述第二结构的至少一个以电绝缘、磁绝缘、光绝缘或热绝缘方式的至少一种绝缘。
11.根据权利要求10所述的半导体器件，其特征在于，所述屏蔽层被构造为用于使所述第一结构与所述第二结构热绝缘的散热器。
12.根据权利要求11所述的半导体器件，其特征在于，还包括将所述屏蔽层连接到导电柱，所述导电柱被构造为使热传导离开所述第一结构或所述第二结构的至少一个。
13.根据权利要求10所述的半导体器件，其特征在于，所述屏蔽层包括被构造为用于反射所述第一结构或所述第二结构的至少一个产生的光的反射表面。
14.根据权利要求10所述的半导体器件，其特征在于，还包括在所述第一结构或所述第二结构的至少一个的上方形成第二屏蔽层。
15.根据权利要求10所述的半导体器件，其特征在于，所述第一结构包括数字电路，并且所述第二结构包括模拟电路。
16.根据权利要求10所述的半导体器件，其特征在于，所述第一结构包括发光器件，并且所述第二结构包括光传感器件。
17.一种器件，其包括：
载体基底，限定第一腔和第二腔；
第一结构，在所述第一腔中至少部分地附着到所述载体基底，所述第一结构包括电子电路；
第二结构，在所述第二腔中至少部分地附着到所述载体基底，所述第二结构包括电子电路；以及
介电屏蔽层，设置在所述载体基底与所述第一结构和所述第二结构之间，以将所述第一结构和所述第二结构介电耦合。
18.根据权利要求17所述的半导体器件，其特征在于，所述介电屏蔽层包括用于反射所述第一结构或所述第二结构的至少一个产生的光的反射表面。
19.根据权利要求17所述的半导体器件，其特征在于，还包括设置在所述第一结构或所述第二结构的至少一个的上方的第二屏蔽层。
20.根据权利要求17所述的半导体器件，其特征在于，所述第一结构包括数字电路，并且所述第二结构包括模拟电路。
CN201210417388.6A 2011-10-28 2012-10-26 具有屏蔽结构的3d芯片封装 Active CN103094257B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/284,116 2011-10-28
US13/284,116 US8686543B2 (en) 2011-10-28 2011-10-28 3D chip package with shielded structures

Publications (2)

Publication Number Publication Date
CN103094257A true CN103094257A (zh) 2013-05-08
CN103094257B CN103094257B (zh) 2018-09-28

Family

ID=48084489

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210417388.6A Active CN103094257B (zh) 2011-10-28 2012-10-26 具有屏蔽结构的3d芯片封装

Country Status (3)

Country Link
US (1) US8686543B2 (zh)
CN (1) CN103094257B (zh)
DE (1) DE102012110000A1 (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105552061A (zh) * 2014-10-22 2016-05-04 日月光半导体制造股份有限公司 半导体封装元件
CN106409774A (zh) * 2015-07-31 2017-02-15 富葵精密组件(深圳)有限公司 屏蔽罩、封装结构及封装结构制作方法
CN106537570A (zh) * 2014-09-26 2017-03-22 德州仪器公司 用于半导体封装的印刷互连件
CN110109736A (zh) * 2013-12-09 2019-08-09 超威半导体公司 3d芯片系统中的电压下降缓解

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8846452B2 (en) * 2012-08-21 2014-09-30 Infineon Technologies Ag Semiconductor device package and methods of packaging thereof
US9484313B2 (en) * 2013-02-27 2016-11-01 Advanced Semiconductor Engineering, Inc. Semiconductor packages with thermal-enhanced conformal shielding and related methods
US20140254991A1 (en) * 2013-03-06 2014-09-11 Analog Devices Technology Isolator
DE102013021519A1 (de) * 2013-12-12 2015-06-18 Connaught Electronics Ltd. Bilderfassungseinrichtung mit einem Bildsensor und einem thermischen Infrarotsensor sowie Kraftfahrzeug mit einer Bilderfassungseinrichtung
KR102187809B1 (ko) 2014-02-21 2020-12-07 삼성전자주식회사 자기 차폐부를 가지는 반도체 패키지 제조방법
US9786613B2 (en) 2014-08-07 2017-10-10 Qualcomm Incorporated EMI shield for high frequency layer transferred devices
WO2017093281A1 (en) * 2015-11-30 2017-06-08 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Electronic component packaged in component carrier serving as shielding cage
US10225964B2 (en) 2016-03-31 2019-03-05 Apple Inc. Component shielding structures with magnetic shielding
WO2018182656A1 (en) * 2017-03-30 2018-10-04 Intel Corporation Ultra-low profile package shielding technique using magnetic and conductive layers for integrated switching voltage regulator
DE102017108048A1 (de) 2017-04-13 2018-10-18 Infineon Technologies Austria Ag Halbleitervorrichtung mit einer grabenstruktur
CN107452720B (zh) * 2017-08-03 2020-04-17 华天科技（昆山）电子有限公司 芯片扇出封装结构、多芯片集成模块及晶圆级封装方法
US10181449B1 (en) * 2017-09-28 2019-01-15 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure
KR20190075647A (ko) * 2017-12-21 2019-07-01 삼성전자주식회사 팬-아웃 반도체 패키지
US10727086B2 (en) * 2018-03-24 2020-07-28 Maxim Integrated Products, Inc. Optical sensor packaging system
US11177226B2 (en) * 2018-09-19 2021-11-16 Intel Corporation Flexible shield for semiconductor devices
CN111372369B (zh) 2018-12-25 2023-07-07 奥特斯科技(重庆)有限公司 具有部件屏蔽的部件承载件及其制造方法
US10998489B2 (en) * 2019-01-14 2021-05-04 Nxp B.V. Magnetic shielding structure for MRAM array
WO2021114281A1 (zh) * 2019-12-13 2021-06-17 华为技术有限公司 一种电子元件、带电子元件的电路板和电子设备
US11626337B2 (en) * 2020-05-19 2023-04-11 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and methods of manufacturing semiconductor devices
US11810895B2 (en) * 2021-10-14 2023-11-07 Honeywell Federal Manufacturing & Technologies, Llc Electrical interconnect structure using metal bridges to interconnect die

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030042582A1 (en) * 2001-09-06 2003-03-06 Crane Stanford W. Semiconductor package
US6590346B1 (en) * 2001-07-16 2003-07-08 Alien Technology Corporation Double-metal background driven displays
CN1921141A (zh) * 2006-09-11 2007-02-28 友达光电股份有限公司 低反射率的自发光单元显示器的像素单元结构
TW201042735A (en) * 2009-05-25 2010-12-01 Nan Ya Printed Circuit Board Packing substrate with embedded chip

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5998868A (en) * 1998-02-04 1999-12-07 International Business Machines Corporation Very dense chip package
US6932519B2 (en) * 2000-11-16 2005-08-23 Shipley Company, L.L.C. Optical device package
WO2004102681A1 (de) * 2003-05-19 2004-11-25 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Optoelektronisches bauelement mit einer leuchtdiode und einem lichtsensor
US8349653B2 (en) 2010-06-02 2013-01-08 Maxim Integrated Products, Inc. Use of device assembly for a generalization of three-dimensional metal interconnect technologies

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6590346B1 (en) * 2001-07-16 2003-07-08 Alien Technology Corporation Double-metal background driven displays
US20030042582A1 (en) * 2001-09-06 2003-03-06 Crane Stanford W. Semiconductor package
CN1921141A (zh) * 2006-09-11 2007-02-28 友达光电股份有限公司 低反射率的自发光单元显示器的像素单元结构
TW201042735A (en) * 2009-05-25 2010-12-01 Nan Ya Printed Circuit Board Packing substrate with embedded chip

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110109736A (zh) * 2013-12-09 2019-08-09 超威半导体公司 3d芯片系统中的电压下降缓解
CN110109736B (zh) * 2013-12-09 2023-03-07 超威半导体公司 3d芯片系统中的电压下降缓解
CN106537570A (zh) * 2014-09-26 2017-03-22 德州仪器公司 用于半导体封装的印刷互连件
CN105552061A (zh) * 2014-10-22 2016-05-04 日月光半导体制造股份有限公司 半导体封装元件
CN106409774A (zh) * 2015-07-31 2017-02-15 富葵精密组件(深圳)有限公司 屏蔽罩、封装结构及封装结构制作方法
CN106409774B (zh) * 2015-07-31 2019-04-26 鹏鼎控股(深圳)股份有限公司 屏蔽罩、封装结构及封装结构制作方法

Also Published As

Publication number Publication date
CN103094257B (zh) 2018-09-28
DE102012110000A1 (de) 2013-05-02
US20130105950A1 (en) 2013-05-02
US8686543B2 (en) 2014-04-01

Similar Documents

Publication Publication Date Title
CN103094257A (zh) 具有屏蔽结构的3d芯片封装
US8159052B2 (en) Apparatus and method for a chip assembly including a frequency extending device
US9406738B2 (en) Inductive structure formed using through silicon vias
US20190172902A1 (en) Semiconductor Device and Method of Forming Substrate Including Embedded Component with Symmetrical Structure
US7033927B2 (en) Apparatus and method for thermal isolation, circuit cooling and electromagnetic shielding of a wafer
CN103579169B (zh) 半导体封装及半导体封装基座的制造方法
US10636778B2 (en) Isolator integrated circuits with package structure cavity and fabrication methods
US7078794B2 (en) Chip package and process for forming the same
US20050101116A1 (en) Integrated circuit device and the manufacturing method thereof
US20130249031A1 (en) Quantum Efficiency Back Side Illuminated CMOS Image Sensor And Package, And Method Of Making Same
JP4597512B2 (ja) 複数の集積回路デバイスを含む単一パッケージ及び半導体デバイスをパッケージする方法
US20130168791A1 (en) Quantum Efficiency Back Side Illuminated CMOS Image Sensor And Package, And Method Of Making Same
KR101757749B1 (ko) 고 대역폭 상호 연결을 위한 단열 구조
US10276490B2 (en) Isolation devices with faraday shields
EP2026082A2 (en) Double sided integrated processing and sensing chip
US9184113B1 (en) Methods of forming coaxial feedthroughs for 3D integrated circuits
CN104916623A (zh) 半导体封装和制造半导体封装基底的方法
CN102623424B (zh) 晶片封装体及其形成方法
CN117690920A (zh) 集成封装及其制造方法
KR20140081550A (ko) 배선 구조물을 구비하는 패키지 기판 구조물 및 이를 포함하는 반도체 패키지, 패키지 기판 구조물 및 반도체 패키지의 제조 방법
CN109786362A (zh) 无焊垫外扇晶粒叠层结构及其制作方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant