201042735 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種具有埋入式晶片的基板結構，特 別是有關於一種具有散熱構造的埋入式晶片的基板結構， 可以將晶片產生的熱傳遞至基板外。 【先前技術】 現今電路板產品趨勢為輕、薄、短、小、高速、高頻 ❹和多功能，為了滿足需求，半導體封裝已從BGA(；BallGl>id Ar^y，球柵陣列）封裝和Fc (FUpChip，覆晶封裝）進化 為三維雄疊形結構’或於載板表面安裝元件，以或WB 方式將各Package接合，而形成一多功能的結構體。根據 不同的主動或被動元件，而產生各種新型封裝結構，如MCp (Multi Chip Package )、poP ( Packa名e on Package )及 SIp (System In Package )等。 矛J用FC方式或打線接合（wb，Wire Bonding )將主 ❹動元件與承載板形成一封裝結構體，並將一個以上之封裝 進行堆疊或安裝於同一載板表面上。考量各元件間互相透 過線路連接及載板表面由於面積及體積增加 ，而使得佈線 難度愈來愈高’故業界開始研發將主動或被動元件埋入載 板内之技術。 第1圖為一習知的埋入式晶片的基板構造，其包括一 承載板10，一盲凹槽12形成於該承載板1〇，一半導體晶 片.C以黏著劑F固定於盲凹槽12的底部，一第一絕緣層 20形成於承載板10上，並覆蓋半導體晶月c以及填入盲 201042735 凹槽12，一第一線路層30形成於該第一絕緣層20上，並 以導電盲孔32連接於半導體晶片C，一第二絕緣層40形 成於該第一線路層30上，一第二線路層50形成於第二絕 緣層40上，並電性連接於第一線路層30，一防銲層60形 成於第二線路層50上，錫球70形成於防銲層60上並電性 連接於第二線路層50。半導體晶片C的訊號經由第一線路 層30及第二線路層50雨傳遞至錫球70。 由於電子產品之操作頻率愈來愈高且愈來愈多的元件 〇 需安裝於同一載板，故主動元件與被動元件所產生之熱能 持續增加，故對於埋入式封裝而言，散熱結構愈發重要。 在第1圖的構造中，為單顆之埋入式晶片結構，單邊 增層，而且無散熱的設計，晶片所產生的熱無法導出。 【發明内容】 有鑑於此，本發明的目的在於提供一種具有散熱構造 或設計的埋入式晶片的基板結構。 ❹ 本發明之埋入式晶片的基板結構的一較佳實施例包 括：一承載板、一第一線路層、一第二線路層、一第一絕 緣層、一第二絕緣層、至少一導熱膠、至少一第一半導體 晶片、一第三線路層、一第四線路層、一第三絕緣層、一 第四絕緣層、一第五線路廣、一第六線路層、一第一防鮮 層、一第二防鋒層、一第一錫球以及一第二錫球。承載板 具有一第一面、一第二面以及至少一第一通孔，第二面係 _對於第一面，第一通孔係連通第一面與第二面，第一線 路層形成於第一面上；第二線路層形成於第二面上，並藉 6 201042735 由金屬導通孔電性連接於第一線路層；第一絕緣層形成於 第一面及第一線路層上；第二絕緣層形成於第二面及第二 線路層上；導熱膠形成於第一通孔中，並鄰接於第二面； 第一半導體晶片固定於導熱膠上；第三線路層形成於第一 絕緣層上，並透過導盲孔電性連接於第一半導體晶片；第 四線路層形成於第二絕緣層上，並透過導盲孔導通於導熱 膠；第三絕緣層形成於第三線路層上；第五線路層形成於 第三絕緣層上，並透過導盲孔電性連接於第三線路層；第 q 一防鲜層覆蓋第五線路層以及第三絕緣層；第一錫球形成 於第一防銲層上並電性連接於第五線路層；第四絕緣層形 成於第四線路層上；第六線路層形成於第四絕緣層上，並 透過導盲孔電性連接於第四線路層；第二防銲層覆蓋第六 線路層以及第四絕緣層；第二錫球形成於第二防銲層上並 導通於第六線路層，其中第一半導體晶片的訊號依序經由 第三線路層及第五線路層傳遞至第一錫球，第一半導體晶 片產生的熱，依序經由導熱膠、第二線路層、第四線路層 ❹ 及第六線路層而傳遞至第二錫球，以進行散熱。 在上述之較佳實施例中，承載板更包括至少一第二通 孔，連通該第一面與該第二面，而該埋入式晶片基板結構 更包括：至少一導熱膠以及至少一第二半導體晶片。導熱 膠形成於該第二通孔中，並鄰接於該第一面，該第三線路 層係透過導盲孔導通於該導熱膠；至少一第二半導體晶 片，固定於該導熱膠上，該第四線路層透過導盲孔電性連 接於該第二半導體晶片5其中該第二半導體晶片的訊號依 序經由該第四線路層及該第六線路層傳遞至第二錫球，該 7 201042735 第二半導體晶片產生的熱，依序經由該導熱膠、該第 路層及該第五線路層而傳遞至該第一錫球，以進行散熱 為了讓本發明之上述和其他目的、特徵和優點 顯易懂’下文特舉一較佳實施例，並配合所附圖示，作詳 細說明如下 【實施方式】 第2圖為本發明的埋入式晶片的基板結構的第〆實施 ^ 例的不意圖 。該基板結構的核心為/承載板100 ’承栽板 100包括一第一面1〇2以及一第二面1〇4，第一面102與第 二面104係相對設置，然後在承載板100上開設複數個第 一通孔106、複數個第二通孔108 (在第2圖中，為了方便 說明，僅表示一第一通孔106以及一第二通孔1〇8)以及 複數個金屬導通孔110，第一通孔106及第二通孔1〇8貫 穿承載板100並連通第一面102及第二面1〇4，金屬導通 孔Π0中則填充有灌孔樹脂40:2。對第一面102及第二面 〇 104進行電鍍而形成第一線路層202及第二線路層204,並 在第一通孔106及第二通孔1〇8中形成金屬通孔凹槽2〇6, 金屬通孔凹槽206係連通第一線路層202及第二線路層 204，在第一通孔106中填入一導熱膠5〇5，導熱膠5〇5係 接觸於金屬通孔凹槽206並鄰接於第二面1〇4，在第二通 孔108中填入導熱膠505，導熱膠505係接觸於金屬通孔 凹槽206並鄰接於第一面1〇2，一第一半導體晶片602係 設於導熱膠· 505上，一第二半導體晶片6〇4係設於另一導 熱膠505上，在第一線路層202上形成一第一絕緣層（介 8 201042735 電層）302 ’並覆蓋第-半導體晶片6〇2及填入第 106 ’在第二線路Ρ04上形成一第二絕緣層3〇4， Ο 〇 第二半導體晶片_及填人第二通孔刚。在第_絕緣^ 302上形成-第三線路層7〇2,第三線路層观經由填 鐘所形成之導盲孔706電性連接於第—半導體晶片· 而且經由導熱膠505熱連接於第二線路層施。在第 緣層304上形成一第四線路層7〇4，第四線路層取:由 填孔電鐘所形成的導盲孔寫電性連接於第二半導體 604，而且經由導㈣505熱連接於第一線路層2〇2。: 三線路層702上形成-第三絕緣& 8〇2，在第四線路層取 上形成-第四絕緣層804 ’在第三絕緣| 8〇2上形成_第 五線路層術’第玉線路層902係透過導盲孔寫導通於 第三線路層7G2’在第四絕緣層謝上形成一第六線路層 904 ’第六線路層904係透過導盲孔7〇6導通於第四線路層 704，在第五線路層902上形成一第一防銲層92〇，在第一 防銲層920上設置一第一錫球1020，第一錫球1〇2〇電性 導通於第五線路層902,在第六線路層9〇4上形成一第二 防銲層940，在第二防銲層940上設置一第二錫球1〇4〇， 第二锡球1040電性導通於第六線路層904。 以上述的構造而s ’層與層間通過導盲孔706電性連 接或導熱，而第一半導體晶片602的訊號依序經由第三線 路層702、第玉線路層902而傳遞至第一錫球1〇2〇，藉此 可以傳遞至基板結構的外部，第一半導體晶片6〇2產生的 熱依序經由導熱膠505、，第二線路層2〇4、第四線路層7〇4 以及第六線路層904傳遞至第二錫球〗，而將熱傳遞至 9 201042735 基板結構以外，進行散熱。第二半導體晶片604的訊號依 序經由第四線路層704、第六線路層904而傳遞至第二錫 球1040 ’藉此可以傳遞至基板結構的外部，第二半導體晶 片604產生的熱依序經由導熱膠5〇5、第一線路層202、第 三線路層702以及第五線路層9〇2傳遞至第一錫球1020， 而將熱傳遞至基板結構以外，進行散熱。如此埋設於基板 結構中的晶片的熱可藉由本發明所設置的導熱路徑導出至 基板結構之外。 Q 第3圖為本發明的埋入式晶片的基板結構的第二實施 例的示意圖。第二實施例與第一實施例的差異在於第二實 施例是在承載板100上的第一面102内開設第一盲凹槽 106’，並在第二面104開設複數個第一通孔106”，連通第 一盲凹槽106’與第二面104 ,在第二面1〇4上亦開設第二 盲凹槽108 ，並在第一面102開設複數個第二通孔 108”，連通第二盲凹槽108’與第一面金屬盲凹槽 206’係以電鍍方式形成於第一盲凹槽106’及第一通孔 ❹ 106”中並連通第一線路層202及第二線路層204。由於其 餘構造與第一實施例相同，因此給予相同的標號並省略其 說明。 第一 _半導體晶片60.2的訊號依序經由第二線路層 702、第五線路層902而傳遞至第一錫球1020，藉此可以 傳遞至基板結構的外部，第一半導體晶片602產生的熱依 序經由導熱膠505、金屬盲凹槽206,、第一通孔106”、第 二線路層204、第四線路層704以及第六線路層904傳遞 至第二錫球1040,而將熱傳遞至基板結構以外，進行散熱。 201042735 第一半導體晶片604的訊號佑皮Α 现依序經由第四線路層704、第 六線路層904而傳遞至第-锯1+ ^ ’弟—Μ 1_，藉此可以傳遞至基 板結構的外部，第二半導體晶 守日曰片604產生的熱依序經由導 熱膠505、金屬盲凹槽206,、第-υ丨而，，墙^ 昂一通孔108、第一線路層 202、第三線路層702以及镇& 及第五線路層902傳遞至第一錫球 1020，而將熱傳遞至基板結構以外，進行散熱。 Ο201042735 VI. Description of the Invention: [Technical Field] The present invention relates to a substrate structure having a buried wafer, and more particularly to a substrate structure of a buried wafer having a heat dissipation structure, which can be produced by a wafer Heat is transferred to the outside of the substrate. [Prior Art] Today's circuit board products are trending light, thin, short, small, high speed, high frequency, and versatile. In order to meet the demand, semiconductor packages have been packaged from BGA (BallGl>id Ar^y, ball grid array). And Fc (FUpChip, flip-chip package) evolved into a three-dimensional male-stacked structure' or mounted on the surface of the carrier, and each package was joined in WB mode to form a multifunctional structure. Various new package structures, such as MCp (Multi Chip Package), poP (Packa name e on Package), and SIp (System In Package), are generated depending on different active or passive components. The spear J forms a package structure with the carrier element and the carrier board by FC or wire bonding (wb, Wire Bonding), and stacks or mounts one or more packages on the same carrier surface. Considering that the components are connected to each other through the line and the surface of the carrier is increased due to the increased area and volume, the industry has begun to develop technologies for embedding active or passive components in the carrier. 1 is a conventional substrate structure of a buried wafer, which includes a carrier 10 on which a blind recess 12 is formed, and a semiconductor wafer C is fixed to the blind recess with an adhesive F. A first insulating layer 20 is formed on the carrier 10 and covers the semiconductor crystal c and fills the recesses 12,427,425, and a first wiring layer 30 is formed on the first insulating layer 20, and The conductive blind vias 32 are connected to the semiconductor wafer C. A second insulating layer 40 is formed on the first wiring layer 30. A second wiring layer 50 is formed on the second insulating layer 40 and electrically connected to the first circuit layer. 30. A solder resist layer 60 is formed on the second wiring layer 50. The solder ball 70 is formed on the solder resist layer 60 and electrically connected to the second wiring layer 50. The signal of the semiconductor wafer C is transferred to the solder ball 70 via the first wiring layer 30 and the second wiring layer 50. Since the operating frequency of electronic products is getting higher and higher and more and more components need to be mounted on the same carrier board, the thermal energy generated by the active components and the passive components continues to increase, so for the buried package, the heat dissipation structure is increased. It is important. In the configuration of Fig. 1, a single buried wafer structure, unilaterally layered, and without heat dissipation design, the heat generated by the wafer cannot be derived. SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a substrate structure of a buried wafer having a heat dissipation structure or design. A preferred embodiment of the substrate structure of the embedded wafer of the present invention comprises: a carrier board, a first circuit layer, a second circuit layer, a first insulating layer, a second insulating layer, and at least one heat conducting a glue, at least a first semiconductor wafer, a third circuit layer, a fourth circuit layer, a third insulating layer, a fourth insulating layer, a fifth line wide, a sixth circuit layer, and a first fresh-keeping layer a layer, a second anti-front layer, a first solder ball and a second solder ball. The carrier board has a first surface, a second surface, and at least one first through hole. The second surface is for the first surface, the first through hole is connected to the first surface and the second surface, and the first circuit layer is formed on the first circuit layer. a first circuit layer is formed on the second surface, and is electrically connected to the first circuit layer by a metal via hole by 6 201042735; the first insulating layer is formed on the first surface and the first circuit layer; The second insulating layer is formed on the second surface and the second circuit layer; the thermal conductive adhesive is formed in the first through hole and adjacent to the second surface; the first semiconductor wafer is fixed on the thermal conductive adhesive; the third circuit layer is formed on the first surface The insulating layer is electrically connected to the first semiconductor wafer through the via hole; the fourth circuit layer is formed on the second insulating layer and is electrically connected to the thermal conductive paste through the via hole; and the third insulating layer is formed on the third circuit layer The fifth circuit layer is formed on the third insulating layer and electrically connected to the third circuit layer through the via hole; the qth anti-fresh layer covers the fifth circuit layer and the third insulating layer; the first solder ball is formed On the first solder mask and electrically connected to the fifth circuit layer; The edge layer is formed on the fourth circuit layer; the sixth circuit layer is formed on the fourth insulation layer and electrically connected to the fourth circuit layer through the via hole; the second solder resist layer covers the sixth circuit layer and the fourth insulation layer a second solder ball is formed on the second solder resist layer and is electrically connected to the sixth circuit layer, wherein the signal of the first semiconductor wafer is sequentially transmitted to the first solder ball via the third circuit layer and the fifth circuit layer, first The heat generated by the semiconductor wafer is sequentially transferred to the second solder ball via the thermal conductive paste, the second wiring layer, the fourth wiring layer, and the sixth wiring layer for heat dissipation. In the above preferred embodiment, the carrier board further includes at least one second through hole connecting the first surface and the second surface, and the embedded wafer substrate structure further comprises: at least one thermal conductive adhesive and at least one Two semiconductor wafers. a thermal conductive adhesive is formed in the second through hole and adjacent to the first surface, the third circuit layer is electrically connected to the thermal conductive adhesive through the guiding blind hole; and at least a second semiconductor wafer is fixed on the thermal conductive adhesive. The fourth circuit layer is electrically connected to the second semiconductor wafer 5 through the via hole, wherein the signal of the second semiconductor wafer is sequentially transmitted to the second solder ball via the fourth circuit layer and the sixth circuit layer, the 7 201042735 The heat generated by the second semiconductor wafer is sequentially transferred to the first solder ball via the thermal conductive paste, the via layer and the fifth circuit layer for heat dissipation in order to achieve the above and other objects, features and advantages of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S) The following is a detailed description of the preferred embodiment as follows: [Embodiment] FIG. 2 is a second embodiment of the substrate structure of the embedded wafer of the present invention. intention. The core of the substrate structure is/supporting plate 100. The receiving plate 100 includes a first surface 1〇2 and a second surface 1〇4. The first surface 102 and the second surface 104 are oppositely disposed, and then the carrier plate 100 is disposed. A plurality of first through holes 106 and a plurality of second through holes 108 are opened (in FIG. 2, for convenience of description, only one first through hole 106 and one second through hole 1〇8 are shown) and a plurality of metals The through hole 110, the first through hole 106 and the second through hole 1〇8 penetrate the carrier plate 100 and communicate with the first surface 102 and the second surface 1〇4, and the metal via hole Π0 is filled with the filling resin 40:2. The first surface 102 and the second surface layer 104 are plated to form the first wiring layer 202 and the second wiring layer 204, and the metal via hole 2 is formed in the first through hole 106 and the second through hole 1〇8. 〇6, the metal via hole 206 is connected to the first circuit layer 202 and the second circuit layer 204, and the first through hole 106 is filled with a thermal conductive adhesive 5〇5, and the thermal conductive adhesive 5〇5 is in contact with the metal through hole. The groove 206 is adjacent to the second surface 1〇4, and the second through hole 108 is filled with a thermal conductive adhesive 505, and the thermal conductive adhesive 505 is in contact with the metal through-hole recess 206 and adjacent to the first surface 1〇2, a first A semiconductor wafer 602 is disposed on the thermal conductive paste 505, and a second semiconductor wafer 6 is disposed on the other thermal conductive paste 505 to form a first insulating layer on the first wiring layer 202. 302' and covering the first semiconductor wafer 6〇2 and filling the 106th' form a second insulating layer 3〇4 on the second wiring layer 04, the second semiconductor wafer _ and the second via hole. A third wiring layer 7〇2 is formed on the first insulating layer 302, and the third wiring layer is electrically connected to the first semiconductor wafer through the via hole 706 formed by the filling of the clock, and is thermally connected to the first via the thermal conductive adhesive 505. Two line layer application. A fourth circuit layer 7〇4 is formed on the edge layer 304. The fourth circuit layer is electrically connected to the second semiconductor 604 by a via hole formed by the hole filling clock, and is thermally connected to the second semiconductor via the 504. The first circuit layer 2〇2. : a third wiring layer 702 is formed with a third insulation & 8〇2, and a fourth wiring layer is formed on the fourth wiring layer. The fourth insulating layer 804 is formed on the third insulation | 8〇2. The jade circuit layer 902 is electrically connected to the third circuit layer 7G2 ′ through the via hole to form a sixth circuit layer 904 on the fourth insulating layer. The sixth circuit layer 904 is electrically connected to the fourth through the via hole 7 〇 6 . a first solder resist layer 92 is formed on the fifth circuit layer 902, and a first solder ball 1020 is disposed on the first solder resist layer 920. The first solder ball is electrically connected to the first solder ball 1020. The fifth circuit layer 902 has a second solder resist layer 940 formed on the sixth circuit layer 9〇4, and a second solder ball 1〇4〇 is disposed on the second solder resist layer 940, and the second solder ball 1040 is electrically connected. At the sixth circuit layer 904. In the above configuration, the layer and the interlayer are electrically connected or thermally conductive through the via hole 706, and the signal of the first semiconductor wafer 602 is sequentially transmitted to the first solder ball via the third circuit layer 702 and the jade circuit layer 902. 1〇2〇, thereby being transferred to the outside of the substrate structure, the heat generated by the first semiconductor wafer 6〇2 is sequentially passed through the thermal conductive paste 505, the second wiring layer 2〇4, the fourth wiring layer 7〇4, and The six-line layer 904 is transferred to the second solder ball, and the heat is transferred to the outside of the 9 201042735 substrate structure for heat dissipation. The signal of the second semiconductor wafer 604 is sequentially transmitted to the second solder ball 1040 ′ via the fourth circuit layer 704 and the sixth circuit layer 904 , thereby being transmitted to the outside of the substrate structure, and the heat generated by the second semiconductor wafer 604 is sequentially processed. The heat transfer is performed to the first solder ball 1020 via the thermal conductive paste 5〇5, the first wiring layer 202, the third wiring layer 702, and the fifth wiring layer 9〇2, and heat is transferred to the outside of the substrate structure to dissipate heat. The heat of the wafer thus embedded in the substrate structure can be led out of the substrate structure by the heat conduction path provided by the present invention. Q Fig. 3 is a schematic view showing a second embodiment of the substrate structure of the embedded wafer of the present invention. The difference between the second embodiment and the first embodiment is that the second embodiment has a first blind recess 106 ′ in the first surface 102 on the carrier board 100 and a plurality of first through holes in the second surface 104 . 106", the first blind groove 106' and the second surface 104 are connected, a second blind groove 108 is also formed on the second surface 1〇4, and a plurality of second through holes 108" are opened in the first surface 102, The second blind recess 108 ′ and the first surface metal blind recess 206 ′ are formed in the first blind recess 106 ′ and the first via ❹ 106 ′ in an electroplating manner and communicate with the first wiring layer 202 and the second The circuit layer 204. Since the rest of the configuration is the same as that of the first embodiment, the same reference numerals are given and the description thereof is omitted. The signal of the first semiconductor wafer 60.2 is sequentially transmitted to the first via the second circuit layer 702 and the fifth circuit layer 902. A solder ball 1020 can be transferred to the outside of the substrate structure, and the heat generated by the first semiconductor wafer 602 is sequentially passed through the thermal conductive paste 505, the metal blind recess 206, the first via 106", the second wiring layer 204, The fourth circuit layer 704 and the sixth circuit layer 904 are transferred to the second solder ball 1040, and the heat is transmitted. Transfer to the outside of the substrate structure for heat dissipation. 201042735 The signal of the first semiconductor wafer 604 is sequentially transmitted to the first saw 1 + ^ 'di- Μ 1_ via the fourth circuit layer 704 and the sixth circuit layer 904, thereby being transmitted to the outside of the substrate structure. The heat generated by the second semiconductor crystal slab 604 is sequentially passed through the thermal conductive adhesive 505, the metal blind recess 206, the first cymbal, the wall, the through hole 108, the first circuit layer 202, and the third line. The layer 702 and the town & and fifth circuit layer 902 are transferred to the first solder ball 1020 to transfer heat to the outside of the substrate structure for heat dissipation. Ο
第4圖為本發明的埋入式晶片的基板結構的第三實施 例的示意圖。第三實施例與第—實施例的差異在於第一實 施例中疋在承載板1GG上形成金屬通孔凹槽雇，而本實 施例中則是在承載板100上形成金屬通孔2〇6，，，並以一導 熱材料502’填充於金屬通孔2〇6，，中，而熱連通第一線路層 202及第二線路層204,第一半導體晶片6〇2係設於第一線 路層202上並以一導熱膠505固定於導熱材料5〇2，的介面 及第一線路層202上，同樣地，第二半導體晶片6〇4係設 於第二線路層204上並以一導熱膠505固定於導熱材料 502’的介面及第二線路層204上。由於其餘構造與第一實 施例相同，因此給予相同的標號並省略其說明。 第一半導體晶片602的訊號依序經由第三線路層 702、第五線路層902而傳遞至第一錫球1〇2〇 ,藉此可以 傳遞至基板結構的外部’第一半導體晶片602產生的熱依 序經由導熱膠505、導熱材料502,、第二線路層204、第四 線路層704以及第六線路層904傳遞至第二錫球104〇，而 將熱傳遞至基板結構以外，進行散熱。第二半導體晶片6〇4 的訊號依序經由第四線路層704、.第六線路層904而傳遞 至第二錫球1040，藉此可以傳遞至基板結構的外部，第二 201042735 半導體晶片604產生的熱依序經由導熱膠5〇5、導熱材料 502’、第一線路層2〇2、第三線路層7〇2以及第五線路層 902傳遞至第一錫球1020，而將熱傳遞至基板結構以外， 進行散熱。 第5圖為本發明的埋入式晶片的基板結構的第四實施 例的示意圖。第四實施例與第三實施例的差異在於金屬通 孔206’’係貫穿承載板1〇〇、第一線路層2〇2、第一絕緣層 302、第二線路層702、第一線路層.204、第二絕緣層304、 ❹ 第四線路層704，金屬通孔206，’係連通第三線路層7〇2、 第一線路層202、第二線路層204及第四線路層704，在金 屬通孔206’’中係填充有導熱材料:5〇2，。金屬導通孔11()中 則填充有灌孔樹脂402，第一半導體晶片.6〇2係設於第三 線路層702上，並經由導熱膠505固定於第三線路層7〇2 及導熱材料502’的介面上，第五線路層9〇2電性連接於第 一半導體晶片602 ’第二半導體晶片6〇4經由導熱膠5〇5 固定於第四線路層704上，第六線路層904係電性連接於 ❹第二半導體晶片604。由於其餘構造與第三實施例相同， 因此給予相同的標號並省略其說明。 第一半導體晶片602的訊號依序經由第五線路層9〇2 而傳遞至第一錫球1020,藉此可以傳遞至基板結構的外 部’第一半導體晶片602產生的熱依序經由導熱膠505、 導熱材料502’、金屬通孔206’’、第四線路層704以及第六 線路層904傳遞至第二錫球1〇4〇 ’而將熱傳遞至基板結構 以外，進行散熱。第二半導體晶片604的訊號依序經由第 六線路層904雨傳遞至第二錫球1〇4〇，藉此可以傳遞至基 12 201042735 板結構的外部，第二半導體晶片604產生的熱依序經由導 熱膠505、第四線路層704、第二線路層204、金屬導通孔 110、第一線路層202、第三線路層702以及第五線路層902 傳遞至第一錫球1020，而將熱傳遞至基板結構以外，進行 散熱。 第6圖為本發明的埋入式晶片的基板結構的第五貫施 例的示意圖。第五實施例的構造與第四實施例相似，差異 點在於第一半導體晶片602及第二半導體晶片604均設於 〇 第一防銲層920下方，第一防銲層920係覆蓋第一半導體 晶片602及第二半導體晶片604，而第一錫球1020係直接 電性連接於第一半導體晶片602及第二半導體晶片604 , 第五實施例的金屬導通孔110係填充灌孔樹脂402。由於 其餘構造與第四實施例相同，因此給予相同的標號並省略 其說明。 第一半導體晶片602的訊號直接傳遞至第一錫球 1020，藉此可以傳遞至基板結構的外部，第一半導體晶片 ❹ 602產生的熱依序經由導熱膠505、第五線路層902、第三 線路層702、金屬導通孔110、第四線路層704以及第六線 路層904傳遞至第二錫球1040，而將熱傳遞至基板結構以 外，進行散熱。第二半導體晶片604的訊號直接傳遞至第 一錫球1020，藉此可以傳遞至基板結構的外部，第二半導 體晶片604產生的熱依序經由導熱膠50.5、第五線路層 902、第三線路層702、第一線路層202、金屬導通孔110、 第二線路層204、第四線路層704以及第六.線路層904傳 遞至第二錫球1040，而將熱傳遞至基板結構以外，進行散 13 201042735 熱。 本發明的埋入式晶片的基板結構可以埋設複數個主動 元件而以不同的方式配置，藉此可提高封裝密度。另外， 本發明的埋入式晶片的基板結構於結構中增加散熱通孔， 並藉由金屬將熱排出，不會產生由於主動元件埋設於基板 中無法散熱而導致過熱的問題。 灌孔、增層結構、填孔電鍍、防銲層塗布與錫球印刷 製程及方法皆為習知技術，本文不多加贅述，僅針對本發 〇 明之新開發之結構與製作做說明。 在上述的實施例中的增層數僅是舉例說明，並非用於 限制本發明，實際的情況是依照產品而調整1其數量可增 加或減少。 導熱凹槽或通孔是依照產品而調整，可在同一結構中 合併使用多種導熱凹槽或通孔，可依照導熱公式而調整位 置。 雖然本發明已以較佳實施例揭露如上，然其並非用以 ❹ 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 14 201042735 【圖式簡單說明】 第1圖為習知的埋入式晶片基板結構的示意圖。 第2圖為本發明的埋入式晶片基板結構的第一實施例 的示意圖。 第3圖為本發明的埋入式晶片基板結構的第二實施例 的示意圖。 第4圖為本發明的埋入式晶片基板結構的第三實施例 的示意圖。 〇 第5圖為本發明的埋入式晶片基板結構的第四實施例 的示意圖。 第6圖為本發明的埋入式晶片基板結構的第五實施例 的示意圖。Fig. 4 is a schematic view showing a third embodiment of the substrate structure of the buried wafer of the present invention. The difference between the third embodiment and the first embodiment is that in the first embodiment, the crucible is formed on the carrier plate 1GG, and in the embodiment, the metal through hole 2〇6 is formed on the carrier board 100. And filling the metal via hole 2〇6 with a heat conductive material 502', and thermally connecting the first circuit layer 202 and the second circuit layer 204, and the first semiconductor wafer 6〇2 is disposed on the first line The layer 202 is fixed on the interface of the heat conductive material 5〇2 and the first circuit layer 202 by a thermal conductive adhesive 505. Similarly, the second semiconductor wafer 6〇4 is disposed on the second circuit layer 204 and is thermally conductive. The glue 505 is fixed to the interface of the heat conductive material 502' and the second circuit layer 204. Since the rest of the configuration is the same as that of the first embodiment, the same reference numerals are given and the description thereof is omitted. The signal of the first semiconductor wafer 602 is sequentially transmitted to the first solder ball 1〇2〇 via the third circuit layer 702 and the fifth circuit layer 902, thereby being transmitted to the outside of the substrate structure, which is generated by the first semiconductor wafer 602. The heat is sequentially transmitted to the second solder ball 104〇 via the thermal conductive paste 505, the thermal conductive material 502, the second wiring layer 204, the fourth wiring layer 704, and the sixth wiring layer 904, and heat is transferred to the outside of the substrate structure for heat dissipation. . The signal of the second semiconductor wafer 6〇4 is sequentially transmitted to the second solder ball 1040 via the fourth circuit layer 704 and the sixth circuit layer 904, thereby being transmitted to the outside of the substrate structure, and the second 201042735 semiconductor wafer 604 is generated. The heat is sequentially transmitted to the first solder ball 1020 via the thermal conductive paste 5〇5, the thermal conductive material 502', the first wiring layer 2〇2, the third wiring layer 7〇2, and the fifth wiring layer 902, and the heat is transferred to In addition to the substrate structure, heat is dissipated. Fig. 5 is a schematic view showing a fourth embodiment of the substrate structure of the buried wafer of the present invention. The difference between the fourth embodiment and the third embodiment is that the metal through hole 206 ′′ is penetrated through the carrier plate 1 , the first circuit layer 2 , the first insulating layer 302 , the second circuit layer 702 , and the first circuit layer. .204, the second insulating layer 304, the fourth wiring layer 704, the metal via 206, 'connects the third circuit layer 〇2, the first circuit layer 202, the second circuit layer 204, and the fourth circuit layer 704, The metal via 206'' is filled with a thermally conductive material: 5〇2. The metal via hole 11 () is filled with the filling resin 402, and the first semiconductor wafer.6〇2 is disposed on the third wiring layer 702, and is fixed to the third wiring layer 7〇2 and the heat conductive material via the thermal conductive adhesive 505. At the interface of 502 ′, the fifth circuit layer 9 〇 2 is electrically connected to the first semiconductor wafer 602 ′. The second semiconductor wafer 6 〇 4 is fixed on the fourth circuit layer 704 via the thermal conductive adhesive 5 〇 5 , and the sixth circuit layer 904 Electrically connected to the second semiconductor wafer 604. Since the rest of the configuration is the same as that of the third embodiment, the same reference numerals are given and the description thereof is omitted. The signal of the first semiconductor wafer 602 is sequentially transmitted to the first solder ball 1020 via the fifth circuit layer 9〇2, thereby being transmitted to the outside of the substrate structure. The heat generated by the first semiconductor wafer 602 is sequentially transmitted via the thermal conductive paste 505. The heat conductive material 502 ′, the metal via 206 ′′, the fourth wiring layer 704 , and the sixth wiring layer 904 are transferred to the second solder ball 1 〇 4 ′′ to transfer heat to the outside of the substrate structure for heat dissipation. The signal of the second semiconductor wafer 604 is sequentially transmitted to the second solder ball through the sixth circuit layer 904, thereby being transferred to the outside of the base structure of the base 12 201042735, and the heat generated by the second semiconductor wafer 604 is sequentially processed. The heat transfer adhesive 505, the fourth circuit layer 704, the second circuit layer 204, the metal via hole 110, the first circuit layer 202, the third circuit layer 702, and the fifth circuit layer 902 are transferred to the first solder ball 1020, and the heat is transferred. Transfer to the outside of the substrate structure for heat dissipation. Fig. 6 is a schematic view showing a fifth embodiment of the substrate structure of the buried wafer of the present invention. The configuration of the fifth embodiment is similar to that of the fourth embodiment, except that the first semiconductor wafer 602 and the second semiconductor wafer 604 are both disposed under the first solder resist layer 920, and the first solder resist layer 920 covers the first semiconductor. The first solder ball 1020 is directly electrically connected to the first semiconductor wafer 602 and the second semiconductor wafer 604, and the metal via hole 110 of the fifth embodiment is filled with the filling resin 402. Since the rest of the configuration is the same as that of the fourth embodiment, the same reference numerals are given and the description thereof is omitted. The signal of the first semiconductor wafer 602 is directly transmitted to the first solder ball 1020, thereby being transmitted to the outside of the substrate structure, and the heat generated by the first semiconductor wafer 602 is sequentially passed through the thermal conductive paste 505, the fifth wiring layer 902, and the third. The wiring layer 702, the metal via hole 110, the fourth wiring layer 704, and the sixth wiring layer 904 are transferred to the second solder ball 1040 to transfer heat to the outside of the substrate structure for heat dissipation. The signal of the second semiconductor wafer 604 is directly transmitted to the first solder ball 1020, thereby being transmitted to the outside of the substrate structure, and the heat generated by the second semiconductor wafer 604 is sequentially passed through the thermal conductive adhesive 50.5, the fifth wiring layer 902, and the third circuit. The layer 702, the first wiring layer 202, the metal via 110, the second wiring layer 204, the fourth wiring layer 704, and the sixth wiring layer 904 are transferred to the second solder ball 1040, and heat is transferred to the outside of the substrate structure.散13 201042735 Hot. The substrate structure of the buried wafer of the present invention can be embedded in a plurality of active elements and arranged in different manners, whereby the package density can be increased. Further, the substrate structure of the embedded wafer of the present invention has a heat dissipation through hole in the structure, and the heat is discharged by the metal, so that there is no problem that the active element is buried in the substrate and cannot be dissipated by heat. Grouting, layer-adding structure, hole-filling plating, solder-proof layer coating and solder ball printing processes and methods are all well-known techniques. This article will not be described in detail, but only for the newly developed structure and production of this invention. The number of layers in the above embodiments is merely illustrative and is not intended to limit the invention. Actually, the number of adjustments may be increased or decreased depending on the product. The heat transfer grooves or through holes are adjusted according to the product. A variety of heat transfer grooves or through holes can be combined in the same structure, and the position can be adjusted according to the heat transfer formula. While the present invention has been described in its preferred embodiments, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. 14 201042735 [Simplified Schematic] FIG. 1 is a schematic view showing a conventional buried wafer substrate structure. Fig. 2 is a schematic view showing the first embodiment of the buried wafer substrate structure of the present invention. Fig. 3 is a schematic view showing a second embodiment of the buried wafer substrate structure of the present invention. Fig. 4 is a schematic view showing a third embodiment of the buried wafer substrate structure of the present invention. Fig. 5 is a schematic view showing a fourth embodiment of the buried wafer substrate structure of the present invention. Figure 6 is a schematic view showing a fifth embodiment of the buried wafer substrate structure of the present invention.
I主要元件符號說明】 10- 〜承載板 12- 〜盲凹槽 C〜半導體晶片 F- /黏著劑 20- 〜第一絕緣層 30, 〜第一線路層 32- 〜導電盲孔 40- 〜第二絕緣層 50- 〜第二線路層 60〜防鲜層 70 〜錫球 15 201042735 100〜 承載板 102〜 第一面 104〜 第二面 106〜 第一通孔 106’〜第一盲凹槽 106，，' 〜"第一通孔 108〜 第二通孔 108，， -第二盲凹槽 108，，' 〜第二通孔 110〜 金屬導通孔 2 02〜 第一線路層 204〜 第二線路層 206〜金屬通孔凹槽 206^ -金屬盲凹槽 206，， 〜金屬通孔 302〜 第一絕緣層 304〜 第二絕緣層 402〜 灌孔樹脂 502，， ""導熱材料 505〜 •導熱膠 602〜 第一半導體晶片 604〜 第二半導體晶片 702〜 '第三線路層 704〜 '第四線路層 706〜 '導盲孔 16 201042735 802〜第三絕緣層 804〜第四絕緣層 902〜第五線路層 904〜第六線路層 920〜第一防銲層 940〜第二防銲層 1020〜第一錫球 1040〜第二錫球I main component symbol description] 10-~ carrier plate 12-~ blind groove C~ semiconductor wafer F- / adhesive 20 - ~ first insulating layer 30, ~ first circuit layer 32 - ~ conductive blind hole 40 - ~ Two insulating layers 50 - ~ second circuit layer 60 ~ anti-fresh layer 70 ~ solder balls 15 201042735 100 ~ carrier plate 102 ~ first surface 104 ~ second surface 106 ~ first through hole 106' ~ first blind groove 106 ,, '~" first through hole 108~ second through hole 108,, - second blind groove 108,, 'to second through hole 110~ metal through hole 2 02~ first line layer 204 to second Circuit layer 206 to metal via recess 206^-metal blind recess 206, metal via 302~ first insulating layer 304~ second insulating layer 402~ potting resin 502, "" thermally conductive material 505 ~ • Thermal paste 602~ First semiconductor wafer 604~ Second semiconductor wafer 702~ 'Third wiring layer 704~' Fourth wiring layer 706~ 'Blind hole 16 201042735 802~3rd insulating layer 804~4th insulating layer 902 to fifth circuit layer 904 to sixth circuit layer 920 to first solder resist layer 9 40~second solder mask 1020~first tin ball 1040~second tin ball
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